diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 167 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 21 |
5 files changed, 194 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 6f1fb9e2..b2c143a6 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile | |||
@@ -14,6 +14,7 @@ obj-$(CONFIG_GK20A) += \ | |||
14 | ltc_gp10b.o \ | 14 | ltc_gp10b.o \ |
15 | mm_gp10b.o \ | 15 | mm_gp10b.o \ |
16 | fb_gp10b.o \ | 16 | fb_gp10b.o \ |
17 | pmu_gp10b.o \ | ||
17 | hal_gp10b.o | 18 | hal_gp10b.o |
18 | 19 | ||
19 | obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o | 20 | obj-$(CONFIG_TEGRA_GK20A) += platform_gp10b_tegra.o |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a739ce77..526caff1 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include "gp10b/ltc_gp10b.h" | 25 | #include "gp10b/ltc_gp10b.h" |
26 | #include "gp10b/mm_gp10b.h" | 26 | #include "gp10b/mm_gp10b.h" |
27 | #include "gp10b/fb_gp10b.h" | 27 | #include "gp10b/fb_gp10b.h" |
28 | #include "gp10b/pmu_gp10b.h" | ||
28 | 29 | ||
29 | #include "gm20b/gr_gm20b.h" | 30 | #include "gm20b/gr_gm20b.h" |
30 | #include "gm20b/gm20b_gating_reglist.h" | 31 | #include "gm20b/gm20b_gating_reglist.h" |
@@ -95,7 +96,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
95 | gm20b_init_fifo(gops); | 96 | gm20b_init_fifo(gops); |
96 | gm20b_init_gr_ctx(gops); | 97 | gm20b_init_gr_ctx(gops); |
97 | gp10b_init_mm(gops); | 98 | gp10b_init_mm(gops); |
98 | gm20b_init_pmu_ops(gops); | 99 | gp10b_init_pmu_ops(gops); |
99 | gm20b_init_clk_ops(gops); | 100 | gm20b_init_clk_ops(gops); |
100 | gops->name = "gp10b"; | 101 | gops->name = "gp10b"; |
101 | 102 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c index f199d569..0f2d290f 100644 --- a/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/gp10b/platform_gp10b_tegra.c | |||
@@ -81,6 +81,9 @@ static int gp10b_tegra_suspend(struct device *dev) | |||
81 | struct gk20a_platform t18x_gpu_tegra_platform = { | 81 | struct gk20a_platform t18x_gpu_tegra_platform = { |
82 | .has_syncpoints = true, | 82 | .has_syncpoints = true, |
83 | 83 | ||
84 | /* power management configuration */ | ||
85 | .enable_elpg = false, | ||
86 | |||
84 | .default_big_page_size = SZ_128K, | 87 | .default_big_page_size = SZ_128K, |
85 | 88 | ||
86 | .probe = gp10b_tegra_probe, | 89 | .probe = gp10b_tegra_probe, |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c new file mode 100644 index 00000000..3db0d4c3 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -0,0 +1,167 @@ | |||
1 | /* | ||
2 | * GP10B PMU | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/delay.h> /* for udelay */ | ||
17 | #include "gk20a/gk20a.h" | ||
18 | #include "gk20a/pmu_gk20a.h" | ||
19 | #include "gm20b/acr_gm20b.h" | ||
20 | #include "gm20b/pmu_gm20b.h" | ||
21 | |||
22 | #include "pmu_gp10b.h" | ||
23 | |||
24 | /*! | ||
25 | * Structure/object which single register write need to be done during PG init | ||
26 | * sequence to set PROD values. | ||
27 | */ | ||
28 | struct pg_init_sequence_list { | ||
29 | u32 regaddr; | ||
30 | u32 writeval; | ||
31 | }; | ||
32 | |||
33 | /* PROD settings for ELPG sequencing registers*/ | ||
34 | static struct pg_init_sequence_list _pginitseq_gm20b[] = { | ||
35 | { 0x0010ab10, 0x8180}, | ||
36 | { 0x0010e118, 0x83828180}, | ||
37 | { 0x0010e068, 0}, | ||
38 | { 0x0010e06c, 0x00000080}, | ||
39 | { 0x0010e06c, 0x00000081}, | ||
40 | { 0x0010e06c, 0x00000082}, | ||
41 | { 0x0010e06c, 0x00000083}, | ||
42 | { 0x0010e06c, 0x00000084}, | ||
43 | { 0x0010e06c, 0x00000085}, | ||
44 | { 0x0010e06c, 0x00000086}, | ||
45 | { 0x0010e06c, 0x00000087}, | ||
46 | { 0x0010e06c, 0x00000088}, | ||
47 | { 0x0010e06c, 0x00000089}, | ||
48 | { 0x0010e06c, 0x0000008a}, | ||
49 | { 0x0010e06c, 0x0000008b}, | ||
50 | { 0x0010e06c, 0x0000008c}, | ||
51 | { 0x0010e06c, 0x0000008d}, | ||
52 | { 0x0010e06c, 0x0000008e}, | ||
53 | { 0x0010e06c, 0x0000008f}, | ||
54 | { 0x0010e06c, 0x00000090}, | ||
55 | { 0x0010e06c, 0x00000091}, | ||
56 | { 0x0010e06c, 0x00000092}, | ||
57 | { 0x0010e06c, 0x00000093}, | ||
58 | { 0x0010e06c, 0x00000094}, | ||
59 | { 0x0010e06c, 0x00000095}, | ||
60 | { 0x0010e06c, 0x00000096}, | ||
61 | { 0x0010e06c, 0x00000097}, | ||
62 | { 0x0010e06c, 0x00000098}, | ||
63 | { 0x0010e06c, 0x00000099}, | ||
64 | { 0x0010e06c, 0x0000009a}, | ||
65 | { 0x0010e06c, 0x0000009b}, | ||
66 | { 0x0010e06c, 0x00000000}, | ||
67 | { 0x0010e06c, 0x00000000}, | ||
68 | { 0x0010e06c, 0x00000000}, | ||
69 | { 0x0010e06c, 0x00000000}, | ||
70 | { 0x0010e06c, 0x00000000}, | ||
71 | { 0x0010e06c, 0x00000000}, | ||
72 | { 0x0010e06c, 0x00000000}, | ||
73 | { 0x0010e06c, 0x00000000}, | ||
74 | { 0x0010e06c, 0x00000000}, | ||
75 | { 0x0010e06c, 0x00000000}, | ||
76 | { 0x0010e06c, 0x00000000}, | ||
77 | { 0x0010e06c, 0x00000000}, | ||
78 | { 0x0010e06c, 0x00000000}, | ||
79 | { 0x0010e06c, 0x00000000}, | ||
80 | { 0x0010e06c, 0x00000000}, | ||
81 | { 0x0010e06c, 0x00000000}, | ||
82 | { 0x0010e06c, 0x00000000}, | ||
83 | { 0x0010e06c, 0x00000000}, | ||
84 | { 0x0010e06c, 0x00000000}, | ||
85 | { 0x0010e06c, 0x00000000}, | ||
86 | { 0x0010e06c, 0x00000000}, | ||
87 | { 0x0010e06c, 0x00000000}, | ||
88 | { 0x0010e06c, 0x00000000}, | ||
89 | { 0x0010e06c, 0x00000000}, | ||
90 | { 0x0010e06c, 0x00000000}, | ||
91 | { 0x0010e06c, 0x00000000}, | ||
92 | { 0x0010e06c, 0x00000000}, | ||
93 | { 0x0010e06c, 0x00000000}, | ||
94 | { 0x0010e06c, 0x00000000}, | ||
95 | { 0x0010e06c, 0x00000000}, | ||
96 | { 0x0010e06c, 0x00000000}, | ||
97 | { 0x0010e06c, 0x00000000}, | ||
98 | { 0x0010e06c, 0x00000000}, | ||
99 | { 0x0010e06c, 0x00000000}, | ||
100 | { 0x0010e06c, 0x00000000}, | ||
101 | { 0x0010e06c, 0x00000000}, | ||
102 | { 0x0010e06c, 0x00000000}, | ||
103 | { 0x0010e06c, 0x00000000}, | ||
104 | { 0x0010ab14, 0x00000000}, | ||
105 | { 0x0010ab18, 0x00000000}, | ||
106 | { 0x0010e024, 0x00000000}, | ||
107 | { 0x0010e028, 0x00000000}, | ||
108 | { 0x0010e11c, 0x00000000}, | ||
109 | { 0x0010e120, 0x00000000}, | ||
110 | { 0x0010ab1c, 0x02010155}, | ||
111 | { 0x0010e020, 0x001b1b55}, | ||
112 | { 0x0010e124, 0x01030355}, | ||
113 | { 0x0010ab20, 0x89abcdef}, | ||
114 | { 0x0010ab24, 0x00000000}, | ||
115 | { 0x0010e02c, 0x89abcdef}, | ||
116 | { 0x0010e030, 0x00000000}, | ||
117 | { 0x0010e128, 0x89abcdef}, | ||
118 | { 0x0010e12c, 0x00000000}, | ||
119 | { 0x0010ab28, 0x74444444}, | ||
120 | { 0x0010ab2c, 0x70000000}, | ||
121 | { 0x0010e034, 0x74444444}, | ||
122 | { 0x0010e038, 0x70000000}, | ||
123 | { 0x0010e130, 0x74444444}, | ||
124 | { 0x0010e134, 0x70000000}, | ||
125 | { 0x0010ab30, 0x00000000}, | ||
126 | { 0x0010ab34, 0x00000001}, | ||
127 | { 0x00020004, 0x00000000}, | ||
128 | { 0x0010e138, 0x00000000}, | ||
129 | { 0x0010e040, 0x00000000}, | ||
130 | }; | ||
131 | |||
132 | static int gp10b_pmu_setup_elpg(struct gk20a *g) | ||
133 | { | ||
134 | int ret = 0; | ||
135 | u32 reg_writes; | ||
136 | u32 index; | ||
137 | |||
138 | gk20a_dbg_fn(""); | ||
139 | |||
140 | if (g->elpg_enabled) { | ||
141 | reg_writes = ((sizeof(_pginitseq_gm20b) / | ||
142 | sizeof((_pginitseq_gm20b)[0]))); | ||
143 | /* Initialize registers with production values*/ | ||
144 | for (index = 0; index < reg_writes; index++) { | ||
145 | gk20a_writel(g, _pginitseq_gm20b[index].regaddr, | ||
146 | _pginitseq_gm20b[index].writeval); | ||
147 | } | ||
148 | } | ||
149 | |||
150 | gk20a_dbg_fn("done"); | ||
151 | return ret; | ||
152 | } | ||
153 | |||
154 | void gp10b_init_pmu_ops(struct gpu_ops *gops) | ||
155 | { | ||
156 | if (gops->privsecurity) { | ||
157 | gm20b_init_secure_pmu(gops); | ||
158 | gops->pmu.init_wpr_region = NULL; | ||
159 | } else { | ||
160 | gk20a_init_pmu_ops(gops); | ||
161 | gops->pmu.init_wpr_region = NULL; | ||
162 | } | ||
163 | gops->pmu.pmu_setup_elpg = gp10b_pmu_setup_elpg; | ||
164 | gops->pmu.lspmuwprinitdone = false; | ||
165 | gops->pmu.fecsbootstrapdone = false; | ||
166 | gops->pmu.fecsrecoveryinprogress = 0; | ||
167 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h new file mode 100644 index 00000000..f61f6a93 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | |||
@@ -0,0 +1,21 @@ | |||
1 | /* | ||
2 | * GP10B PMU | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef __PMU_GP10B_H_ | ||
17 | #define __PMU_GP10B_H_ | ||
18 | |||
19 | void gp10b_init_pmu_ops(struct gpu_ops *gops); | ||
20 | |||
21 | #endif /*__PMU_GP10B_H_*/ | ||