diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | 38 |
6 files changed, 93 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cd121455..cc20fa43 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -397,6 +397,8 @@ static const struct gpu_ops gv100_ops = { | |||
397 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | 397 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, |
398 | .preempt_channel = gv11b_fifo_preempt_channel, | 398 | .preempt_channel = gv11b_fifo_preempt_channel, |
399 | .preempt_tsg = gv11b_fifo_preempt_tsg, | 399 | .preempt_tsg = gv11b_fifo_preempt_tsg, |
400 | .enable_tsg = gv11b_fifo_enable_tsg, | ||
401 | .disable_tsg = gk20a_disable_tsg, | ||
400 | .update_runlist = gk20a_fifo_update_runlist, | 402 | .update_runlist = gk20a_fifo_update_runlist, |
401 | .trigger_mmu_fault = NULL, | 403 | .trigger_mmu_fault = NULL, |
402 | .get_mmu_fault_info = NULL, | 404 | .get_mmu_fault_info = NULL, |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 80bb64a0..1d5e593c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -785,6 +785,21 @@ static int __locked_fifo_preempt_runlists(struct gk20a *g, u32 runlists_mask) | |||
785 | return ret; | 785 | return ret; |
786 | } | 786 | } |
787 | 787 | ||
788 | /* TSG enable sequence applicable for Volta and onwards */ | ||
789 | int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg) | ||
790 | { | ||
791 | struct gk20a *g = tsg->g; | ||
792 | struct channel_gk20a *ch; | ||
793 | |||
794 | down_read(&tsg->ch_list_lock); | ||
795 | nvgpu_list_for_each_entry(ch, &tsg->ch_list, channel_gk20a, ch_entry) { | ||
796 | g->ops.fifo.enable_channel(ch); | ||
797 | } | ||
798 | up_read(&tsg->ch_list_lock); | ||
799 | |||
800 | return 0; | ||
801 | } | ||
802 | |||
788 | int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) | 803 | int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid) |
789 | { | 804 | { |
790 | struct fifo_gk20a *f = &g->fifo; | 805 | struct fifo_gk20a *f = &g->fifo; |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 3fb2f6e9..e576714c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | |||
@@ -69,6 +69,7 @@ int gv11b_fifo_is_preempt_pending(struct gk20a *g, u32 id, | |||
69 | unsigned int id_type, unsigned int timeout_rc_type); | 69 | unsigned int id_type, unsigned int timeout_rc_type); |
70 | int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid); | 70 | int gv11b_fifo_preempt_channel(struct gk20a *g, u32 chid); |
71 | int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); | 71 | int gv11b_fifo_preempt_tsg(struct gk20a *g, u32 tsgid); |
72 | int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg); | ||
72 | int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, | 73 | int gv11b_fifo_preempt_ch_tsg(struct gk20a *g, u32 id, |
73 | unsigned int id_type, unsigned int timeout_rc_type); | 74 | unsigned int id_type, unsigned int timeout_rc_type); |
74 | void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, | 75 | void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index e9053081..947ac503 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -430,6 +430,8 @@ static const struct gpu_ops gv11b_ops = { | |||
430 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | 430 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, |
431 | .preempt_channel = gv11b_fifo_preempt_channel, | 431 | .preempt_channel = gv11b_fifo_preempt_channel, |
432 | .preempt_tsg = gv11b_fifo_preempt_tsg, | 432 | .preempt_tsg = gv11b_fifo_preempt_tsg, |
433 | .enable_tsg = gv11b_fifo_enable_tsg, | ||
434 | .disable_tsg = gk20a_disable_tsg, | ||
433 | .update_runlist = gk20a_fifo_update_runlist, | 435 | .update_runlist = gk20a_fifo_update_runlist, |
434 | .trigger_mmu_fault = NULL, | 436 | .trigger_mmu_fault = NULL, |
435 | .get_mmu_fault_info = NULL, | 437 | .get_mmu_fault_info = NULL, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h index f64f542c..664c0b80 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ccsr_gv100.h | |||
@@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r) | |||
110 | { | 110 | { |
111 | return (r >> 24) & 0xf; | 111 | return (r >> 24) & 0xf; |
112 | } | 112 | } |
113 | static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | ||
114 | { | ||
115 | return 0x00000002; | ||
116 | } | ||
117 | static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) | ||
118 | { | ||
119 | return 0x00000004; | ||
120 | } | ||
121 | static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) | ||
122 | { | ||
123 | return 0x0000000a; | ||
124 | } | ||
125 | static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) | ||
126 | { | ||
127 | return 0x0000000b; | ||
128 | } | ||
129 | static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) | ||
130 | { | ||
131 | return 0x0000000c; | ||
132 | } | ||
133 | static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) | ||
134 | { | ||
135 | return 0x0000000d; | ||
136 | } | ||
137 | static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) | ||
138 | { | ||
139 | return 0x0000000e; | ||
140 | } | ||
141 | static inline u32 ccsr_channel_next_v(u32 r) | ||
142 | { | ||
143 | return (r >> 1) & 0x1; | ||
144 | } | ||
145 | static inline u32 ccsr_channel_next_true_v(void) | ||
146 | { | ||
147 | return 0x00000001; | ||
148 | } | ||
113 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) | 149 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) |
114 | { | 150 | { |
115 | return (v & 0x1) << 22; | 151 | return (v & 0x1) << 22; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h index 618c4806..7e30c34b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ccsr_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -110,6 +110,42 @@ static inline u32 ccsr_channel_status_v(u32 r) | |||
110 | { | 110 | { |
111 | return (r >> 24) & 0xf; | 111 | return (r >> 24) & 0xf; |
112 | } | 112 | } |
113 | static inline u32 ccsr_channel_status_pending_ctx_reload_v(void) | ||
114 | { | ||
115 | return 0x00000002; | ||
116 | } | ||
117 | static inline u32 ccsr_channel_status_pending_acq_ctx_reload_v(void) | ||
118 | { | ||
119 | return 0x00000004; | ||
120 | } | ||
121 | static inline u32 ccsr_channel_status_on_pbdma_ctx_reload_v(void) | ||
122 | { | ||
123 | return 0x0000000a; | ||
124 | } | ||
125 | static inline u32 ccsr_channel_status_on_pbdma_and_eng_ctx_reload_v(void) | ||
126 | { | ||
127 | return 0x0000000b; | ||
128 | } | ||
129 | static inline u32 ccsr_channel_status_on_eng_ctx_reload_v(void) | ||
130 | { | ||
131 | return 0x0000000c; | ||
132 | } | ||
133 | static inline u32 ccsr_channel_status_on_eng_pending_ctx_reload_v(void) | ||
134 | { | ||
135 | return 0x0000000d; | ||
136 | } | ||
137 | static inline u32 ccsr_channel_status_on_eng_pending_acq_ctx_reload_v(void) | ||
138 | { | ||
139 | return 0x0000000e; | ||
140 | } | ||
141 | static inline u32 ccsr_channel_next_v(u32 r) | ||
142 | { | ||
143 | return (r >> 1) & 0x1; | ||
144 | } | ||
145 | static inline u32 ccsr_channel_next_true_v(void) | ||
146 | { | ||
147 | return 0x00000001; | ||
148 | } | ||
113 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) | 149 | static inline u32 ccsr_channel_pbdma_faulted_f(u32 v) |
114 | { | 150 | { |
115 | return (v & 0x1) << 22; | 151 | return (v & 0x1) << 22; |