diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 68 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gsp_gv100.c | 72 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/gsp_gv100.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h | 28 |
7 files changed, 181 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 2a4ee6d5..f5ae565a 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -67,6 +67,7 @@ static get_ucode_details pmu_acr_supp_ucode_list[] = { | |||
67 | pmu_ucode_details, | 67 | pmu_ucode_details, |
68 | fecs_ucode_details, | 68 | fecs_ucode_details, |
69 | gpccs_ucode_details, | 69 | gpccs_ucode_details, |
70 | sec2_ucode_details, | ||
70 | }; | 71 | }; |
71 | 72 | ||
72 | void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) | 73 | void gp106_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) |
@@ -388,6 +389,73 @@ rel_sig: | |||
388 | return err; | 389 | return err; |
389 | } | 390 | } |
390 | 391 | ||
392 | int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | ||
393 | { | ||
394 | struct nvgpu_firmware *sec2_fw, *sec2_desc, *sec2_sig; | ||
395 | struct pmu_ucode_desc_v1 *desc; | ||
396 | struct lsf_ucode_desc_v1 *lsf_desc; | ||
397 | u32 *ucode_image; | ||
398 | int err = 0; | ||
399 | |||
400 | gp106_dbg_pmu(g, "requesting SEC2 ucode in %s", g->name); | ||
401 | sec2_fw = nvgpu_request_firmware(g, LSF_SEC2_UCODE_IMAGE_BIN, | ||
402 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | ||
403 | if (sec2_fw == NULL) { | ||
404 | nvgpu_err(g, "failed to load sec2 ucode!!"); | ||
405 | return -ENOENT; | ||
406 | } | ||
407 | |||
408 | ucode_image = (u32 *)sec2_fw->data; | ||
409 | |||
410 | gp106_dbg_pmu(g, "requesting SEC2 ucode desc in %s", g->name); | ||
411 | sec2_desc = nvgpu_request_firmware(g, LSF_SEC2_UCODE_DESC_BIN, | ||
412 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | ||
413 | if (sec2_desc == NULL) { | ||
414 | nvgpu_err(g, "failed to load SEC2 ucode desc!!"); | ||
415 | err = -ENOENT; | ||
416 | goto release_img_fw; | ||
417 | } | ||
418 | |||
419 | desc = (struct pmu_ucode_desc_v1 *)sec2_desc->data; | ||
420 | |||
421 | sec2_sig = nvgpu_request_firmware(g, LSF_SEC2_UCODE_SIG_BIN, | ||
422 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | ||
423 | if (sec2_sig == NULL) { | ||
424 | nvgpu_err(g, "failed to load SEC2 sig!!"); | ||
425 | err = -ENOENT; | ||
426 | goto release_desc; | ||
427 | } | ||
428 | |||
429 | lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc_v1)); | ||
430 | if (lsf_desc == NULL) { | ||
431 | err = -ENOMEM; | ||
432 | goto release_sig; | ||
433 | } | ||
434 | |||
435 | memcpy(lsf_desc, (void *)sec2_sig->data, | ||
436 | min_t(size_t, sizeof(*lsf_desc), sec2_sig->size)); | ||
437 | |||
438 | lsf_desc->falcon_id = LSF_FALCON_ID_SEC2; | ||
439 | |||
440 | p_img->desc = desc; | ||
441 | p_img->data = ucode_image; | ||
442 | p_img->data_size = desc->app_start_offset + desc->app_size; | ||
443 | p_img->fw_ver = NULL; | ||
444 | p_img->header = NULL; | ||
445 | p_img->lsf_desc = (struct lsf_ucode_desc_v1 *)lsf_desc; | ||
446 | |||
447 | gp106_dbg_pmu(g, "requesting SEC2 ucode in %s done", g->name); | ||
448 | |||
449 | return err; | ||
450 | release_sig: | ||
451 | nvgpu_release_firmware(g, sec2_sig); | ||
452 | release_desc: | ||
453 | nvgpu_release_firmware(g, sec2_desc); | ||
454 | release_img_fw: | ||
455 | nvgpu_release_firmware(g, sec2_fw); | ||
456 | return err; | ||
457 | } | ||
458 | |||
391 | /* | 459 | /* |
392 | * Discover all supported shared data falcon SUB WPRs | 460 | * Discover all supported shared data falcon SUB WPRs |
393 | */ | 461 | */ |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h index ad004bf0..0fe3d119 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h | |||
@@ -53,6 +53,7 @@ int fecs_ucode_details(struct gk20a *g, | |||
53 | struct flcn_ucode_img_v1 *p_img); | 53 | struct flcn_ucode_img_v1 *p_img); |
54 | int gpccs_ucode_details(struct gk20a *g, | 54 | int gpccs_ucode_details(struct gk20a *g, |
55 | struct flcn_ucode_img_v1 *p_img); | 55 | struct flcn_ucode_img_v1 *p_img); |
56 | int sec2_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img); | ||
56 | int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, | 57 | int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr_v1 *plsfm, |
57 | struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id); | 58 | struct flcn_ucode_img_v1 *ucode_image, u32 falcon_id); |
58 | int lsfm_discover_ucode_images(struct gk20a *g, | 59 | int lsfm_discover_ucode_images(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gv100/gsp_gv100.c b/drivers/gpu/nvgpu/gv100/gsp_gv100.c index 6ea7ab71..d6d01b7f 100644 --- a/drivers/gpu/nvgpu/gv100/gsp_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gsp_gv100.c | |||
@@ -39,3 +39,75 @@ int gv100_gsp_reset(struct gk20a *g) | |||
39 | 39 | ||
40 | return 0; | 40 | return 0; |
41 | } | 41 | } |
42 | |||
43 | static int gsp_flcn_bl_bootstrap(struct gk20a *g, | ||
44 | struct nvgpu_falcon_bl_info *bl_info) | ||
45 | { | ||
46 | struct mm_gk20a *mm = &g->mm; | ||
47 | u32 data = 0; | ||
48 | u32 status = 0; | ||
49 | |||
50 | gk20a_writel(g, pgsp_falcon_itfen_r(), | ||
51 | gk20a_readl(g, pgsp_falcon_itfen_r()) | | ||
52 | pgsp_falcon_itfen_ctxen_enable_f()); | ||
53 | |||
54 | gk20a_writel(g, pgsp_falcon_nxtctx_r(), | ||
55 | pgsp_falcon_nxtctx_ctxptr_f( | ||
56 | nvgpu_inst_block_addr(g, &mm->pmu.inst_block) >> 12U) | | ||
57 | pgsp_falcon_nxtctx_ctxvalid_f(1) | | ||
58 | nvgpu_aperture_mask(g, &mm->pmu.inst_block, | ||
59 | pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(), | ||
60 | pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(), | ||
61 | pgsp_falcon_nxtctx_ctxtgt_fb_f())); | ||
62 | |||
63 | data = gk20a_readl(g, pgsp_falcon_debug1_r()); | ||
64 | data |= pgsp_falcon_debug1_ctxsw_mode_m(); | ||
65 | gk20a_writel(g, pgsp_falcon_debug1_r(), data); | ||
66 | |||
67 | data = gk20a_readl(g, pgsp_falcon_engctl_r()); | ||
68 | data |= pgsp_falcon_engctl_switch_context_true_f(); | ||
69 | gk20a_writel(g, pgsp_falcon_engctl_r(), data); | ||
70 | |||
71 | status = nvgpu_flcn_bl_bootstrap(&g->gsp_flcn, bl_info); | ||
72 | |||
73 | return status; | ||
74 | } | ||
75 | |||
76 | int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g, | ||
77 | struct hs_acr *acr_desc, | ||
78 | struct nvgpu_falcon_bl_info *bl_info) | ||
79 | { | ||
80 | u32 data = 0; | ||
81 | int err = 0; | ||
82 | |||
83 | err = nvgpu_flcn_reset(&g->gsp_flcn); | ||
84 | if (err != 0) { | ||
85 | goto exit; | ||
86 | } | ||
87 | |||
88 | data = gk20a_readl(g, pgsp_fbif_ctl_r()); | ||
89 | data |= pgsp_fbif_ctl_allow_phys_no_ctx_allow_f(); | ||
90 | gk20a_writel(g, pgsp_fbif_ctl_r(), data); | ||
91 | |||
92 | /* setup apertures - virtual */ | ||
93 | gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
94 | pgsp_fbif_transcfg_mem_type_physical_f() | | ||
95 | pgsp_fbif_transcfg_target_local_fb_f()); | ||
96 | gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
97 | pgsp_fbif_transcfg_mem_type_virtual_f()); | ||
98 | /* setup apertures - physical */ | ||
99 | gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
100 | pgsp_fbif_transcfg_mem_type_physical_f() | | ||
101 | pgsp_fbif_transcfg_target_local_fb_f()); | ||
102 | gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
103 | pgsp_fbif_transcfg_mem_type_physical_f() | | ||
104 | pgsp_fbif_transcfg_target_coherent_sysmem_f()); | ||
105 | gk20a_writel(g, pgsp_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
106 | pgsp_fbif_transcfg_mem_type_physical_f() | | ||
107 | pgsp_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
108 | |||
109 | err = gsp_flcn_bl_bootstrap(g, bl_info); | ||
110 | |||
111 | exit: | ||
112 | return err; | ||
113 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/gsp_gv100.h b/drivers/gpu/nvgpu/gv100/gsp_gv100.h index a4363d73..71d4564e 100644 --- a/drivers/gpu/nvgpu/gv100/gsp_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gsp_gv100.h | |||
@@ -24,5 +24,8 @@ | |||
24 | #define GSP_GV100_H | 24 | #define GSP_GV100_H |
25 | 25 | ||
26 | int gv100_gsp_reset(struct gk20a *g); | 26 | int gv100_gsp_reset(struct gk20a *g); |
27 | int gv100_gsp_setup_hw_and_bl_bootstrap(struct gk20a *g, | ||
28 | struct hs_acr *acr_desc, | ||
29 | struct nvgpu_falcon_bl_info *bl_info); | ||
27 | 30 | ||
28 | #endif /*GSP_GV100_H */ | 31 | #endif /*GSP_GV100_H */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h index 90d2d20d..f9d9e2a8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | |||
@@ -48,7 +48,7 @@ | |||
48 | * Defines a common Light Secure Falcon identifier. | 48 | * Defines a common Light Secure Falcon identifier. |
49 | */ | 49 | */ |
50 | #define LSF_FALCON_ID_PMU (0) | 50 | #define LSF_FALCON_ID_PMU (0) |
51 | #define LSF_FALCON_ID_RESERVED (1) | 51 | #define LSF_FALCON_ID_GSPLITE (1) |
52 | #define LSF_FALCON_ID_FECS (2) | 52 | #define LSF_FALCON_ID_FECS (2) |
53 | #define LSF_FALCON_ID_GPCCS (3) | 53 | #define LSF_FALCON_ID_GPCCS (3) |
54 | #define LSF_FALCON_ID_SEC2 (7) | 54 | #define LSF_FALCON_ID_SEC2 (7) |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h index 5fb26e1a..ba658c95 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h | |||
@@ -40,6 +40,14 @@ struct nvgpu_acr; | |||
40 | 40 | ||
41 | #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" | 41 | #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" |
42 | #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" | 42 | #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" |
43 | #define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" | ||
44 | #define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin" | ||
45 | #define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin" | ||
46 | #define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin" | ||
47 | |||
48 | #define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin" | ||
49 | #define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin" | ||
50 | #define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin" | ||
43 | 51 | ||
44 | #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ | 52 | #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ |
45 | 53 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h index f0f5bc26..34d0eae8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_pgsp_gv100.h | |||
@@ -252,6 +252,26 @@ static inline u32 pgsp_falcon_nxtctx_r(void) | |||
252 | { | 252 | { |
253 | return 0x00110054U; | 253 | return 0x00110054U; |
254 | } | 254 | } |
255 | static inline u32 pgsp_falcon_nxtctx_ctxptr_f(u32 v) | ||
256 | { | ||
257 | return (v & 0xfffffffU) << 0U; | ||
258 | } | ||
259 | static inline u32 pgsp_falcon_nxtctx_ctxtgt_fb_f(void) | ||
260 | { | ||
261 | return 0x0U; | ||
262 | } | ||
263 | static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_coh_f(void) | ||
264 | { | ||
265 | return 0x20000000U; | ||
266 | } | ||
267 | static inline u32 pgsp_falcon_nxtctx_ctxtgt_sys_ncoh_f(void) | ||
268 | { | ||
269 | return 0x30000000U; | ||
270 | } | ||
271 | static inline u32 pgsp_falcon_nxtctx_ctxvalid_f(u32 v) | ||
272 | { | ||
273 | return (v & 0x1U) << 30U; | ||
274 | } | ||
255 | static inline u32 pgsp_falcon_mailbox0_r(void) | 275 | static inline u32 pgsp_falcon_mailbox0_r(void) |
256 | { | 276 | { |
257 | return 0x00110040U; | 277 | return 0x00110040U; |
@@ -288,6 +308,14 @@ static inline u32 pgsp_falcon_engctl_r(void) | |||
288 | { | 308 | { |
289 | return 0x001100a4U; | 309 | return 0x001100a4U; |
290 | } | 310 | } |
311 | static inline u32 pgsp_falcon_engctl_switch_context_true_f(void) | ||
312 | { | ||
313 | return 0x8U; | ||
314 | } | ||
315 | static inline u32 pgsp_falcon_engctl_switch_context_false_f(void) | ||
316 | { | ||
317 | return 0x0U; | ||
318 | } | ||
291 | static inline u32 pgsp_falcon_cpuctl_r(void) | 319 | static inline u32 pgsp_falcon_cpuctl_r(void) |
292 | { | 320 | { |
293 | return 0x00110100U; | 321 | return 0x00110100U; |