diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 41 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 14 |
6 files changed, 93 insertions, 66 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 41e394f9..8e37a709 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -357,6 +357,24 @@ void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn) | |||
357 | flcn->flcn_id); | 357 | flcn->flcn_id); |
358 | } | 358 | } |
359 | 359 | ||
360 | int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn, | ||
361 | struct nvgpu_falcon_bl_info *bl_info) | ||
362 | { | ||
363 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | ||
364 | int status = 0; | ||
365 | |||
366 | if (flcn_ops->bl_bootstrap != NULL) { | ||
367 | status = flcn_ops->bl_bootstrap(flcn, bl_info); | ||
368 | } | ||
369 | else { | ||
370 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | ||
371 | flcn->flcn_id); | ||
372 | status = -EINVAL; | ||
373 | } | ||
374 | |||
375 | return status; | ||
376 | } | ||
377 | |||
360 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) | 378 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) |
361 | { | 379 | { |
362 | struct nvgpu_falcon *flcn = NULL; | 380 | struct nvgpu_falcon *flcn = NULL; |
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 83850a19..520d9bb2 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | |||
@@ -432,6 +432,46 @@ static void gk20a_falcon_mailbox_write(struct nvgpu_falcon *flcn, | |||
432 | nvgpu_err(g, "incorrect mailbox id %d", mailbox_index); | 432 | nvgpu_err(g, "incorrect mailbox id %d", mailbox_index); |
433 | } | 433 | } |
434 | 434 | ||
435 | static int gk20a_falcon_bl_bootstrap(struct nvgpu_falcon *flcn, | ||
436 | struct nvgpu_falcon_bl_info *bl_info) | ||
437 | { | ||
438 | struct gk20a *g = flcn->g; | ||
439 | u32 base_addr = flcn->flcn_base; | ||
440 | u32 virt_addr = 0; | ||
441 | u32 dst = 0; | ||
442 | int err = 0; | ||
443 | |||
444 | /*copy bootloader interface structure to dmem*/ | ||
445 | err = gk20a_flcn_copy_to_dmem(flcn, 0, (u8 *)bl_info->bl_desc, | ||
446 | bl_info->bl_desc_size, (u8)0); | ||
447 | if (err != 0) { | ||
448 | goto exit; | ||
449 | } | ||
450 | |||
451 | /* copy bootloader to TOP of IMEM */ | ||
452 | dst = (falcon_falcon_hwcfg_imem_size_v(gk20a_readl(g, | ||
453 | base_addr + falcon_falcon_hwcfg_r())) << 8) - bl_info->bl_size; | ||
454 | |||
455 | err = gk20a_flcn_copy_to_imem(flcn, dst, (u8 *)(bl_info->bl_src), | ||
456 | bl_info->bl_size, (u8)0, false, bl_info->bl_start_tag); | ||
457 | if (err != 0) { | ||
458 | goto exit; | ||
459 | } | ||
460 | |||
461 | gk20a_falcon_mailbox_write(flcn, FALCON_MAILBOX_0, 0xDEADA5A5U); | ||
462 | |||
463 | virt_addr = bl_info->bl_start_tag << 8; | ||
464 | |||
465 | err = gk20a_falcon_bootstrap(flcn, virt_addr); | ||
466 | |||
467 | exit: | ||
468 | if (err != 0) { | ||
469 | nvgpu_err(g, "falcon id-0x%x bootstrap failed", flcn->flcn_id); | ||
470 | } | ||
471 | |||
472 | return err; | ||
473 | } | ||
474 | |||
435 | static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn) | 475 | static void gk20a_falcon_dump_imblk(struct nvgpu_falcon *flcn) |
436 | { | 476 | { |
437 | struct gk20a *g = flcn->g; | 477 | struct gk20a *g = flcn->g; |
@@ -644,6 +684,7 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn) | |||
644 | flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats; | 684 | flcn_ops->dump_falcon_stats = gk20a_falcon_dump_stats; |
645 | flcn_ops->mailbox_read = gk20a_falcon_mailbox_read; | 685 | flcn_ops->mailbox_read = gk20a_falcon_mailbox_read; |
646 | flcn_ops->mailbox_write = gk20a_falcon_mailbox_write; | 686 | flcn_ops->mailbox_write = gk20a_falcon_mailbox_write; |
687 | flcn_ops->bl_bootstrap = gk20a_falcon_bl_bootstrap; | ||
647 | 688 | ||
648 | gk20a_falcon_engine_dependency_ops(flcn); | 689 | gk20a_falcon_engine_dependency_ops(flcn); |
649 | } | 690 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 615b6b46..1694a1ad 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1165,11 +1165,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, | |||
1165 | struct flcn_bl_dmem_desc *pbl_desc, u32 bl_sz) | 1165 | struct flcn_bl_dmem_desc *pbl_desc, u32 bl_sz) |
1166 | { | 1166 | { |
1167 | struct gk20a *g = gk20a_from_pmu(pmu); | 1167 | struct gk20a *g = gk20a_from_pmu(pmu); |
1168 | struct acr_desc *acr = &g->acr; | ||
1169 | struct mm_gk20a *mm = &g->mm; | 1168 | struct mm_gk20a *mm = &g->mm; |
1170 | u32 virt_addr = 0; | 1169 | struct nvgpu_falcon_bl_info bl_info; |
1171 | struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc; | ||
1172 | u32 dst; | ||
1173 | 1170 | ||
1174 | nvgpu_log_fn(g, " "); | 1171 | nvgpu_log_fn(g, " "); |
1175 | gk20a_writel(g, pwr_falcon_itfen_r(), | 1172 | gk20a_writel(g, pwr_falcon_itfen_r(), |
@@ -1181,23 +1178,12 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, | |||
1181 | pwr_pmu_new_instblk_valid_f(1) | | 1178 | pwr_pmu_new_instblk_valid_f(1) | |
1182 | pwr_pmu_new_instblk_target_sys_coh_f()); | 1179 | pwr_pmu_new_instblk_target_sys_coh_f()); |
1183 | 1180 | ||
1184 | /*copy bootloader interface structure to dmem*/ | 1181 | bl_info.bl_src = g->acr.hsbl_ucode.cpu_va; |
1185 | nvgpu_flcn_copy_to_dmem(pmu->flcn, 0, (u8 *)pbl_desc, | 1182 | bl_info.bl_desc = (u8 *)pbl_desc; |
1186 | sizeof(struct flcn_bl_dmem_desc), 0); | 1183 | bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc); |
1187 | 1184 | bl_info.bl_size = bl_sz; | |
1188 | /* copy bootloader to TOP of IMEM */ | 1185 | bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag; |
1189 | dst = (pwr_falcon_hwcfg_imem_size_v( | 1186 | nvgpu_flcn_bl_bootstrap(&g->pmu_flcn, &bl_info); |
1190 | gk20a_readl(g, pwr_falcon_hwcfg_r())) << 8) - bl_sz; | ||
1191 | |||
1192 | nvgpu_flcn_copy_to_imem(pmu->flcn, dst, | ||
1193 | (u8 *)(acr->hsbl_ucode.cpu_va), bl_sz, 0, 0, | ||
1194 | pmu_bl_gm10x_desc->bl_start_tag); | ||
1195 | |||
1196 | gm20b_dbg_pmu(g, "Before starting falcon with BL\n"); | ||
1197 | |||
1198 | virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8; | ||
1199 | |||
1200 | nvgpu_flcn_bootstrap(pmu->flcn, virt_addr); | ||
1201 | 1187 | ||
1202 | return 0; | 1188 | return 0; |
1203 | } | 1189 | } |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index d480d875..29fc2df0 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -82,12 +82,9 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, | |||
82 | void *desc, u32 bl_sz) | 82 | void *desc, u32 bl_sz) |
83 | { | 83 | { |
84 | struct gk20a *g = gk20a_from_pmu(pmu); | 84 | struct gk20a *g = gk20a_from_pmu(pmu); |
85 | struct acr_desc *acr = &g->acr; | ||
86 | struct mm_gk20a *mm = &g->mm; | 85 | struct mm_gk20a *mm = &g->mm; |
87 | u32 virt_addr = 0; | 86 | struct nvgpu_falcon_bl_info bl_info; |
88 | struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc; | ||
89 | u32 data = 0; | 87 | u32 data = 0; |
90 | u32 dst; | ||
91 | 88 | ||
92 | nvgpu_log_fn(g, " "); | 89 | nvgpu_log_fn(g, " "); |
93 | 90 | ||
@@ -113,25 +110,12 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, | |||
113 | data |= (1 << 3); | 110 | data |= (1 << 3); |
114 | gk20a_writel(g, psec_falcon_engctl_r(), data); | 111 | gk20a_writel(g, psec_falcon_engctl_r(), data); |
115 | 112 | ||
116 | /*copy bootloader interface structure to dmem*/ | 113 | bl_info.bl_src = g->acr.hsbl_ucode.cpu_va; |
117 | nvgpu_flcn_copy_to_dmem(&g->sec2_flcn, 0, (u8 *)desc, | 114 | bl_info.bl_desc = desc; |
118 | sizeof(struct flcn_bl_dmem_desc), 0); | 115 | bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); |
119 | 116 | bl_info.bl_size = bl_sz; | |
120 | /* copy bootloader to TOP of IMEM */ | 117 | bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag; |
121 | dst = (psec_falcon_hwcfg_imem_size_v( | 118 | nvgpu_flcn_bl_bootstrap(&g->sec2_flcn, &bl_info); |
122 | gk20a_readl(g, psec_falcon_hwcfg_r())) << 8) - bl_sz; | ||
123 | |||
124 | nvgpu_flcn_copy_to_imem(&g->sec2_flcn, dst, | ||
125 | (u8 *)(acr->hsbl_ucode.cpu_va), bl_sz, 0, 0, | ||
126 | pmu_bl_gm10x_desc->bl_start_tag); | ||
127 | |||
128 | gm20b_dbg_pmu(g, "Before starting falcon with BL\n"); | ||
129 | |||
130 | gk20a_writel(g, psec_falcon_mailbox0_r(), 0xDEADA5A5); | ||
131 | |||
132 | virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8; | ||
133 | |||
134 | nvgpu_flcn_bootstrap(&g->sec2_flcn, virt_addr); | ||
135 | 119 | ||
136 | return 0; | 120 | return 0; |
137 | } | 121 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index 673cb7f2..7fe3a2ea 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c | |||
@@ -206,11 +206,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, | |||
206 | struct flcn_bl_dmem_desc_v1 *pbl_desc, u32 bl_sz) | 206 | struct flcn_bl_dmem_desc_v1 *pbl_desc, u32 bl_sz) |
207 | { | 207 | { |
208 | struct gk20a *g = gk20a_from_pmu(pmu); | 208 | struct gk20a *g = gk20a_from_pmu(pmu); |
209 | struct acr_desc *acr = &g->acr; | ||
210 | struct mm_gk20a *mm = &g->mm; | 209 | struct mm_gk20a *mm = &g->mm; |
211 | u32 virt_addr = 0; | 210 | struct nvgpu_falcon_bl_info bl_info; |
212 | struct hsflcn_bl_desc *pmu_bl_gm10x_desc = g->acr.pmu_hsbl_desc; | ||
213 | u32 dst; | ||
214 | 211 | ||
215 | nvgpu_log_fn(g, " "); | 212 | nvgpu_log_fn(g, " "); |
216 | 213 | ||
@@ -225,23 +222,12 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, | |||
225 | pwr_pmu_new_instblk_target_sys_coh_f() : | 222 | pwr_pmu_new_instblk_target_sys_coh_f() : |
226 | pwr_pmu_new_instblk_target_sys_ncoh_f())) ; | 223 | pwr_pmu_new_instblk_target_sys_ncoh_f())) ; |
227 | 224 | ||
228 | /*copy bootloader interface structure to dmem*/ | 225 | bl_info.bl_src = g->acr.hsbl_ucode.cpu_va; |
229 | nvgpu_flcn_copy_to_dmem(pmu->flcn, 0, (u8 *)pbl_desc, | 226 | bl_info.bl_desc = (u8 *)pbl_desc; |
230 | sizeof(struct flcn_bl_dmem_desc_v1), 0); | 227 | bl_info.bl_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); |
231 | 228 | bl_info.bl_size = bl_sz; | |
232 | /* copy bootloader to TOP of IMEM */ | 229 | bl_info.bl_start_tag = g->acr.pmu_hsbl_desc->bl_start_tag; |
233 | dst = (pwr_falcon_hwcfg_imem_size_v( | 230 | nvgpu_flcn_bl_bootstrap(&g->pmu_flcn, &bl_info); |
234 | gk20a_readl(g, pwr_falcon_hwcfg_r())) << 8) - bl_sz; | ||
235 | |||
236 | nvgpu_flcn_copy_to_imem(pmu->flcn, dst, | ||
237 | (u8 *)(acr->hsbl_ucode.cpu_va), bl_sz, 0, 0, | ||
238 | pmu_bl_gm10x_desc->bl_start_tag); | ||
239 | |||
240 | gv11b_dbg_pmu(g, "Before starting falcon with BL\n"); | ||
241 | |||
242 | virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8; | ||
243 | |||
244 | nvgpu_flcn_bootstrap(pmu->flcn, virt_addr); | ||
245 | 231 | ||
246 | return 0; | 232 | return 0; |
247 | } | 233 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index a08c0c31..6cfb6670 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -165,6 +165,7 @@ struct nvgpu_falcon_dma_info { | |||
165 | 165 | ||
166 | struct gk20a; | 166 | struct gk20a; |
167 | struct nvgpu_falcon; | 167 | struct nvgpu_falcon; |
168 | struct nvgpu_falcon_bl_info; | ||
168 | 169 | ||
169 | struct nvgpu_falcon_version_ops { | 170 | struct nvgpu_falcon_version_ops { |
170 | void (*start_cpu_secure)(struct nvgpu_falcon *flcn); | 171 | void (*start_cpu_secure)(struct nvgpu_falcon *flcn); |
@@ -198,6 +199,16 @@ struct nvgpu_falcon_ops { | |||
198 | u32 data); | 199 | u32 data); |
199 | int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector); | 200 | int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector); |
200 | void (*dump_falcon_stats)(struct nvgpu_falcon *flcn); | 201 | void (*dump_falcon_stats)(struct nvgpu_falcon *flcn); |
202 | int (*bl_bootstrap)(struct nvgpu_falcon *flcn, | ||
203 | struct nvgpu_falcon_bl_info *bl_info); | ||
204 | }; | ||
205 | |||
206 | struct nvgpu_falcon_bl_info { | ||
207 | void *bl_src; | ||
208 | u8 *bl_desc; | ||
209 | u32 bl_desc_size; | ||
210 | u32 bl_size; | ||
211 | u32 bl_start_tag; | ||
201 | }; | 212 | }; |
202 | 213 | ||
203 | struct nvgpu_falcon { | 214 | struct nvgpu_falcon { |
@@ -245,8 +256,9 @@ int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector); | |||
245 | void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size); | 256 | void nvgpu_flcn_print_dmem(struct nvgpu_falcon *flcn, u32 src, u32 size); |
246 | void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size); | 257 | void nvgpu_flcn_print_imem(struct nvgpu_falcon *flcn, u32 src, u32 size); |
247 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); | 258 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); |
259 | int nvgpu_flcn_bl_bootstrap(struct nvgpu_falcon *flcn, | ||
260 | struct nvgpu_falcon_bl_info *bl_info); | ||
248 | 261 | ||
249 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); | 262 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); |
250 | 263 | ||
251 | |||
252 | #endif /* __FALCON_H__ */ | 264 | #endif /* __FALCON_H__ */ |