diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 22 |
5 files changed, 23 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 078a7158..04695d11 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -279,7 +279,7 @@ int gk20a_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, | |||
279 | return ret; | 279 | return ret; |
280 | } | 280 | } |
281 | 281 | ||
282 | static int init_engine_info(struct fifo_gk20a *f) | 282 | int gk20a_fifo_init_engine_info(struct fifo_gk20a *f) |
283 | { | 283 | { |
284 | struct gk20a *g = f->g; | 284 | struct gk20a *g = f->g; |
285 | struct device *d = dev_from_gk20a(g); | 285 | struct device *d = dev_from_gk20a(g); |
@@ -796,7 +796,7 @@ static int gk20a_init_fifo_setup_sw(struct gk20a *g) | |||
796 | for (i = 0; i < f->num_pbdma; ++i) | 796 | for (i = 0; i < f->num_pbdma; ++i) |
797 | f->pbdma_map[i] = gk20a_readl(g, fifo_pbdma_map_r(i)); | 797 | f->pbdma_map[i] = gk20a_readl(g, fifo_pbdma_map_r(i)); |
798 | 798 | ||
799 | init_engine_info(f); | 799 | g->ops.fifo.init_engine_info(f); |
800 | 800 | ||
801 | init_runlist(g, f); | 801 | init_runlist(g, f); |
802 | 802 | ||
@@ -3082,4 +3082,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
3082 | /* gk20a doesn't support device_info_data packet parsing */ | 3082 | /* gk20a doesn't support device_info_data packet parsing */ |
3083 | gops->fifo.device_info_data_parse = NULL; | 3083 | gops->fifo.device_info_data_parse = NULL; |
3084 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; | 3084 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; |
3085 | gops->fifo.init_engine_info = gk20a_fifo_init_engine_info; | ||
3085 | } | 3086 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index e6ae0bdc..3473bc78 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -250,4 +250,7 @@ bool gk20a_fifo_is_valid_runlist_id(struct gk20a *g, u32 runlist_id); | |||
250 | 250 | ||
251 | int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 hw_chid, | 251 | int gk20a_fifo_update_runlist_ids(struct gk20a *g, u32 runlist_ids, u32 hw_chid, |
252 | bool add, bool wait_for_finish); | 252 | bool add, bool wait_for_finish); |
253 | |||
254 | int gk20a_fifo_init_engine_info(struct fifo_gk20a *f); | ||
255 | |||
253 | #endif /*__GR_GK20A_H__*/ | 256 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 74ffab61..997da125 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -352,6 +352,7 @@ struct gpu_ops { | |||
352 | struct channel_gk20a *ch); | 352 | struct channel_gk20a *ch); |
353 | int (*tsg_unbind_channel)(struct channel_gk20a *ch); | 353 | int (*tsg_unbind_channel)(struct channel_gk20a *ch); |
354 | u32 (*eng_runlist_base_size)(void); | 354 | u32 (*eng_runlist_base_size)(void); |
355 | int (*init_engine_info)(struct fifo_gk20a *f); | ||
355 | } fifo; | 356 | } fifo; |
356 | struct pmu_v { | 357 | struct pmu_v { |
357 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 358 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 031c5bae..00db510a 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -155,4 +155,5 @@ void gm20b_init_fifo(struct gpu_ops *gops) | |||
155 | gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type; | 155 | gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type; |
156 | gops->fifo.device_info_data_parse = gm20b_device_info_data_parse; | 156 | gops->fifo.device_info_data_parse = gm20b_device_info_data_parse; |
157 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; | 157 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; |
158 | gops->fifo.init_engine_info = gk20a_fifo_init_engine_info; | ||
158 | } | 159 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 11f389fb..ffa16cd3 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -160,22 +160,29 @@ static int vgpu_channel_setup_ramfc(struct channel_gk20a *ch, u64 gpfifo_base, | |||
160 | return (err || msg.ret) ? -ENOMEM : 0; | 160 | return (err || msg.ret) ? -ENOMEM : 0; |
161 | } | 161 | } |
162 | 162 | ||
163 | static int init_engine_info(struct fifo_gk20a *f) | 163 | static int vgpu_fifo_init_engine_info(struct fifo_gk20a *f) |
164 | { | 164 | { |
165 | struct fifo_engine_info_gk20a *gr_info; | 165 | struct fifo_engine_info_gk20a *gr_info; |
166 | struct fifo_engine_info_gk20a *ce_info; | ||
166 | const u32 gr_sw_id = ENGINE_GR_GK20A; | 167 | const u32 gr_sw_id = ENGINE_GR_GK20A; |
168 | const u32 ce_sw_id = ENGINE_GRCE_GK20A; | ||
167 | 169 | ||
168 | gk20a_dbg_fn(""); | 170 | gk20a_dbg_fn(""); |
169 | 171 | ||
170 | /* all we really care about finding is the graphics entry */ | 172 | f->num_engines = 2; |
171 | /* especially early on in sim it probably thinks it has more */ | ||
172 | f->num_engines = 1; | ||
173 | 173 | ||
174 | gr_info = f->engine_info + gr_sw_id; | 174 | gr_info = &f->engine_info[0]; |
175 | 175 | ||
176 | /* FIXME: retrieve this from server */ | 176 | /* FIXME: retrieve this from server */ |
177 | gr_info->runlist_id = 0; | 177 | gr_info->runlist_id = 0; |
178 | f->active_engines_list[0] = gr_sw_id; | 178 | gr_info->engine_enum = gr_sw_id; |
179 | f->active_engines_list[0] = 0; | ||
180 | |||
181 | ce_info = &f->engine_info[1]; | ||
182 | ce_info->runlist_id = 0; | ||
183 | ce_info->inst_id = 2; | ||
184 | ce_info->engine_enum = ce_sw_id; | ||
185 | f->active_engines_list[1] = 1; | ||
179 | 186 | ||
180 | return 0; | 187 | return 0; |
181 | } | 188 | } |
@@ -292,7 +299,7 @@ static int vgpu_init_fifo_setup_sw(struct gk20a *g) | |||
292 | } | 299 | } |
293 | memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32))); | 300 | memset(f->active_engines_list, 0xff, (f->max_engines * sizeof(u32))); |
294 | 301 | ||
295 | init_engine_info(f); | 302 | g->ops.fifo.init_engine_info(f); |
296 | 303 | ||
297 | init_runlist(g, f); | 304 | init_runlist(g, f); |
298 | 305 | ||
@@ -778,4 +785,5 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) | |||
778 | gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; | 785 | gops->fifo.set_runlist_interleave = vgpu_fifo_set_runlist_interleave; |
779 | gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; | 786 | gops->fifo.channel_set_timeslice = vgpu_channel_set_timeslice; |
780 | gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch; | 787 | gops->fifo.force_reset_ch = vgpu_fifo_force_reset_ch; |
788 | gops->fifo.init_engine_info = vgpu_fifo_init_engine_info; | ||
781 | } | 789 | } |