diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | 120 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 48 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 |
3 files changed, 88 insertions, 82 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c index 58178ac3..2a91b87d 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | |||
@@ -221,57 +221,113 @@ gk20a_ctrl_ioctl_gpu_characteristics( | |||
221 | struct gk20a *g, | 221 | struct gk20a *g, |
222 | struct nvgpu_gpu_get_characteristics *request) | 222 | struct nvgpu_gpu_get_characteristics *request) |
223 | { | 223 | { |
224 | struct nvgpu_gpu_characteristics *pgpu = &g->gpu_characteristics; | 224 | struct nvgpu_gpu_characteristics gpu; |
225 | long err = 0; | 225 | long err = 0; |
226 | 226 | ||
227 | pgpu->flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); | 227 | if (gk20a_busy(g)) { |
228 | nvgpu_err(g, "failed to power on gpu"); | ||
229 | return -EINVAL; | ||
230 | } | ||
231 | |||
232 | memset(&gpu, 0, sizeof(gpu)); | ||
233 | |||
234 | gpu.L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g); | ||
235 | gpu.on_board_video_memory_size = 0; /* integrated GPU */ | ||
236 | |||
237 | gpu.num_gpc = g->gr.gpc_count; | ||
238 | gpu.max_gpc_count = g->gr.max_gpc_count; | ||
239 | |||
240 | gpu.num_tpc_per_gpc = g->gr.max_tpc_per_gpc_count; | ||
241 | |||
242 | gpu.bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */ | ||
243 | |||
244 | gpu.compression_page_size = g->ops.fb.compression_page_size(g); | ||
245 | |||
246 | gpu.gpc_mask = (1 << g->gr.gpc_count)-1; | ||
247 | |||
248 | gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); | ||
228 | #ifdef CONFIG_TEGRA_19x_GPU | 249 | #ifdef CONFIG_TEGRA_19x_GPU |
229 | pgpu->flags |= nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(g); | 250 | gpu.flags |= nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(g); |
230 | #endif | 251 | #endif |
231 | pgpu->arch = g->params.gpu_arch; | 252 | gpu.arch = g->params.gpu_arch; |
232 | pgpu->impl = g->params.gpu_impl; | 253 | gpu.impl = g->params.gpu_impl; |
233 | pgpu->rev = g->params.gpu_rev; | 254 | gpu.rev = g->params.gpu_rev; |
234 | pgpu->reg_ops_limit = NVGPU_IOCTL_DBG_REG_OPS_LIMIT; | 255 | gpu.reg_ops_limit = NVGPU_IOCTL_DBG_REG_OPS_LIMIT; |
235 | pgpu->map_buffer_batch_limit = nvgpu_is_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH) ? | 256 | gpu.map_buffer_batch_limit = nvgpu_is_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH) ? |
236 | NVGPU_IOCTL_AS_MAP_BUFFER_BATCH_LIMIT : 0; | 257 | NVGPU_IOCTL_AS_MAP_BUFFER_BATCH_LIMIT : 0; |
237 | pgpu->twod_class = g->ops.get_litter_value(g, GPU_LIT_TWOD_CLASS); | 258 | gpu.twod_class = g->ops.get_litter_value(g, GPU_LIT_TWOD_CLASS); |
238 | pgpu->threed_class = g->ops.get_litter_value(g, GPU_LIT_THREED_CLASS); | 259 | gpu.threed_class = g->ops.get_litter_value(g, GPU_LIT_THREED_CLASS); |
239 | pgpu->compute_class = g->ops.get_litter_value(g, GPU_LIT_COMPUTE_CLASS); | 260 | gpu.compute_class = g->ops.get_litter_value(g, GPU_LIT_COMPUTE_CLASS); |
240 | pgpu->gpfifo_class = g->ops.get_litter_value(g, GPU_LIT_GPFIFO_CLASS); | 261 | gpu.gpfifo_class = g->ops.get_litter_value(g, GPU_LIT_GPFIFO_CLASS); |
241 | pgpu->inline_to_memory_class = | 262 | gpu.inline_to_memory_class = |
242 | g->ops.get_litter_value(g, GPU_LIT_I2M_CLASS); | 263 | g->ops.get_litter_value(g, GPU_LIT_I2M_CLASS); |
243 | pgpu->dma_copy_class = | 264 | gpu.dma_copy_class = |
244 | g->ops.get_litter_value(g, GPU_LIT_DMA_COPY_CLASS); | 265 | g->ops.get_litter_value(g, GPU_LIT_DMA_COPY_CLASS); |
245 | 266 | ||
246 | pgpu->vbios_version = g->bios.vbios_version; | 267 | gpu.vbios_version = g->bios.vbios_version; |
247 | pgpu->vbios_oem_version = g->bios.vbios_oem_version; | 268 | gpu.vbios_oem_version = g->bios.vbios_oem_version; |
248 | 269 | ||
249 | pgpu->big_page_size = nvgpu_mm_get_default_big_page_size(g); | 270 | gpu.big_page_size = nvgpu_mm_get_default_big_page_size(g); |
250 | pgpu->pde_coverage_bit_count = | 271 | gpu.pde_coverage_bit_count = |
251 | g->ops.mm.get_mmu_levels(g, pgpu->big_page_size)[0].lo_bit[0]; | 272 | g->ops.mm.get_mmu_levels(g, gpu.big_page_size)[0].lo_bit[0]; |
252 | pgpu->available_big_page_sizes = nvgpu_mm_get_available_big_page_sizes(g); | 273 | gpu.available_big_page_sizes = nvgpu_mm_get_available_big_page_sizes(g); |
253 | 274 | ||
254 | pgpu->sm_arch_sm_version = g->params.sm_arch_sm_version; | 275 | gpu.sm_arch_sm_version = g->params.sm_arch_sm_version; |
255 | pgpu->sm_arch_spa_version = g->params.sm_arch_spa_version; | 276 | gpu.sm_arch_spa_version = g->params.sm_arch_spa_version; |
256 | pgpu->sm_arch_warp_count = g->params.sm_arch_warp_count; | 277 | gpu.sm_arch_warp_count = g->params.sm_arch_warp_count; |
257 | 278 | ||
258 | pgpu->max_css_buffer_size = g->gr.max_css_buffer_size; | 279 | gpu.max_css_buffer_size = g->gr.max_css_buffer_size; |
259 | 280 | ||
260 | nvgpu_set_preemption_mode_flags(g, pgpu); | 281 | gpu.gpu_ioctl_nr_last = NVGPU_GPU_IOCTL_LAST; |
282 | gpu.tsg_ioctl_nr_last = NVGPU_TSG_IOCTL_LAST; | ||
283 | gpu.dbg_gpu_ioctl_nr_last = NVGPU_DBG_GPU_IOCTL_LAST; | ||
284 | gpu.ioctl_channel_nr_last = NVGPU_IOCTL_CHANNEL_LAST; | ||
285 | gpu.as_ioctl_nr_last = NVGPU_AS_IOCTL_LAST; | ||
286 | gpu.event_ioctl_nr_last = NVGPU_EVENT_IOCTL_LAST; | ||
287 | gpu.gpu_va_bit_count = 40; | ||
288 | |||
289 | strlcpy(gpu.chipname, g->name, sizeof(gpu.chipname)); | ||
290 | gpu.max_fbps_count = g->ops.gr.get_max_fbps_count(g); | ||
291 | gpu.fbp_en_mask = g->ops.gr.get_fbp_en_mask(g); | ||
292 | gpu.max_ltc_per_fbp = g->ops.gr.get_max_ltc_per_fbp(g); | ||
293 | gpu.max_lts_per_ltc = g->ops.gr.get_max_lts_per_ltc(g); | ||
294 | gpu.gr_compbit_store_base_hw = g->gr.compbit_store.base_hw; | ||
295 | gpu.gr_gobs_per_comptagline_per_slice = | ||
296 | g->gr.gobs_per_comptagline_per_slice; | ||
297 | gpu.num_ltc = g->ltc_count; | ||
298 | gpu.lts_per_ltc = g->gr.slices_per_ltc; | ||
299 | gpu.cbc_cache_line_size = g->gr.cacheline_size; | ||
300 | gpu.cbc_comptags_per_line = g->gr.comptags_per_cacheline; | ||
301 | |||
302 | if (g->ops.clk.get_maxrate) | ||
303 | gpu.max_freq = g->ops.clk.get_maxrate(g, CTRL_CLK_DOMAIN_GPCCLK); | ||
304 | |||
305 | gpu.local_video_memory_size = g->mm.vidmem.size; | ||
306 | |||
307 | gpu.pci_vendor_id = g->pci_vendor_id; | ||
308 | gpu.pci_device_id = g->pci_device_id; | ||
309 | gpu.pci_subsystem_vendor_id = g->pci_subsystem_vendor_id; | ||
310 | gpu.pci_subsystem_device_id = g->pci_subsystem_device_id; | ||
311 | gpu.pci_class = g->pci_class; | ||
312 | gpu.pci_revision = g->pci_revision; | ||
313 | |||
314 | nvgpu_set_preemption_mode_flags(g, &gpu); | ||
261 | 315 | ||
262 | if (request->gpu_characteristics_buf_size > 0) { | 316 | if (request->gpu_characteristics_buf_size > 0) { |
263 | size_t write_size = sizeof(*pgpu); | 317 | size_t write_size = sizeof(gpu); |
264 | 318 | ||
265 | if (write_size > request->gpu_characteristics_buf_size) | 319 | if (write_size > request->gpu_characteristics_buf_size) |
266 | write_size = request->gpu_characteristics_buf_size; | 320 | write_size = request->gpu_characteristics_buf_size; |
267 | 321 | ||
268 | err = copy_to_user((void __user *)(uintptr_t) | 322 | err = copy_to_user((void __user *)(uintptr_t) |
269 | request->gpu_characteristics_buf_addr, | 323 | request->gpu_characteristics_buf_addr, |
270 | pgpu, write_size); | 324 | &gpu, write_size); |
271 | } | 325 | } |
272 | 326 | ||
273 | if (err == 0) | 327 | if (err == 0) |
274 | request->gpu_characteristics_buf_size = sizeof(*pgpu); | 328 | request->gpu_characteristics_buf_size = sizeof(gpu); |
329 | |||
330 | gk20a_idle(g); | ||
275 | 331 | ||
276 | return err; | 332 | return err; |
277 | } | 333 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 8f67da69..5dc60917 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -381,20 +381,6 @@ int gk20a_wait_for_idle(struct gk20a *g) | |||
381 | 381 | ||
382 | int gk20a_init_gpu_characteristics(struct gk20a *g) | 382 | int gk20a_init_gpu_characteristics(struct gk20a *g) |
383 | { | 383 | { |
384 | struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; | ||
385 | |||
386 | gpu->L2_cache_size = g->ops.ltc.determine_L2_size_bytes(g); | ||
387 | gpu->on_board_video_memory_size = 0; /* integrated GPU */ | ||
388 | |||
389 | gpu->num_gpc = g->gr.gpc_count; | ||
390 | gpu->max_gpc_count = g->gr.max_gpc_count; | ||
391 | |||
392 | gpu->num_tpc_per_gpc = g->gr.max_tpc_per_gpc_count; | ||
393 | |||
394 | gpu->bus_type = NVGPU_GPU_BUS_TYPE_AXI; /* always AXI for now */ | ||
395 | |||
396 | gpu->compression_page_size = g->ops.fb.compression_page_size(g); | ||
397 | |||
398 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true); | 384 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true); |
399 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true); | 385 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true); |
400 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true); | 386 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_BUFFER_BATCH, true); |
@@ -436,46 +422,12 @@ int gk20a_init_gpu_characteristics(struct gk20a *g) | |||
436 | if (g->ops.clk_arb.get_arbiter_clk_domains) | 422 | if (g->ops.clk_arb.get_arbiter_clk_domains) |
437 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true); | 423 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true); |
438 | 424 | ||
439 | gpu->gpc_mask = (1 << g->gr.gpc_count)-1; | ||
440 | |||
441 | g->ops.gr.detect_sm_arch(g); | 425 | g->ops.gr.detect_sm_arch(g); |
442 | 426 | ||
443 | if (g->ops.gr.init_cyclestats) | 427 | if (g->ops.gr.init_cyclestats) |
444 | g->ops.gr.init_cyclestats(g); | 428 | g->ops.gr.init_cyclestats(g); |
445 | 429 | ||
446 | gpu->gpu_ioctl_nr_last = NVGPU_GPU_IOCTL_LAST; | ||
447 | gpu->tsg_ioctl_nr_last = NVGPU_TSG_IOCTL_LAST; | ||
448 | gpu->dbg_gpu_ioctl_nr_last = NVGPU_DBG_GPU_IOCTL_LAST; | ||
449 | gpu->ioctl_channel_nr_last = NVGPU_IOCTL_CHANNEL_LAST; | ||
450 | gpu->as_ioctl_nr_last = NVGPU_AS_IOCTL_LAST; | ||
451 | gpu->event_ioctl_nr_last = NVGPU_EVENT_IOCTL_LAST; | ||
452 | gpu->gpu_va_bit_count = 40; | ||
453 | |||
454 | strlcpy(gpu->chipname, g->name, sizeof(gpu->chipname)); | ||
455 | gpu->max_fbps_count = g->ops.gr.get_max_fbps_count(g); | ||
456 | gpu->fbp_en_mask = g->ops.gr.get_fbp_en_mask(g); | ||
457 | gpu->max_ltc_per_fbp = g->ops.gr.get_max_ltc_per_fbp(g); | ||
458 | gpu->max_lts_per_ltc = g->ops.gr.get_max_lts_per_ltc(g); | ||
459 | g->ops.gr.get_rop_l2_en_mask(g); | 430 | g->ops.gr.get_rop_l2_en_mask(g); |
460 | gpu->gr_compbit_store_base_hw = g->gr.compbit_store.base_hw; | ||
461 | gpu->gr_gobs_per_comptagline_per_slice = | ||
462 | g->gr.gobs_per_comptagline_per_slice; | ||
463 | gpu->num_ltc = g->ltc_count; | ||
464 | gpu->lts_per_ltc = g->gr.slices_per_ltc; | ||
465 | gpu->cbc_cache_line_size = g->gr.cacheline_size; | ||
466 | gpu->cbc_comptags_per_line = g->gr.comptags_per_cacheline; | ||
467 | |||
468 | if (g->ops.clk.get_maxrate) | ||
469 | gpu->max_freq = g->ops.clk.get_maxrate(g, CTRL_CLK_DOMAIN_GPCCLK); | ||
470 | |||
471 | gpu->local_video_memory_size = g->mm.vidmem.size; | ||
472 | |||
473 | gpu->pci_vendor_id = g->pci_vendor_id; | ||
474 | gpu->pci_device_id = g->pci_device_id; | ||
475 | gpu->pci_subsystem_vendor_id = g->pci_subsystem_vendor_id; | ||
476 | gpu->pci_subsystem_device_id = g->pci_subsystem_device_id; | ||
477 | gpu->pci_class = g->pci_class; | ||
478 | gpu->pci_revision = g->pci_revision; | ||
479 | 431 | ||
480 | return 0; | 432 | return 0; |
481 | } | 433 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 3381d974..09597bb2 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1225,8 +1225,6 @@ struct gk20a { | |||
1225 | 1225 | ||
1226 | struct nvgpu_spinlock mc_enable_lock; | 1226 | struct nvgpu_spinlock mc_enable_lock; |
1227 | 1227 | ||
1228 | struct nvgpu_gpu_characteristics gpu_characteristics; | ||
1229 | |||
1230 | struct gk20a_as as; | 1228 | struct gk20a_as as; |
1231 | 1229 | ||
1232 | struct nvgpu_mutex client_lock; | 1230 | struct nvgpu_mutex client_lock; |