diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_dev.c | 61 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_pmu.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_policy.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_rail.c | 55 |
4 files changed, 107 insertions, 57 deletions
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index d900b37b..728b0eaf 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c | |||
@@ -46,8 +46,9 @@ static u32 volt_device_pmu_data_init_super(struct gk20a *g, | |||
46 | struct nv_pmu_volt_volt_device_boardobj_set *pset; | 46 | struct nv_pmu_volt_volt_device_boardobj_set *pset; |
47 | 47 | ||
48 | status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); | 48 | status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata); |
49 | if (status) | 49 | if (status) { |
50 | return status; | 50 | return status; |
51 | } | ||
51 | 52 | ||
52 | pdev = (struct voltage_device *)pboard_obj; | 53 | pdev = (struct voltage_device *)pboard_obj; |
53 | pset = (struct nv_pmu_volt_volt_device_boardobj_set *)ppmudata; | 54 | pset = (struct nv_pmu_volt_volt_device_boardobj_set *)ppmudata; |
@@ -68,8 +69,9 @@ static u32 volt_device_pmu_data_init_pwm(struct gk20a *g, | |||
68 | struct nv_pmu_volt_volt_device_pwm_boardobj_set *pset; | 69 | struct nv_pmu_volt_volt_device_pwm_boardobj_set *pset; |
69 | 70 | ||
70 | status = volt_device_pmu_data_init_super(g, pboard_obj, ppmudata); | 71 | status = volt_device_pmu_data_init_super(g, pboard_obj, ppmudata); |
71 | if (status) | 72 | if (status) { |
72 | return status; | 73 | return status; |
74 | } | ||
73 | 75 | ||
74 | pdev = (struct voltage_device_pwm *)pboard_obj; | 76 | pdev = (struct voltage_device_pwm *)pboard_obj; |
75 | pset = (struct nv_pmu_volt_volt_device_pwm_boardobj_set *)ppmudata; | 77 | pset = (struct nv_pmu_volt_volt_device_pwm_boardobj_set *)ppmudata; |
@@ -90,8 +92,9 @@ static u32 construct_volt_device(struct gk20a *g, | |||
90 | u32 status = 0; | 92 | u32 status = 0; |
91 | 93 | ||
92 | status = boardobj_construct_super(g, ppboardobj, size, pargs); | 94 | status = boardobj_construct_super(g, ppboardobj, size, pargs); |
93 | if (status) | 95 | if (status) { |
94 | return status; | 96 | return status; |
97 | } | ||
95 | 98 | ||
96 | pvolt_dev = (struct voltage_device *)*ppboardobj; | 99 | pvolt_dev = (struct voltage_device *)*ppboardobj; |
97 | 100 | ||
@@ -121,8 +124,9 @@ static u32 construct_pwm_volt_device(struct gk20a *g, | |||
121 | u32 status = 0; | 124 | u32 status = 0; |
122 | 125 | ||
123 | status = construct_volt_device(g, ppboardobj, size, pargs); | 126 | status = construct_volt_device(g, ppboardobj, size, pargs); |
124 | if (status) | 127 | if (status) { |
125 | return status; | 128 | return status; |
129 | } | ||
126 | 130 | ||
127 | pboard_obj = (*ppboardobj); | 131 | pboard_obj = (*ppboardobj); |
128 | pdev = (struct voltage_device_pwm *)*ppboardobj; | 132 | pdev = (struct voltage_device_pwm *)*ppboardobj; |
@@ -148,8 +152,9 @@ static struct voltage_device_entry *volt_dev_construct_dev_entry_pwm( | |||
148 | (struct voltage_device_pwm_entry *)pargs; | 152 | (struct voltage_device_pwm_entry *)pargs; |
149 | 153 | ||
150 | pentry = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm_entry)); | 154 | pentry = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm_entry)); |
151 | if (pentry == NULL) | 155 | if (pentry == NULL) { |
152 | return NULL; | 156 | return NULL; |
157 | } | ||
153 | 158 | ||
154 | memset(pentry, 0, sizeof(struct voltage_device_pwm_entry)); | 159 | memset(pentry, 0, sizeof(struct voltage_device_pwm_entry)); |
155 | 160 | ||
@@ -213,8 +218,9 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g, | |||
213 | struct voltage_device_pwm_entry pwm_entry = { { 0 } }; | 218 | struct voltage_device_pwm_entry pwm_entry = { { 0 } }; |
214 | 219 | ||
215 | ptmp_dev = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm)); | 220 | ptmp_dev = nvgpu_kzalloc(g, sizeof(struct voltage_device_pwm)); |
216 | if (ptmp_dev == NULL) | 221 | if (ptmp_dev == NULL) { |
217 | return -ENOMEM; | 222 | return -ENOMEM; |
223 | } | ||
218 | 224 | ||
219 | frequency_hz = (u32)BIOS_GET_FIELD(p_bios_entry->param0, | 225 | frequency_hz = (u32)BIOS_GET_FIELD(p_bios_entry->param0, |
220 | NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY); | 226 | NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY); |
@@ -247,8 +253,9 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g, | |||
247 | 253 | ||
248 | steps = (u8)BIOS_GET_FIELD(p_bios_entry->param3, | 254 | steps = (u8)BIOS_GET_FIELD(p_bios_entry->param3, |
249 | NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS); | 255 | NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS); |
250 | if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID) | 256 | if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID) { |
251 | steps = VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT; | 257 | steps = VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT; |
258 | } | ||
252 | 259 | ||
253 | ptmp_dev->voltage_offset_scale_uv = | 260 | ptmp_dev->voltage_offset_scale_uv = |
254 | BIOS_GET_FIELD(p_bios_entry->param4, | 261 | BIOS_GET_FIELD(p_bios_entry->param4, |
@@ -265,12 +272,14 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g, | |||
265 | 272 | ||
266 | if (ptmp_dev->super.operation_type == | 273 | if (ptmp_dev->super.operation_type == |
267 | CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { | 274 | CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { |
268 | if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) | 275 | if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) { |
269 | ptmp_dev->source = | 276 | ptmp_dev->source = |
270 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0; | 277 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0; |
271 | if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) | 278 | } |
279 | if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) { | ||
272 | ptmp_dev->source = | 280 | ptmp_dev->source = |
273 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; | 281 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; |
282 | } | ||
274 | ptmp_dev->raw_period = | 283 | ptmp_dev->raw_period = |
275 | g->ops.clk.get_crystal_clk_hz(g) / frequency_hz; | 284 | g->ops.clk.get_crystal_clk_hz(g) / frequency_hz; |
276 | } else if (ptmp_dev->super.operation_type == | 285 | } else if (ptmp_dev->super.operation_type == |
@@ -319,11 +328,12 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g, | |||
319 | /* Skip creating entry for invalid voltage. */ | 328 | /* Skip creating entry for invalid voltage. */ |
320 | if ((voltage_uv >= pvolt_dev_pwm->super.voltage_min_uv) && | 329 | if ((voltage_uv >= pvolt_dev_pwm->super.voltage_min_uv) && |
321 | (voltage_uv <= pvolt_dev_pwm->super.voltage_max_uv)) { | 330 | (voltage_uv <= pvolt_dev_pwm->super.voltage_max_uv)) { |
322 | if (pvolt_dev_pwm->voltage_offset_scale_uv < 0) | 331 | if (pvolt_dev_pwm->voltage_offset_scale_uv < 0) { |
323 | pwm_entry.duty_cycle = | 332 | pwm_entry.duty_cycle = |
324 | pvolt_dev_pwm->raw_period - duty_cycle; | 333 | pvolt_dev_pwm->raw_period - duty_cycle; |
325 | else | 334 | } else { |
326 | pwm_entry.duty_cycle = duty_cycle; | 335 | pwm_entry.duty_cycle = duty_cycle; |
336 | } | ||
327 | 337 | ||
328 | /* Check if there is room left in the voltage table. */ | 338 | /* Check if there is room left in the voltage table. */ |
329 | if (entry_cnt == VOLTAGE_TABLE_MAX_ENTRIES) { | 339 | if (entry_cnt == VOLTAGE_TABLE_MAX_ENTRIES) { |
@@ -349,14 +359,16 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g, | |||
349 | duty_cycle = duty_cycle + (u32)steps; | 359 | duty_cycle = duty_cycle + (u32)steps; |
350 | 360 | ||
351 | /* Cap duty cycle to PWM period. */ | 361 | /* Cap duty cycle to PWM period. */ |
352 | if (duty_cycle > pvolt_dev_pwm->raw_period) | 362 | if (duty_cycle > pvolt_dev_pwm->raw_period) { |
353 | duty_cycle = pvolt_dev_pwm->raw_period; | 363 | duty_cycle = pvolt_dev_pwm->raw_period; |
364 | } | ||
354 | 365 | ||
355 | } while (duty_cycle < pvolt_dev_pwm->raw_period); | 366 | } while (duty_cycle < pvolt_dev_pwm->raw_period); |
356 | 367 | ||
357 | done: | 368 | done: |
358 | if (pvolt_dev != NULL) | 369 | if (pvolt_dev != NULL) { |
359 | pvolt_dev->num_entries = entry_cnt; | 370 | pvolt_dev->num_entries = entry_cnt; |
371 | } | ||
360 | 372 | ||
361 | nvgpu_kfree(g, ptmp_dev); | 373 | nvgpu_kfree(g, ptmp_dev); |
362 | return status; | 374 | return status; |
@@ -390,10 +402,11 @@ static u32 volt_get_volt_devices_table(struct gk20a *g, | |||
390 | memcpy(&entry, entry_offset, | 402 | memcpy(&entry, entry_offset, |
391 | sizeof(struct vbios_voltage_device_table_1x_entry)); | 403 | sizeof(struct vbios_voltage_device_table_1x_entry)); |
392 | 404 | ||
393 | if (entry.type == NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV) | 405 | if (entry.type == NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV) { |
394 | status = volt_get_voltage_device_table_1x_psv(g, | 406 | status = volt_get_voltage_device_table_1x_psv(g, |
395 | &entry, pvolt_device_metadata, | 407 | &entry, pvolt_device_metadata, |
396 | entry_idx); | 408 | entry_idx); |
409 | } | ||
397 | } | 410 | } |
398 | 411 | ||
399 | done: | 412 | done: |
@@ -412,8 +425,9 @@ static u32 _volt_device_devgrp_pmudata_instget(struct gk20a *g, | |||
412 | 425 | ||
413 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 426 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
414 | if (((u32)BIT(idx) & | 427 | if (((u32)BIT(idx) & |
415 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 428 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
416 | return -EINVAL; | 429 | return -EINVAL; |
430 | } | ||
417 | 431 | ||
418 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 432 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
419 | &pgrp_set->objects[idx].data.board_obj; | 433 | &pgrp_set->objects[idx].data.board_obj; |
@@ -431,8 +445,9 @@ static u32 _volt_device_devgrp_pmustatus_instget(struct gk20a *g, | |||
431 | 445 | ||
432 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 446 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
433 | if (((u32)BIT(idx) & | 447 | if (((u32)BIT(idx) & |
434 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) | 448 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { |
435 | return -EINVAL; | 449 | return -EINVAL; |
450 | } | ||
436 | 451 | ||
437 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | 452 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) |
438 | &pgrp_get_status->objects[idx].data.board_obj; | 453 | &pgrp_get_status->objects[idx].data.board_obj; |
@@ -459,11 +474,12 @@ static u32 volt_device_state_init(struct gk20a *g, | |||
459 | NULL); | 474 | NULL); |
460 | 475 | ||
461 | /* Initialize VOLT_DEVICE step size. */ | 476 | /* Initialize VOLT_DEVICE step size. */ |
462 | if (pvolt_dev->num_entries <= VOLTAGE_TABLE_MAX_ENTRIES_ONE) | 477 | if (pvolt_dev->num_entries <= VOLTAGE_TABLE_MAX_ENTRIES_ONE) { |
463 | pvolt_dev->volt_step_uv = NV_PMU_VOLT_VALUE_0V_IN_UV; | 478 | pvolt_dev->volt_step_uv = NV_PMU_VOLT_VALUE_0V_IN_UV; |
464 | else | 479 | } else { |
465 | pvolt_dev->volt_step_uv = (pvolt_dev->pentry[1]->voltage_uv - | 480 | pvolt_dev->volt_step_uv = (pvolt_dev->pentry[1]->voltage_uv - |
466 | pvolt_dev->pentry[0]->voltage_uv); | 481 | pvolt_dev->pentry[0]->voltage_uv); |
482 | } | ||
467 | 483 | ||
468 | /* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */ | 484 | /* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */ |
469 | /* If VOLT_RAIL isn't supported, exit. */ | 485 | /* If VOLT_RAIL isn't supported, exit. */ |
@@ -495,8 +511,9 @@ static u32 volt_device_state_init(struct gk20a *g, | |||
495 | } | 511 | } |
496 | 512 | ||
497 | done: | 513 | done: |
498 | if (status) | 514 | if (status) { |
499 | nvgpu_err(g, "Error in building rail sw state device sw"); | 515 | nvgpu_err(g, "Error in building rail sw state device sw"); |
516 | } | ||
500 | 517 | ||
501 | return status; | 518 | return status; |
502 | } | 519 | } |
@@ -510,8 +527,9 @@ u32 volt_dev_pmu_setup(struct gk20a *g) | |||
510 | 527 | ||
511 | pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super; | 528 | pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super; |
512 | 529 | ||
513 | if (!pboardobjgrp->bconstructed) | 530 | if (!pboardobjgrp->bconstructed) { |
514 | return -EINVAL; | 531 | return -EINVAL; |
532 | } | ||
515 | 533 | ||
516 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 534 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
517 | 535 | ||
@@ -545,8 +563,9 @@ u32 volt_dev_sw_setup(struct gk20a *g) | |||
545 | /* Obtain Voltage Rail Table from VBIOS */ | 563 | /* Obtain Voltage Rail Table from VBIOS */ |
546 | status = volt_get_volt_devices_table(g, &g->perf_pmu.volt. | 564 | status = volt_get_volt_devices_table(g, &g->perf_pmu.volt. |
547 | volt_dev_metadata); | 565 | volt_dev_metadata); |
548 | if (status) | 566 | if (status) { |
549 | goto done; | 567 | goto done; |
568 | } | ||
550 | 569 | ||
551 | /* Populate data for the VOLT_RAIL PMU interface */ | 570 | /* Populate data for the VOLT_RAIL PMU interface */ |
552 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_DEVICE); | 571 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_DEVICE); |
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index bd9177ff..6d92686c 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c | |||
@@ -54,8 +54,9 @@ static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg, | |||
54 | return; | 54 | return; |
55 | } | 55 | } |
56 | 56 | ||
57 | if (phandlerparams->prpc_call->b_supported) | 57 | if (phandlerparams->prpc_call->b_supported) { |
58 | phandlerparams->success = 1; | 58 | phandlerparams->success = 1; |
59 | } | ||
59 | } | 60 | } |
60 | 61 | ||
61 | 62 | ||
@@ -124,10 +125,11 @@ u32 nvgpu_volt_send_load_cmd_to_pmu_gp10x(struct gk20a *g) | |||
124 | rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD; | 125 | rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD; |
125 | 126 | ||
126 | status = volt_pmu_rpc_execute(g, &rpc_call); | 127 | status = volt_pmu_rpc_execute(g, &rpc_call); |
127 | if (status) | 128 | if (status) { |
128 | nvgpu_err(g, | 129 | nvgpu_err(g, |
129 | "Error while executing LOAD RPC: status = 0x%08x.", | 130 | "Error while executing LOAD RPC: status = 0x%08x.", |
130 | status); | 131 | status); |
132 | } | ||
131 | 133 | ||
132 | return status; | 134 | return status; |
133 | } | 135 | } |
@@ -241,9 +243,10 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id, | |||
241 | } | 243 | } |
242 | 244 | ||
243 | /* Convert the client ID to index. */ | 245 | /* Convert the client ID to index. */ |
244 | if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) | 246 | if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ) { |
245 | policy_idx = | 247 | policy_idx = |
246 | pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx; | 248 | pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx; |
249 | } | ||
247 | else { | 250 | else { |
248 | status = -EINVAL; | 251 | status = -EINVAL; |
249 | goto exit; | 252 | goto exit; |
@@ -257,9 +260,10 @@ static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id, | |||
257 | 260 | ||
258 | /* Execute the voltage change request via PMU RPC. */ | 261 | /* Execute the voltage change request via PMU RPC. */ |
259 | status = volt_pmu_rpc_execute(g, &rpc_call); | 262 | status = volt_pmu_rpc_execute(g, &rpc_call); |
260 | if (status) | 263 | if (status) { |
261 | nvgpu_err(g, | 264 | nvgpu_err(g, |
262 | "Error while executing VOLT_POLICY_SET_VOLTAGE RPC"); | 265 | "Error while executing VOLT_POLICY_SET_VOLTAGE RPC"); |
266 | } | ||
263 | 267 | ||
264 | exit: | 268 | exit: |
265 | return status; | 269 | return status; |
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c index 3783dc32..4c8737d3 100644 --- a/drivers/gpu/nvgpu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/volt/volt_policy.c | |||
@@ -43,8 +43,9 @@ static u32 construct_volt_policy(struct gk20a *g, | |||
43 | u32 status = 0; | 43 | u32 status = 0; |
44 | 44 | ||
45 | status = boardobj_construct_super(g, ppboardobj, size, pArgs); | 45 | status = boardobj_construct_super(g, ppboardobj, size, pArgs); |
46 | if (status) | 46 | if (status) { |
47 | return status; | 47 | return status; |
48 | } | ||
48 | 49 | ||
49 | pvolt_policy = (struct voltage_policy *)*ppboardobj; | 50 | pvolt_policy = (struct voltage_policy *)*ppboardobj; |
50 | 51 | ||
@@ -62,8 +63,9 @@ static u32 construct_volt_policy_split_rail(struct gk20a *g, | |||
62 | u32 status = 0; | 63 | u32 status = 0; |
63 | 64 | ||
64 | status = construct_volt_policy(g, ppboardobj, size, pArgs); | 65 | status = construct_volt_policy(g, ppboardobj, size, pArgs); |
65 | if (status) | 66 | if (status) { |
66 | return status; | 67 | return status; |
68 | } | ||
67 | 69 | ||
68 | pvolt_policy = (struct voltage_policy_split_rail *)*ppboardobj; | 70 | pvolt_policy = (struct voltage_policy_split_rail *)*ppboardobj; |
69 | 71 | ||
@@ -86,8 +88,9 @@ static u32 construct_volt_policy_single_rail(struct gk20a *g, | |||
86 | u32 status = 0; | 88 | u32 status = 0; |
87 | 89 | ||
88 | status = construct_volt_policy(g, ppboardobj, size, pArgs); | 90 | status = construct_volt_policy(g, ppboardobj, size, pArgs); |
89 | if (status) | 91 | if (status) { |
90 | return status; | 92 | return status; |
93 | } | ||
91 | 94 | ||
92 | pvolt_policy = (struct voltage_policy_single_rail *)*ppboardobj; | 95 | pvolt_policy = (struct voltage_policy_single_rail *)*ppboardobj; |
93 | 96 | ||
@@ -104,8 +107,9 @@ static u32 volt_policy_pmu_data_init_single_rail(struct gk20a *g, | |||
104 | struct nv_pmu_volt_volt_policy_sr_boardobj_set *pset; | 107 | struct nv_pmu_volt_volt_policy_sr_boardobj_set *pset; |
105 | 108 | ||
106 | status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata); | 109 | status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata); |
107 | if (status) | 110 | if (status) { |
108 | goto done; | 111 | goto done; |
112 | } | ||
109 | 113 | ||
110 | ppolicy = (struct voltage_policy_single_rail *)pboardobj; | 114 | ppolicy = (struct voltage_policy_single_rail *)pboardobj; |
111 | pset = (struct nv_pmu_volt_volt_policy_sr_boardobj_set *) | 115 | pset = (struct nv_pmu_volt_volt_policy_sr_boardobj_set *) |
@@ -124,8 +128,9 @@ static u32 volt_policy_pmu_data_init_sr_multi_step(struct gk20a *g, | |||
124 | struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *pset; | 128 | struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *pset; |
125 | 129 | ||
126 | status = volt_policy_pmu_data_init_single_rail(g, pboardobj, ppmudata); | 130 | status = volt_policy_pmu_data_init_single_rail(g, pboardobj, ppmudata); |
127 | if (status) | 131 | if (status) { |
128 | goto done; | 132 | goto done; |
133 | } | ||
129 | 134 | ||
130 | ppolicy = (struct voltage_policy_single_rail_multi_step *)pboardobj; | 135 | ppolicy = (struct voltage_policy_single_rail_multi_step *)pboardobj; |
131 | pset = (struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *) | 136 | pset = (struct nv_pmu_volt_volt_policy_sr_multi_step_boardobj_set *) |
@@ -149,8 +154,9 @@ static u32 volt_construct_volt_policy_single_rail_multi_step(struct gk20a *g, | |||
149 | u32 status = 0; | 154 | u32 status = 0; |
150 | 155 | ||
151 | status = construct_volt_policy_single_rail(g, ppboardobj, size, pargs); | 156 | status = construct_volt_policy_single_rail(g, ppboardobj, size, pargs); |
152 | if (status) | 157 | if (status) { |
153 | return status; | 158 | return status; |
159 | } | ||
154 | 160 | ||
155 | pboardobj = (*ppboardobj); | 161 | pboardobj = (*ppboardobj); |
156 | p_volt_policy = (struct voltage_policy_single_rail_multi_step *) | 162 | p_volt_policy = (struct voltage_policy_single_rail_multi_step *) |
@@ -176,8 +182,9 @@ static u32 volt_policy_pmu_data_init_split_rail(struct gk20a *g, | |||
176 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *pset; | 182 | struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *pset; |
177 | 183 | ||
178 | status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata); | 184 | status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata); |
179 | if (status) | 185 | if (status) { |
180 | goto done; | 186 | goto done; |
187 | } | ||
181 | 188 | ||
182 | ppolicy = (struct voltage_policy_split_rail *)pboardobj; | 189 | ppolicy = (struct voltage_policy_split_rail *)pboardobj; |
183 | pset = (struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *) | 190 | pset = (struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *) |
@@ -201,8 +208,9 @@ static u32 volt_construct_volt_policy_split_rail_single_step(struct gk20a *g, | |||
201 | u32 status = 0; | 208 | u32 status = 0; |
202 | 209 | ||
203 | status = construct_volt_policy_split_rail(g, ppboardobj, size, pargs); | 210 | status = construct_volt_policy_split_rail(g, ppboardobj, size, pargs); |
204 | if (status) | 211 | if (status) { |
205 | return status; | 212 | return status; |
213 | } | ||
206 | 214 | ||
207 | pboardobj = (*ppboardobj); | 215 | pboardobj = (*ppboardobj); |
208 | pboardobj->pmudatainit = volt_policy_pmu_data_init_split_rail; | 216 | pboardobj->pmudatainit = volt_policy_pmu_data_init_split_rail; |
@@ -374,8 +382,9 @@ static u32 _volt_policy_devgrp_pmudata_instget(struct gk20a *g, | |||
374 | 382 | ||
375 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 383 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
376 | if (((u32)BIT(idx) & | 384 | if (((u32)BIT(idx) & |
377 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 385 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
378 | return -EINVAL; | 386 | return -EINVAL; |
387 | } | ||
379 | 388 | ||
380 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 389 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
381 | &pgrp_set->objects[idx].data.board_obj; | 390 | &pgrp_set->objects[idx].data.board_obj; |
@@ -393,8 +402,9 @@ static u32 _volt_policy_devgrp_pmustatus_instget(struct gk20a *g, | |||
393 | 402 | ||
394 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 403 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
395 | if (((u32)BIT(idx) & | 404 | if (((u32)BIT(idx) & |
396 | p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) | 405 | p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { |
397 | return -EINVAL; | 406 | return -EINVAL; |
407 | } | ||
398 | 408 | ||
399 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | 409 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) |
400 | &p_get_status->objects[idx].data.board_obj; | 410 | &p_get_status->objects[idx].data.board_obj; |
@@ -435,8 +445,9 @@ u32 volt_policy_pmu_setup(struct gk20a *g) | |||
435 | pboardobjgrp = | 445 | pboardobjgrp = |
436 | &g->perf_pmu.volt.volt_policy_metadata.volt_policies.super; | 446 | &g->perf_pmu.volt.volt_policy_metadata.volt_policies.super; |
437 | 447 | ||
438 | if (!pboardobjgrp->bconstructed) | 448 | if (!pboardobjgrp->bconstructed) { |
439 | return -EINVAL; | 449 | return -EINVAL; |
450 | } | ||
440 | 451 | ||
441 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 452 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
442 | 453 | ||
@@ -470,8 +481,9 @@ u32 volt_policy_sw_setup(struct gk20a *g) | |||
470 | /* Obtain Voltage Rail Table from VBIOS */ | 481 | /* Obtain Voltage Rail Table from VBIOS */ |
471 | status = volt_get_volt_policy_table(g, &g->perf_pmu.volt. | 482 | status = volt_get_volt_policy_table(g, &g->perf_pmu.volt. |
472 | volt_policy_metadata); | 483 | volt_policy_metadata); |
473 | if (status) | 484 | if (status) { |
474 | goto done; | 485 | goto done; |
486 | } | ||
475 | 487 | ||
476 | /* Populate data for the VOLT_RAIL PMU interface */ | 488 | /* Populate data for the VOLT_RAIL PMU interface */ |
477 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_POLICY); | 489 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_POLICY); |
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index 6a7dcdbe..e44d8973 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c | |||
@@ -89,8 +89,9 @@ u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail | |||
89 | volt_dev_idx); | 89 | volt_dev_idx); |
90 | 90 | ||
91 | exit: | 91 | exit: |
92 | if (status) | 92 | if (status) { |
93 | nvgpu_err(g, "Failed to register VOLTAGE_DEVICE"); | 93 | nvgpu_err(g, "Failed to register VOLTAGE_DEVICE"); |
94 | } | ||
94 | 95 | ||
95 | return status; | 96 | return status; |
96 | } | 97 | } |
@@ -138,8 +139,9 @@ static u32 volt_rail_init_pmudata_super(struct gk20a *g, | |||
138 | nvgpu_log_info(g, " "); | 139 | nvgpu_log_info(g, " "); |
139 | 140 | ||
140 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 141 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
141 | if (status) | 142 | if (status) { |
142 | return status; | 143 | return status; |
144 | } | ||
143 | 145 | ||
144 | prail = (struct voltage_rail *)board_obj_ptr; | 146 | prail = (struct voltage_rail *)board_obj_ptr; |
145 | rail_pmu_data = (struct nv_pmu_volt_volt_rail_boardobj_set *) | 147 | rail_pmu_data = (struct nv_pmu_volt_volt_rail_boardobj_set *) |
@@ -166,9 +168,10 @@ static u32 volt_rail_init_pmudata_super(struct gk20a *g, | |||
166 | status = boardobjgrpmask_export(&prail->volt_dev_mask.super, | 168 | status = boardobjgrpmask_export(&prail->volt_dev_mask.super, |
167 | prail->volt_dev_mask.super.bitcount, | 169 | prail->volt_dev_mask.super.bitcount, |
168 | &rail_pmu_data->volt_dev_mask.super); | 170 | &rail_pmu_data->volt_dev_mask.super); |
169 | if (status) | 171 | if (status) { |
170 | nvgpu_err(g, | 172 | nvgpu_err(g, |
171 | "Failed to export BOARDOBJGRPMASK of VOLTAGE_DEVICEs"); | 173 | "Failed to export BOARDOBJGRPMASK of VOLTAGE_DEVICEs"); |
174 | } | ||
172 | 175 | ||
173 | nvgpu_log_info(g, "Done"); | 176 | nvgpu_log_info(g, "Done"); |
174 | 177 | ||
@@ -185,8 +188,9 @@ static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs) | |||
185 | nvgpu_log_info(g, " "); | 188 | nvgpu_log_info(g, " "); |
186 | status = boardobj_construct_super(g, &board_obj_ptr, | 189 | status = boardobj_construct_super(g, &board_obj_ptr, |
187 | sizeof(struct voltage_rail), pargs); | 190 | sizeof(struct voltage_rail), pargs); |
188 | if (status) | 191 | if (status) { |
189 | return NULL; | 192 | return NULL; |
193 | } | ||
190 | 194 | ||
191 | board_obj_volt_rail_ptr = (struct voltage_rail *)board_obj_ptr; | 195 | board_obj_volt_rail_ptr = (struct voltage_rail *)board_obj_ptr; |
192 | /* override super class interface */ | 196 | /* override super class interface */ |
@@ -221,8 +225,9 @@ u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g, | |||
221 | { | 225 | { |
222 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { | 226 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { |
223 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: | 227 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: |
224 | if (vbios_volt_domain == 0) | 228 | if (vbios_volt_domain == 0) { |
225 | return CTRL_VOLT_DOMAIN_LOGIC; | 229 | return CTRL_VOLT_DOMAIN_LOGIC; |
230 | } | ||
226 | break; | 231 | break; |
227 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: | 232 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL: |
228 | switch (vbios_volt_domain) { | 233 | switch (vbios_volt_domain) { |
@@ -246,8 +251,9 @@ u32 volt_rail_pmu_setup(struct gk20a *g) | |||
246 | 251 | ||
247 | pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super; | 252 | pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super; |
248 | 253 | ||
249 | if (!pboardobjgrp->bconstructed) | 254 | if (!pboardobjgrp->bconstructed) { |
250 | return -EINVAL; | 255 | return -EINVAL; |
256 | } | ||
251 | 257 | ||
252 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 258 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
253 | 259 | ||
@@ -294,8 +300,9 @@ static u32 volt_get_volt_rail_table(struct gk20a *g, | |||
294 | 300 | ||
295 | volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g, | 301 | volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g, |
296 | i); | 302 | i); |
297 | if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) | 303 | if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) { |
298 | continue; | 304 | continue; |
305 | } | ||
299 | 306 | ||
300 | rail_type_data.board_obj.type = volt_domain; | 307 | rail_type_data.board_obj.type = volt_domain; |
301 | rail_type_data.volt_rail.boot_voltage_uv = | 308 | rail_type_data.volt_rail.boot_voltage_uv = |
@@ -308,44 +315,49 @@ static u32 volt_get_volt_rail_table(struct gk20a *g, | |||
308 | (u8)entry.ov_limit_vfe_equ_idx; | 315 | (u8)entry.ov_limit_vfe_equ_idx; |
309 | 316 | ||
310 | if (header.table_entry_size >= | 317 | if (header.table_entry_size >= |
311 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C) | 318 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C) { |
312 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | 319 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = |
313 | (u8)entry.volt_scale_exp_pwr_equ_idx; | 320 | (u8)entry.volt_scale_exp_pwr_equ_idx; |
314 | else | 321 | } else { |
315 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = | 322 | rail_type_data.volt_rail.volt_scale_exp_pwr_equ_idx = |
316 | CTRL_BOARDOBJ_IDX_INVALID; | 323 | CTRL_BOARDOBJ_IDX_INVALID; |
324 | } | ||
317 | 325 | ||
318 | if (header.table_entry_size >= | 326 | if (header.table_entry_size >= |
319 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) | 327 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B) { |
320 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = | 328 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = |
321 | (u8)entry.volt_margin_limit_vfe_equ_idx; | 329 | (u8)entry.volt_margin_limit_vfe_equ_idx; |
322 | else | 330 | } else { |
323 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = | 331 | rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx = |
324 | CTRL_BOARDOBJ_IDX_INVALID; | 332 | CTRL_BOARDOBJ_IDX_INVALID; |
333 | } | ||
325 | 334 | ||
326 | if (header.table_entry_size >= | 335 | if (header.table_entry_size >= |
327 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A) | 336 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A) { |
328 | rail_type_data.volt_rail.vmin_limit_vfe_equ_idx = | 337 | rail_type_data.volt_rail.vmin_limit_vfe_equ_idx = |
329 | (u8)entry.vmin_limit_vfe_equ_idx; | 338 | (u8)entry.vmin_limit_vfe_equ_idx; |
330 | else | 339 | } else { |
331 | rail_type_data.volt_rail.vmin_limit_vfe_equ_idx = | 340 | rail_type_data.volt_rail.vmin_limit_vfe_equ_idx = |
332 | CTRL_BOARDOBJ_IDX_INVALID; | 341 | CTRL_BOARDOBJ_IDX_INVALID; |
342 | } | ||
333 | 343 | ||
334 | if (header.table_entry_size >= | 344 | if (header.table_entry_size >= |
335 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09) | 345 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09) { |
336 | rail_type_data.volt_rail.boot_volt_vfe_equ_idx = | 346 | rail_type_data.volt_rail.boot_volt_vfe_equ_idx = |
337 | (u8)entry.boot_volt_vfe_equ_idx; | 347 | (u8)entry.boot_volt_vfe_equ_idx; |
338 | else | 348 | } else { |
339 | rail_type_data.volt_rail.boot_volt_vfe_equ_idx = | 349 | rail_type_data.volt_rail.boot_volt_vfe_equ_idx = |
340 | CTRL_BOARDOBJ_IDX_INVALID; | 350 | CTRL_BOARDOBJ_IDX_INVALID; |
351 | } | ||
341 | 352 | ||
342 | if (header.table_entry_size >= | 353 | if (header.table_entry_size >= |
343 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08) | 354 | NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08) { |
344 | rail_type_data.volt_rail.pwr_equ_idx = | 355 | rail_type_data.volt_rail.pwr_equ_idx = |
345 | (u8)entry.pwr_equ_idx; | 356 | (u8)entry.pwr_equ_idx; |
346 | else | 357 | } else { |
347 | rail_type_data.volt_rail.pwr_equ_idx = | 358 | rail_type_data.volt_rail.pwr_equ_idx = |
348 | CTRL_PMGR_PWR_EQUATION_INDEX_INVALID; | 359 | CTRL_PMGR_PWR_EQUATION_INDEX_INVALID; |
360 | } | ||
349 | 361 | ||
350 | prail = construct_volt_rail(g, &rail_type_data); | 362 | prail = construct_volt_rail(g, &rail_type_data); |
351 | 363 | ||
@@ -370,8 +382,9 @@ static u32 _volt_rail_devgrp_pmudata_instget(struct gk20a *g, | |||
370 | 382 | ||
371 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 383 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
372 | if (((u32)BIT(idx) & | 384 | if (((u32)BIT(idx) & |
373 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 385 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
374 | return -EINVAL; | 386 | return -EINVAL; |
387 | } | ||
375 | 388 | ||
376 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 389 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
377 | &pgrp_set->objects[idx].data.board_obj; | 390 | &pgrp_set->objects[idx].data.board_obj; |
@@ -389,8 +402,9 @@ static u32 _volt_rail_devgrp_pmustatus_instget(struct gk20a *g, | |||
389 | 402 | ||
390 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 403 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
391 | if (((u32)BIT(idx) & | 404 | if (((u32)BIT(idx) & |
392 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) | 405 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { |
393 | return -EINVAL; | 406 | return -EINVAL; |
407 | } | ||
394 | 408 | ||
395 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | 409 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) |
396 | &pgrp_get_status->objects[idx].data.board_obj; | 410 | &pgrp_get_status->objects[idx].data.board_obj; |
@@ -426,8 +440,9 @@ u32 volt_rail_sw_setup(struct gk20a *g) | |||
426 | /* Obtain Voltage Rail Table from VBIOS */ | 440 | /* Obtain Voltage Rail Table from VBIOS */ |
427 | status = volt_get_volt_rail_table(g, &g->perf_pmu.volt. | 441 | status = volt_get_volt_rail_table(g, &g->perf_pmu.volt. |
428 | volt_rail_metadata); | 442 | volt_rail_metadata); |
429 | if (status) | 443 | if (status) { |
430 | goto done; | 444 | goto done; |
445 | } | ||
431 | 446 | ||
432 | /* Populate data for the VOLT_RAIL PMU interface */ | 447 | /* Populate data for the VOLT_RAIL PMU interface */ |
433 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_RAIL); | 448 | BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_RAIL); |