diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 53 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 4 |
6 files changed, 9 insertions, 60 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 93687c7b..5edfe4cd 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -135,7 +135,7 @@ static inline void pmu_queue_read(struct nvgpu_pmu *pmu, | |||
135 | static inline void pmu_queue_write(struct nvgpu_pmu *pmu, | 135 | static inline void pmu_queue_write(struct nvgpu_pmu *pmu, |
136 | u32 offset, u8 *src, u32 size) | 136 | u32 offset, u8 *src, u32 size) |
137 | { | 137 | { |
138 | pmu_copy_to_dmem(pmu, offset, src, size, 0); | 138 | nvgpu_flcn_copy_to_dmem(pmu->flcn, offset, src, size, 0); |
139 | } | 139 | } |
140 | 140 | ||
141 | 141 | ||
@@ -562,7 +562,7 @@ int gk20a_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | |||
562 | payload->in.buf, payload->in.fb_size); | 562 | payload->in.buf, payload->in.fb_size); |
563 | 563 | ||
564 | } else { | 564 | } else { |
565 | pmu_copy_to_dmem(pmu, | 565 | nvgpu_flcn_copy_to_dmem(pmu->flcn, |
566 | (pv->pmu_allocation_get_dmem_offset(pmu, in)), | 566 | (pv->pmu_allocation_get_dmem_offset(pmu, in)), |
567 | payload->in.buf, payload->in.size, 0); | 567 | payload->in.buf, payload->in.size, 0); |
568 | } | 568 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 49a1870d..9d378248 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | |||
@@ -232,7 +232,7 @@ static int gk20a_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, | |||
232 | data = 0; | 232 | data = 0; |
233 | for (i = 0; i < bytes; i++) | 233 | for (i = 0; i < bytes; i++) |
234 | ((u8 *)&data)[i] = src[(words << 2) + i]; | 234 | ((u8 *)&data)[i] = src[(words << 2) + i]; |
235 | gk20a_writel(g, falcon_falcon_dmemd_r(port), data); | 235 | gk20a_writel(g, base_addr + falcon_falcon_dmemd_r(port), data); |
236 | } | 236 | } |
237 | 237 | ||
238 | size = ALIGN(size, 4); | 238 | size = ALIGN(size, 4); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index ce965992..4a676b82 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -104,57 +104,6 @@ static void printtrace(struct nvgpu_pmu *pmu) | |||
104 | nvgpu_kfree(g, tracebuffer); | 104 | nvgpu_kfree(g, tracebuffer); |
105 | } | 105 | } |
106 | 106 | ||
107 | void pmu_copy_to_dmem(struct nvgpu_pmu *pmu, | ||
108 | u32 dst, u8 *src, u32 size, u8 port) | ||
109 | { | ||
110 | struct gk20a *g = gk20a_from_pmu(pmu); | ||
111 | u32 i, words, bytes; | ||
112 | u32 data, addr_mask; | ||
113 | u32 *src_u32 = (u32*)src; | ||
114 | |||
115 | if (size == 0) { | ||
116 | nvgpu_err(g, "size is zero"); | ||
117 | return; | ||
118 | } | ||
119 | |||
120 | if (dst & 0x3) { | ||
121 | nvgpu_err(g, "dst (0x%08x) not 4-byte aligned", dst); | ||
122 | return; | ||
123 | } | ||
124 | |||
125 | nvgpu_mutex_acquire(&pmu->pmu_copy_lock); | ||
126 | |||
127 | words = size >> 2; | ||
128 | bytes = size & 0x3; | ||
129 | |||
130 | addr_mask = pwr_falcon_dmemc_offs_m() | | ||
131 | pwr_falcon_dmemc_blk_m(); | ||
132 | |||
133 | dst &= addr_mask; | ||
134 | |||
135 | gk20a_writel(g, pwr_falcon_dmemc_r(port), | ||
136 | dst | pwr_falcon_dmemc_aincw_f(1)); | ||
137 | |||
138 | for (i = 0; i < words; i++) | ||
139 | gk20a_writel(g, pwr_falcon_dmemd_r(port), src_u32[i]); | ||
140 | |||
141 | if (bytes > 0) { | ||
142 | data = 0; | ||
143 | for (i = 0; i < bytes; i++) | ||
144 | ((u8 *)&data)[i] = src[(words << 2) + i]; | ||
145 | gk20a_writel(g, pwr_falcon_dmemd_r(port), data); | ||
146 | } | ||
147 | |||
148 | data = gk20a_readl(g, pwr_falcon_dmemc_r(port)) & addr_mask; | ||
149 | size = ALIGN(size, 4); | ||
150 | if (data != ((dst + size) & addr_mask)) { | ||
151 | nvgpu_err(g, "copy failed. bytes written %d, expected %d", | ||
152 | data - dst, size); | ||
153 | } | ||
154 | nvgpu_mutex_release(&pmu->pmu_copy_lock); | ||
155 | return; | ||
156 | } | ||
157 | |||
158 | void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable) | 107 | void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable) |
159 | { | 108 | { |
160 | struct gk20a *g = gk20a_from_pmu(pmu); | 109 | struct gk20a *g = gk20a_from_pmu(pmu); |
@@ -319,7 +268,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu) | |||
319 | << GK20A_PMU_DMEM_BLKSIZE2) - | 268 | << GK20A_PMU_DMEM_BLKSIZE2) - |
320 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); | 269 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); |
321 | 270 | ||
322 | pmu_copy_to_dmem(pmu, addr_args, | 271 | nvgpu_flcn_copy_to_dmem(pmu->flcn, addr_args, |
323 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | 272 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), |
324 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | 273 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); |
325 | 274 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 43df8f24..08a58abb 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1244,7 +1244,7 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, | |||
1244 | pwr_falcon_dmemc_offs_f(0) | | 1244 | pwr_falcon_dmemc_offs_f(0) | |
1245 | pwr_falcon_dmemc_blk_f(0) | | 1245 | pwr_falcon_dmemc_blk_f(0) | |
1246 | pwr_falcon_dmemc_aincw_f(1)); | 1246 | pwr_falcon_dmemc_aincw_f(1)); |
1247 | pmu_copy_to_dmem(pmu, 0, (u8 *)pbl_desc, | 1247 | nvgpu_flcn_copy_to_dmem(pmu->flcn, 0, (u8 *)pbl_desc, |
1248 | sizeof(struct flcn_bl_dmem_desc), 0); | 1248 | sizeof(struct flcn_bl_dmem_desc), 0); |
1249 | /*TODO This had to be copied to bl_desc_dmem_load_off, but since | 1249 | /*TODO This had to be copied to bl_desc_dmem_load_off, but since |
1250 | * this is 0, so ok for now*/ | 1250 | * this is 0, so ok for now*/ |
@@ -1356,7 +1356,7 @@ static int gm20b_init_pmu_setup_hw1(struct gk20a *g, | |||
1356 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | 1356 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); |
1357 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | 1357 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( |
1358 | pmu, GK20A_PMU_DMAIDX_VIRT); | 1358 | pmu, GK20A_PMU_DMAIDX_VIRT); |
1359 | pmu_copy_to_dmem(pmu, g->acr.pmu_args, | 1359 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, |
1360 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | 1360 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), |
1361 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | 1361 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); |
1362 | /*disable irqs for hs falcon booting as we will poll for halt*/ | 1362 | /*disable irqs for hs falcon booting as we will poll for halt*/ |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 9c86c5b5..a25fc990 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -324,7 +324,7 @@ void init_pmu_setup_hw1(struct gk20a *g) | |||
324 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | 324 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( |
325 | pmu, GK20A_PMU_DMAIDX_VIRT); | 325 | pmu, GK20A_PMU_DMAIDX_VIRT); |
326 | 326 | ||
327 | pmu_copy_to_dmem(pmu, g->acr.pmu_args, | 327 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, |
328 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | 328 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), |
329 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | 329 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); |
330 | 330 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 296510bd..a1a57cd1 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -174,8 +174,8 @@ bool nvgpu_flcn_get_cpu_halted_status(struct nvgpu_falcon *flcn); | |||
174 | bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn); | 174 | bool nvgpu_flcn_get_idle_status(struct nvgpu_falcon *flcn); |
175 | int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, | 175 | int nvgpu_flcn_copy_from_dmem(struct nvgpu_falcon *flcn, |
176 | u32 src, u8 *dst, u32 size, u8 port); | 176 | u32 src, u8 *dst, u32 size, u8 port); |
177 | int nvgpu_flcn_copy_to_mem(struct nvgpu_falcon *flcn, | 177 | int nvgpu_flcn_copy_to_dmem(struct nvgpu_falcon *flcn, |
178 | enum flcn_mem_type mem_type, u32 dst, u8 *src, u32 size, u8 port); | 178 | u32 dst, u8 *src, u32 size, u8 port); |
179 | int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn, | 179 | int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn, |
180 | struct nvgpu_falcon_dma_info *dma_info); | 180 | struct nvgpu_falcon_dma_info *dma_info); |
181 | u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); | 181 | u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); |