diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_api.h | 61 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 75 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/lpwr.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/rppg.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | 3 |
6 files changed, 2 insertions, 142 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h deleted file mode 100644 index ad8a6903..00000000 --- a/drivers/gpu/nvgpu/gk20a/pmu_api.h +++ /dev/null | |||
@@ -1,61 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __PMU_API_H__ | ||
15 | #define __PMU_API_H__ | ||
16 | |||
17 | #include <nvgpu/flcnif_cmn.h> | ||
18 | #include "pmuif/gpmuif_pg_rppg.h" | ||
19 | |||
20 | /* FECS mem override command*/ | ||
21 | |||
22 | #define PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS 0 | ||
23 | |||
24 | /*! | ||
25 | * Enable/Disable FECS error feature | ||
26 | */ | ||
27 | struct pmu_cmd_lrf_tex_ltc_dram_en_dis { | ||
28 | /*Command type must be first*/ | ||
29 | u8 cmd_type; | ||
30 | /*unit bitmask*/ | ||
31 | u8 en_dis_mask; | ||
32 | }; | ||
33 | |||
34 | struct pmu_lrf_tex_ltc_dram_cmd { | ||
35 | union { | ||
36 | u8 cmd_type; | ||
37 | struct pmu_cmd_lrf_tex_ltc_dram_en_dis en_dis; | ||
38 | }; | ||
39 | }; | ||
40 | |||
41 | /* FECS mem override messages*/ | ||
42 | #define PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS 0 | ||
43 | |||
44 | struct pmu_msg_lrf_tex_ltc_dram_en_dis { | ||
45 | /*! | ||
46 | * Must be at start | ||
47 | */ | ||
48 | u8 msg_type; | ||
49 | u8 en_fail_mask; | ||
50 | u8 dis_fail_mask; | ||
51 | u32 pmu_status; | ||
52 | }; | ||
53 | |||
54 | struct pmu_lrf_tex_ltc_dram_msg { | ||
55 | union { | ||
56 | u8 msg_type; | ||
57 | struct pmu_msg_lrf_tex_ltc_dram_en_dis en_dis; | ||
58 | }; | ||
59 | }; | ||
60 | |||
61 | #endif /*__PMU_API_H__*/ | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 2f679970..47c2a4b3 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -22,7 +22,6 @@ | |||
22 | #define __PMU_GK20A_H__ | 22 | #define __PMU_GK20A_H__ |
23 | 23 | ||
24 | #include <linux/version.h> | 24 | #include <linux/version.h> |
25 | #include "pmu_api.h" | ||
26 | #include <nvgpu/flcnif_cmn.h> | 25 | #include <nvgpu/flcnif_cmn.h> |
27 | #include "pmuif/nvgpu_gpmu_cmdif.h" | 26 | #include "pmuif/nvgpu_gpmu_cmdif.h" |
28 | 27 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 3837fa60..b989e6a4 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -337,78 +337,6 @@ static int gp10b_init_pmu_setup_hw1(struct gk20a *g) | |||
337 | 337 | ||
338 | } | 338 | } |
339 | 339 | ||
340 | static void pmu_handle_ecc_en_dis_msg(struct gk20a *g, struct pmu_msg *msg, | ||
341 | void *param, u32 handle, u32 status) | ||
342 | { | ||
343 | struct pmu_gk20a *pmu = &g->pmu; | ||
344 | struct pmu_msg_lrf_tex_ltc_dram_en_dis *ecc = | ||
345 | &msg->msg.lrf_tex_ltc_dram.en_dis; | ||
346 | gk20a_dbg_fn(""); | ||
347 | |||
348 | if (status != 0) { | ||
349 | gk20a_err(dev_from_gk20a(g), "ECC en dis cmd aborted"); | ||
350 | return; | ||
351 | } | ||
352 | if (msg->msg.lrf_tex_ltc_dram.msg_type != | ||
353 | PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS) { | ||
354 | gk20a_err(dev_from_gk20a(g), | ||
355 | "Invalid msg for LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS cmd"); | ||
356 | return; | ||
357 | } else if (ecc->pmu_status != 0) { | ||
358 | gk20a_err(dev_from_gk20a(g), | ||
359 | "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg status = %x", | ||
360 | ecc->pmu_status); | ||
361 | gk20a_err(dev_from_gk20a(g), | ||
362 | "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg en fail = %x", | ||
363 | ecc->en_fail_mask); | ||
364 | gk20a_err(dev_from_gk20a(g), | ||
365 | "LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS msg dis fail = %x", | ||
366 | ecc->dis_fail_mask); | ||
367 | } else | ||
368 | pmu->override_done = 1; | ||
369 | gk20a_dbg_fn("done"); | ||
370 | } | ||
371 | |||
372 | static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) | ||
373 | { | ||
374 | struct pmu_gk20a *pmu = &g->pmu; | ||
375 | struct pmu_cmd cmd; | ||
376 | u32 seq; | ||
377 | int status; | ||
378 | u32 val; | ||
379 | gk20a_dbg_fn(""); | ||
380 | |||
381 | tegra_fuse_readl(FUSE_OPT_ECC_EN, &val); | ||
382 | if (!val) { | ||
383 | gk20a_err(dev_from_gk20a(g), "Board not ECC capable"); | ||
384 | return -1; | ||
385 | } | ||
386 | if (!(g->acr.capabilities & | ||
387 | ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE)) { | ||
388 | gk20a_err(dev_from_gk20a(g), "check ACR capabilities"); | ||
389 | return -1; | ||
390 | } | ||
391 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
392 | cmd.hdr.unit_id = PMU_UNIT_FECS_MEM_OVERRIDE; | ||
393 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
394 | sizeof(struct pmu_cmd_lrf_tex_ltc_dram_en_dis); | ||
395 | cmd.cmd.lrf_tex_ltc_dram.en_dis.cmd_type = | ||
396 | PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS; | ||
397 | cmd.cmd.lrf_tex_ltc_dram.en_dis.en_dis_mask = (u8)(bitmask & 0xff); | ||
398 | |||
399 | gp10b_dbg_pmu("cmd post PMU_ECC_CMD_ID_EN_DIS_ECC"); | ||
400 | pmu->override_done = 0; | ||
401 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_LPQ, | ||
402 | pmu_handle_ecc_en_dis_msg, NULL, &seq, ~0); | ||
403 | if (status) | ||
404 | gk20a_err(dev_from_gk20a(g), "ECC override failed"); | ||
405 | else | ||
406 | pmu_wait_message_cond(pmu, gk20a_get_gr_idle_timeout(g), | ||
407 | &pmu->override_done, 1); | ||
408 | gk20a_dbg_fn("done"); | ||
409 | return status; | ||
410 | } | ||
411 | |||
412 | static bool gp10b_is_lazy_bootstrap(u32 falcon_id) | 340 | static bool gp10b_is_lazy_bootstrap(u32 falcon_id) |
413 | { | 341 | { |
414 | bool enable_status = false; | 342 | bool enable_status = false; |
@@ -495,8 +423,7 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) | |||
495 | gops->pmu.pmu_lpwr_enable_pg = NULL; | 423 | gops->pmu.pmu_lpwr_enable_pg = NULL; |
496 | gops->pmu.pmu_lpwr_disable_pg = NULL; | 424 | gops->pmu.pmu_lpwr_disable_pg = NULL; |
497 | gops->pmu.pmu_pg_param_post_init = NULL; | 425 | gops->pmu.pmu_pg_param_post_init = NULL; |
498 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = | 426 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; |
499 | send_ecc_overide_en_dis_cmd; | ||
500 | gops->pmu.reset = gk20a_pmu_reset; | 427 | gops->pmu.reset = gk20a_pmu_reset; |
501 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gp10b; | 428 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gp10b; |
502 | } | 429 | } |
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c index e3483cca..1dc37cd2 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.c +++ b/drivers/gpu/nvgpu/lpwr/lpwr.c | |||
@@ -14,7 +14,6 @@ | |||
14 | #include "gk20a/gk20a.h" | 14 | #include "gk20a/gk20a.h" |
15 | #include "gk20a/pmu_gk20a.h" | 15 | #include "gk20a/pmu_gk20a.h" |
16 | #include "gp106/pmu_gp106.h" | 16 | #include "gp106/pmu_gp106.h" |
17 | #include "gk20a/pmu_api.h" | ||
18 | #include "gm206/bios_gm206.h" | 17 | #include "gm206/bios_gm206.h" |
19 | #include "pstate/pstate.h" | 18 | #include "pstate/pstate.h" |
20 | #include "include/bios.h" | 19 | #include "include/bios.h" |
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c index 40e857ee..cde57bf0 100644 --- a/drivers/gpu/nvgpu/lpwr/rppg.c +++ b/drivers/gpu/nvgpu/lpwr/rppg.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -14,7 +14,6 @@ | |||
14 | #include "gk20a/gk20a.h" | 14 | #include "gk20a/gk20a.h" |
15 | #include "gk20a/pmu_gk20a.h" | 15 | #include "gk20a/pmu_gk20a.h" |
16 | #include "gp106/pmu_gp106.h" | 16 | #include "gp106/pmu_gp106.h" |
17 | #include "gk20a/pmu_api.h" | ||
18 | #include "gm206/bios_gm206.h" | 17 | #include "gm206/bios_gm206.h" |
19 | #include "pstate/pstate.h" | 18 | #include "pstate/pstate.h" |
20 | #include "include/bios.h" | 19 | #include "include/bios.h" |
diff --git a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h index 751d6643..91175c69 100644 --- a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h +++ b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h | |||
@@ -13,7 +13,6 @@ | |||
13 | #ifndef _NVGPUGPMUCMDIF_H_ | 13 | #ifndef _NVGPUGPMUCMDIF_H_ |
14 | #define _NVGPUGPMUCMDIF_H_ | 14 | #define _NVGPUGPMUCMDIF_H_ |
15 | 15 | ||
16 | #include "gk20a/pmu_api.h" | ||
17 | #include <nvgpu/flcnif_cmn.h> | 16 | #include <nvgpu/flcnif_cmn.h> |
18 | #include "gpmuif_cmn.h" | 17 | #include "gpmuif_cmn.h" |
19 | #include "gpmuif_pmu.h" | 18 | #include "gpmuif_pmu.h" |
@@ -35,7 +34,6 @@ struct pmu_cmd { | |||
35 | struct pmu_pg_cmd pg; | 34 | struct pmu_pg_cmd pg; |
36 | struct pmu_zbc_cmd zbc; | 35 | struct pmu_zbc_cmd zbc; |
37 | struct pmu_acr_cmd acr; | 36 | struct pmu_acr_cmd acr; |
38 | struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram; | ||
39 | struct nv_pmu_boardobj_cmd boardobj; | 37 | struct nv_pmu_boardobj_cmd boardobj; |
40 | struct nv_pmu_perf_cmd perf; | 38 | struct nv_pmu_perf_cmd perf; |
41 | struct nv_pmu_volt_cmd volt; | 39 | struct nv_pmu_volt_cmd volt; |
@@ -53,7 +51,6 @@ struct pmu_msg { | |||
53 | struct pmu_pg_msg pg; | 51 | struct pmu_pg_msg pg; |
54 | struct pmu_rc_msg rc; | 52 | struct pmu_rc_msg rc; |
55 | struct pmu_acr_msg acr; | 53 | struct pmu_acr_msg acr; |
56 | struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram; | ||
57 | struct nv_pmu_boardobj_msg boardobj; | 54 | struct nv_pmu_boardobj_msg boardobj; |
58 | struct nv_pmu_perf_msg perf; | 55 | struct nv_pmu_perf_msg perf; |
59 | struct nv_pmu_volt_msg volt; | 56 | struct nv_pmu_volt_msg volt; |