diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 1 |
4 files changed, 29 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c index eff45cb0..6e069d99 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c | |||
@@ -333,6 +333,14 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr) | |||
333 | if (err) | 333 | if (err) |
334 | goto clean_up; | 334 | goto clean_up; |
335 | break; | 335 | break; |
336 | case NETLIST_REGIONID_CTXREG_ETPC: | ||
337 | gk20a_dbg_info("NETLIST_REGIONID_CTXREG_ETPC"); | ||
338 | err = gr_gk20a_alloc_load_netlist_aiv(g, | ||
339 | src, size, &g->gr.ctx_vars.ctxsw_regs.etpc); | ||
340 | if (err) | ||
341 | goto clean_up; | ||
342 | break; | ||
343 | |||
336 | default: | 344 | default: |
337 | gk20a_dbg_info("unrecognized region %d skipped", i); | 345 | gk20a_dbg_info("unrecognized region %d skipped", i); |
338 | break; | 346 | break; |
@@ -383,6 +391,7 @@ clean_up: | |||
383 | nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.perf_pma.l); | 391 | nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.perf_pma.l); |
384 | nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_rop.l); | 392 | nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_rop.l); |
385 | nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_ucgpc.l); | 393 | nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_ucgpc.l); |
394 | nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.etpc.l); | ||
386 | nvgpu_release_firmware(g, netlist_fw); | 395 | nvgpu_release_firmware(g, netlist_fw); |
387 | err = -ENOENT; | 396 | err = -ENOENT; |
388 | } | 397 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h index d645ed13..90041096 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h | |||
@@ -98,6 +98,7 @@ union __max_name { | |||
98 | #define NETLIST_REGIONID_NVPERF_PMA 30 | 98 | #define NETLIST_REGIONID_NVPERF_PMA 30 |
99 | #define NETLIST_REGIONID_CTXREG_PMROP 31 | 99 | #define NETLIST_REGIONID_CTXREG_PMROP 31 |
100 | #define NETLIST_REGIONID_CTXREG_PMUCGPC 32 | 100 | #define NETLIST_REGIONID_CTXREG_PMUCGPC 32 |
101 | #define NETLIST_REGIONID_CTXREG_ETPC 33 | ||
101 | 102 | ||
102 | struct netlist_region { | 103 | struct netlist_region { |
103 | u32 region_id; | 104 | u32 region_id; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c index 12ec9c5f..36071223 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c +++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GK20A Graphics Context for Simulation | 4 | * GK20A Graphics Context for Simulation |
5 | * | 5 | * |
6 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms and conditions of the GNU General Public License, | 9 | * under the terms and conditions of the GNU General Public License, |
@@ -72,6 +72,8 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
72 | &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count); | 72 | &g->gr.ctx_vars.ctxsw_regs.pm_gpc.count); |
73 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, | 73 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_PM_TPC_COUNT", 0, |
74 | &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count); | 74 | &g->gr.ctx_vars.ctxsw_regs.pm_tpc.count); |
75 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC_COUNT", 0, | ||
76 | &g->gr.ctx_vars.ctxsw_regs.etpc.count); | ||
75 | 77 | ||
76 | err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst); | 78 | err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.inst); |
77 | err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.data); | 79 | err |= !alloc_u32_list_gk20a(g, &g->gr.ctx_vars.ucode.fecs.data); |
@@ -90,6 +92,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
90 | err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_sys); | 92 | err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_sys); |
91 | err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_gpc); | 93 | err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_gpc); |
92 | err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_tpc); | 94 | err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.pm_tpc); |
95 | err |= !alloc_aiv_list_gk20a(g, &g->gr.ctx_vars.ctxsw_regs.etpc); | ||
93 | 96 | ||
94 | if (err) | 97 | if (err) |
95 | goto fail; | 98 | goto fail; |
@@ -233,6 +236,20 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr) | |||
233 | i, &l[i].value); | 236 | i, &l[i].value); |
234 | } | 237 | } |
235 | 238 | ||
239 | gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, "query GRCTX_REG_LIST_ETPC"); | ||
240 | for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.etpc.count; i++) { | ||
241 | struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.etpc.l; | ||
242 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:ADDR", | ||
243 | i, &l[i].addr); | ||
244 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:INDEX", | ||
245 | i, &l[i].index); | ||
246 | gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_ETPC:VALUE", | ||
247 | i, &l[i].value); | ||
248 | gk20a_dbg(gpu_dbg_info | gpu_dbg_fn, | ||
249 | "addr:0x%#08x index:0x%08x value:0x%08x", | ||
250 | l[i].addr, l[i].index, l[i].value); | ||
251 | } | ||
252 | |||
236 | g->gr.ctx_vars.valid = true; | 253 | g->gr.ctx_vars.valid = true; |
237 | 254 | ||
238 | gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, | 255 | gk20a_sim_esc_readl(g, "GRCTX_GEN_CTX_REGS_BASE_INDEX", 0, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 436377bd..d32a719e 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -270,6 +270,7 @@ struct gr_gk20a { | |||
270 | struct aiv_list_gk20a perf_pma; | 270 | struct aiv_list_gk20a perf_pma; |
271 | struct aiv_list_gk20a pm_rop; | 271 | struct aiv_list_gk20a pm_rop; |
272 | struct aiv_list_gk20a pm_ucgpc; | 272 | struct aiv_list_gk20a pm_ucgpc; |
273 | struct aiv_list_gk20a etpc; | ||
273 | } ctxsw_regs; | 274 | } ctxsw_regs; |
274 | int regs_base_index; | 275 | int regs_base_index; |
275 | bool valid; | 276 | bool valid; |