diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_domain.c | 60 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_domain.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlclk.h | 41 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | 53 |
4 files changed, 127 insertions, 43 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index dbbf4d4a..1d47d2d5 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -39,8 +39,8 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
39 | static u32 clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj | 39 | static u32 clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj |
40 | *board_obj_ptr, struct nv_pmu_boardobj *ppmudata); | 40 | *board_obj_ptr, struct nv_pmu_boardobj *ppmudata); |
41 | 41 | ||
42 | static const struct vbios_clocks_table_1x_hal_clock_entry | 42 | static struct vbios_clocks_table_1x_hal_clock_entry |
43 | vbiosclktbl1xhalentry[] = { | 43 | vbiosclktbl1xhalentry_gp[] = { |
44 | { clkwhich_gpc2clk, true, }, | 44 | { clkwhich_gpc2clk, true, }, |
45 | { clkwhich_xbar2clk, true, }, | 45 | { clkwhich_xbar2clk, true, }, |
46 | { clkwhich_mclk, false, }, | 46 | { clkwhich_mclk, false, }, |
@@ -51,11 +51,39 @@ static const struct vbios_clocks_table_1x_hal_clock_entry | |||
51 | { clkwhich_dispclk, false, }, | 51 | { clkwhich_dispclk, false, }, |
52 | { clkwhich_pciegenclk, false, } | 52 | { clkwhich_pciegenclk, false, } |
53 | }; | 53 | }; |
54 | /* | ||
55 | * Updated from RM devinit_clock.c | ||
56 | * GV100 is 0x03 and | ||
57 | * GP10x is 0x02 in clocks_hal. | ||
58 | */ | ||
59 | static struct vbios_clocks_table_1x_hal_clock_entry | ||
60 | vbiosclktbl1xhalentry_gv[] = { | ||
61 | { clkwhich_gpcclk, true, }, | ||
62 | { clkwhich_xbarclk, true, }, | ||
63 | { clkwhich_mclk, false, }, | ||
64 | { clkwhich_sysclk, true, }, | ||
65 | { clkwhich_hubclk, false, }, | ||
66 | { clkwhich_nvdclk, true, }, | ||
67 | { clkwhich_pwrclk, false, }, | ||
68 | { clkwhich_dispclk, false, }, | ||
69 | { clkwhich_pciegenclk, false, }, | ||
70 | { clkwhich_hostclk, true, } | ||
71 | }; | ||
54 | 72 | ||
55 | static u32 clktranslatehalmumsettoapinumset(u32 clkhaldomains) | 73 | static u32 clktranslatehalmumsettoapinumset(u32 clkhaldomains) |
56 | { | 74 | { |
57 | u32 clkapidomains = 0; | 75 | u32 clkapidomains = 0; |
58 | 76 | ||
77 | if (clkhaldomains & BIT(clkwhich_gpcclk)) | ||
78 | clkapidomains |= CTRL_CLK_DOMAIN_GPCCLK; | ||
79 | if (clkhaldomains & BIT(clkwhich_xbarclk)) | ||
80 | clkapidomains |= CTRL_CLK_DOMAIN_XBARCLK; | ||
81 | if (clkhaldomains & BIT(clkwhich_sysclk)) | ||
82 | clkapidomains |= CTRL_CLK_DOMAIN_SYSCLK; | ||
83 | if (clkhaldomains & BIT(clkwhich_hubclk)) | ||
84 | clkapidomains |= CTRL_CLK_DOMAIN_HUBCLK; | ||
85 | if (clkhaldomains & BIT(clkwhich_hostclk)) | ||
86 | clkapidomains |= CTRL_CLK_DOMAIN_HOSTCLK; | ||
59 | if (clkhaldomains & BIT(clkwhich_gpc2clk)) | 87 | if (clkhaldomains & BIT(clkwhich_gpc2clk)) |
60 | clkapidomains |= CTRL_CLK_DOMAIN_GPC2CLK; | 88 | clkapidomains |= CTRL_CLK_DOMAIN_GPC2CLK; |
61 | if (clkhaldomains & BIT(clkwhich_xbar2clk)) | 89 | if (clkhaldomains & BIT(clkwhich_xbar2clk)) |
@@ -98,6 +126,7 @@ static u32 _clk_domains_pmudatainit_3x(struct gk20a *g, | |||
98 | 126 | ||
99 | pset->vbios_domains = pdomains->vbios_domains; | 127 | pset->vbios_domains = pdomains->vbios_domains; |
100 | pset->cntr_sampling_periodms = pdomains->cntr_sampling_periodms; | 128 | pset->cntr_sampling_periodms = pdomains->cntr_sampling_periodms; |
129 | pset->version = CLK_DOMAIN_BOARDOBJGRP_VERSION; | ||
101 | pset->b_override_o_v_o_c = false; | 130 | pset->b_override_o_v_o_c = false; |
102 | pset->b_debug_mode = false; | 131 | pset->b_debug_mode = false; |
103 | pset->b_enforce_vf_monotonicity = pdomains->b_enforce_vf_monotonicity; | 132 | pset->b_enforce_vf_monotonicity = pdomains->b_enforce_vf_monotonicity; |
@@ -255,6 +284,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
255 | u8 *clocks_table_ptr = NULL; | 284 | u8 *clocks_table_ptr = NULL; |
256 | struct vbios_clocks_table_1x_header clocks_table_header = { 0 }; | 285 | struct vbios_clocks_table_1x_header clocks_table_header = { 0 }; |
257 | struct vbios_clocks_table_1x_entry clocks_table_entry = { 0 }; | 286 | struct vbios_clocks_table_1x_entry clocks_table_entry = { 0 }; |
287 | struct vbios_clocks_table_1x_hal_clock_entry *vbiosclktbl1xhalentry; | ||
258 | u8 *clocks_tbl_entry_ptr = NULL; | 288 | u8 *clocks_tbl_entry_ptr = NULL; |
259 | u32 index = 0; | 289 | u32 index = 0; |
260 | struct clk_domain *pclkdomain_dev; | 290 | struct clk_domain *pclkdomain_dev; |
@@ -291,6 +321,18 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
291 | goto done; | 321 | goto done; |
292 | } | 322 | } |
293 | 323 | ||
324 | switch (clocks_table_header.clocks_hal) { | ||
325 | case CLK_TABLE_HAL_ENTRY_GP: | ||
326 | vbiosclktbl1xhalentry = vbiosclktbl1xhalentry_gp; | ||
327 | break; | ||
328 | case CLK_TABLE_HAL_ENTRY_GV: | ||
329 | vbiosclktbl1xhalentry = vbiosclktbl1xhalentry_gv; | ||
330 | break; | ||
331 | default: | ||
332 | status = -EINVAL; | ||
333 | goto done; | ||
334 | } | ||
335 | |||
294 | pclkdomainobjs->cntr_sampling_periodms = | 336 | pclkdomainobjs->cntr_sampling_periodms = |
295 | (u16)clocks_table_header.cntr_sampling_periodms; | 337 | (u16)clocks_table_header.cntr_sampling_periodms; |
296 | 338 | ||
@@ -330,7 +372,6 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
330 | clk_domain_data.v3x_prog.noise_unaware_ordering_index = | 372 | clk_domain_data.v3x_prog.noise_unaware_ordering_index = |
331 | (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, | 373 | (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, |
332 | NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX)); | 374 | NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX)); |
333 | |||
334 | if (clk_domain_data.v3x.b_noise_aware_capable) { | 375 | if (clk_domain_data.v3x.b_noise_aware_capable) { |
335 | clk_domain_data.v3x_prog.noise_aware_ordering_index = | 376 | clk_domain_data.v3x_prog.noise_aware_ordering_index = |
336 | (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, | 377 | (u8)(BIOS_GET_FIELD(clocks_table_entry.param2, |
@@ -343,7 +384,9 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
343 | CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID; | 384 | CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID; |
344 | clk_domain_data.v3x_prog.b_force_noise_unaware_ordering = false; | 385 | clk_domain_data.v3x_prog.b_force_noise_unaware_ordering = false; |
345 | } | 386 | } |
346 | clk_domain_data.v3x_prog.factory_offset_khz = 0; | 387 | |
388 | clk_domain_data.v3x_prog.factory_delta.data.delta_khz = 0; | ||
389 | clk_domain_data.v3x_prog.factory_delta.type = 0; | ||
347 | 390 | ||
348 | clk_domain_data.v3x_prog.freq_delta_min_mhz = | 391 | clk_domain_data.v3x_prog.freq_delta_min_mhz = |
349 | (u16)(BIOS_GET_FIELD(clocks_table_entry.param1, | 392 | (u16)(BIOS_GET_FIELD(clocks_table_entry.param1, |
@@ -379,7 +422,8 @@ static u32 devinit_get_clocks_table(struct gk20a *g, | |||
379 | CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID; | 422 | CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID; |
380 | clk_domain_data.v3x_prog.b_force_noise_unaware_ordering = false; | 423 | clk_domain_data.v3x_prog.b_force_noise_unaware_ordering = false; |
381 | } | 424 | } |
382 | clk_domain_data.v3x_prog.factory_offset_khz = 0; | 425 | clk_domain_data.v3x_prog.factory_delta.data.delta_khz = 0; |
426 | clk_domain_data.v3x_prog.factory_delta.type = 0; | ||
383 | clk_domain_data.v3x_prog.freq_delta_min_mhz = 0; | 427 | clk_domain_data.v3x_prog.freq_delta_min_mhz = 0; |
384 | clk_domain_data.v3x_prog.freq_delta_max_mhz = 0; | 428 | clk_domain_data.v3x_prog.freq_delta_max_mhz = 0; |
385 | clk_domain_data.v3x_slave.master_idx = | 429 | clk_domain_data.v3x_slave.master_idx = |
@@ -771,7 +815,7 @@ static u32 _clk_domain_pmudatainit_3x_prog(struct gk20a *g, | |||
771 | pclk_domain_3x_prog->noise_aware_ordering_index; | 815 | pclk_domain_3x_prog->noise_aware_ordering_index; |
772 | pset->b_force_noise_unaware_ordering = | 816 | pset->b_force_noise_unaware_ordering = |
773 | pclk_domain_3x_prog->b_force_noise_unaware_ordering; | 817 | pclk_domain_3x_prog->b_force_noise_unaware_ordering; |
774 | pset->factory_offset_khz = pclk_domain_3x_prog->factory_offset_khz; | 818 | pset->factory_delta = pclk_domain_3x_prog->factory_delta; |
775 | pset->freq_delta_min_mhz = pclk_domain_3x_prog->freq_delta_min_mhz; | 819 | pset->freq_delta_min_mhz = pclk_domain_3x_prog->freq_delta_min_mhz; |
776 | pset->freq_delta_max_mhz = pclk_domain_3x_prog->freq_delta_max_mhz; | 820 | pset->freq_delta_max_mhz = pclk_domain_3x_prog->freq_delta_max_mhz; |
777 | memcpy(&pset->deltas, &pdomains->deltas, | 821 | memcpy(&pset->deltas, &pdomains->deltas, |
@@ -817,7 +861,7 @@ static u32 clk_domain_construct_3x_prog(struct gk20a *g, | |||
817 | ptmpdomain->noise_aware_ordering_index; | 861 | ptmpdomain->noise_aware_ordering_index; |
818 | pdomain->b_force_noise_unaware_ordering = | 862 | pdomain->b_force_noise_unaware_ordering = |
819 | ptmpdomain->b_force_noise_unaware_ordering; | 863 | ptmpdomain->b_force_noise_unaware_ordering; |
820 | pdomain->factory_offset_khz = ptmpdomain->factory_offset_khz; | 864 | pdomain->factory_delta = ptmpdomain->factory_delta; |
821 | pdomain->freq_delta_min_mhz = ptmpdomain->freq_delta_min_mhz; | 865 | pdomain->freq_delta_min_mhz = ptmpdomain->freq_delta_min_mhz; |
822 | pdomain->freq_delta_max_mhz = ptmpdomain->freq_delta_max_mhz; | 866 | pdomain->freq_delta_max_mhz = ptmpdomain->freq_delta_max_mhz; |
823 | 867 | ||
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.h b/drivers/gpu/nvgpu/clk/clk_domain.h index 5374d643..4c4a0de2 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.h +++ b/drivers/gpu/nvgpu/clk/clk_domain.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -29,6 +29,10 @@ | |||
29 | #include "boardobj/boardobjgrp_e32.h" | 29 | #include "boardobj/boardobjgrp_e32.h" |
30 | #include "boardobj/boardobjgrpmask.h" | 30 | #include "boardobj/boardobjgrpmask.h" |
31 | 31 | ||
32 | #define CLK_DOMAIN_BOARDOBJGRP_VERSION 0x30 | ||
33 | #define CLK_TABLE_HAL_ENTRY_GP 0x02 | ||
34 | #define CLK_TABLE_HAL_ENTRY_GV 0x03 | ||
35 | |||
32 | struct clk_domains; | 36 | struct clk_domains; |
33 | struct clk_domain; | 37 | struct clk_domain; |
34 | 38 | ||
@@ -57,10 +61,12 @@ struct clk_domains { | |||
57 | u8 version; | 61 | u8 version; |
58 | bool b_enforce_vf_monotonicity; | 62 | bool b_enforce_vf_monotonicity; |
59 | bool b_enforce_vf_smoothening; | 63 | bool b_enforce_vf_smoothening; |
64 | bool b_override_o_v_o_c; | ||
65 | bool b_debug_mode; | ||
60 | u32 vbios_domains; | 66 | u32 vbios_domains; |
67 | u16 cntr_sampling_periodms; | ||
61 | struct boardobjgrpmask_e32 prog_domains_mask; | 68 | struct boardobjgrpmask_e32 prog_domains_mask; |
62 | struct boardobjgrpmask_e32 master_domains_mask; | 69 | struct boardobjgrpmask_e32 master_domains_mask; |
63 | u16 cntr_sampling_periodms; | ||
64 | struct ctrl_clk_clk_delta deltas; | 70 | struct ctrl_clk_clk_delta deltas; |
65 | 71 | ||
66 | struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS]; | 72 | struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS]; |
@@ -96,13 +102,13 @@ struct clk_domain_3x_prog { | |||
96 | struct clk_domain_3x super; | 102 | struct clk_domain_3x super; |
97 | u8 clk_prog_idx_first; | 103 | u8 clk_prog_idx_first; |
98 | u8 clk_prog_idx_last; | 104 | u8 clk_prog_idx_last; |
99 | u8 noise_unaware_ordering_index; | ||
100 | u8 noise_aware_ordering_index; | ||
101 | bool b_force_noise_unaware_ordering; | 105 | bool b_force_noise_unaware_ordering; |
102 | int factory_offset_khz; | 106 | struct ctrl_clk_freq_delta factory_delta; |
103 | short freq_delta_min_mhz; | 107 | short freq_delta_min_mhz; |
104 | short freq_delta_max_mhz; | 108 | short freq_delta_max_mhz; |
105 | struct ctrl_clk_clk_delta deltas; | 109 | struct ctrl_clk_clk_delta deltas; |
110 | u8 noise_unaware_ordering_index; | ||
111 | u8 noise_aware_ordering_index; | ||
106 | }; | 112 | }; |
107 | 113 | ||
108 | struct clk_domain_3x_master { | 114 | struct clk_domain_3x_master { |
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlclk.h b/drivers/gpu/nvgpu/ctrl/ctrlclk.h index 4834ed24..6e56235b 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlclk.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlclk.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * general p state infrastructure | 2 | * general p state infrastructure |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -32,19 +32,20 @@ | |||
32 | 32 | ||
33 | /* valid clock domain values */ | 33 | /* valid clock domain values */ |
34 | #define CTRL_CLK_DOMAIN_MCLK (0x00000010) | 34 | #define CTRL_CLK_DOMAIN_MCLK (0x00000010) |
35 | #define CTRL_CLK_DOMAIN_HOSTCLK (0x00000020) | ||
35 | #define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) | 36 | #define CTRL_CLK_DOMAIN_DISPCLK (0x00000040) |
36 | #define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) | 37 | #define CTRL_CLK_DOMAIN_GPC2CLK (0x00010000) |
37 | #define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) | 38 | #define CTRL_CLK_DOMAIN_XBAR2CLK (0x00040000) |
38 | #define CTRL_CLK_DOMAIN_SYS2CLK (0x00080000) | 39 | #define CTRL_CLK_DOMAIN_SYS2CLK (0x00800000) |
39 | #define CTRL_CLK_DOMAIN_HUB2CLK (0x00100000) | 40 | #define CTRL_CLK_DOMAIN_HUB2CLK (0x01000000) |
40 | #define CTRL_CLK_DOMAIN_PWRCLK (0x00800000) | 41 | #define CTRL_CLK_DOMAIN_PWRCLK (0x00080000) |
41 | #define CTRL_CLK_DOMAIN_NVDCLK (0x01000000) | 42 | #define CTRL_CLK_DOMAIN_NVDCLK (0x00100000) |
42 | #define CTRL_CLK_DOMAIN_PCIEGENCLK (0x02000000) | 43 | #define CTRL_CLK_DOMAIN_PCIEGENCLK (0x00200000) |
43 | 44 | ||
44 | #define CTRL_CLK_DOMAIN_GPCCLK (0x10000000) | 45 | #define CTRL_CLK_DOMAIN_GPCCLK (0x00000001) |
45 | #define CTRL_CLK_DOMAIN_XBARCLK (0x20000000) | 46 | #define CTRL_CLK_DOMAIN_XBARCLK (0x00000002) |
46 | #define CTRL_CLK_DOMAIN_SYSCLK (0x40000000) | 47 | #define CTRL_CLK_DOMAIN_SYSCLK (0x00000004) |
47 | #define CTRL_CLK_DOMAIN_HUBCLK (0x80000000) | 48 | #define CTRL_CLK_DOMAIN_HUBCLK (0x00000008) |
48 | 49 | ||
49 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 | 50 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X 0x01 |
50 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 | 51 | #define CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED 0x02 |
@@ -55,10 +56,10 @@ | |||
55 | #define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF | 56 | #define CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID 0xFF |
56 | #define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF | 57 | #define CTRL_CLK_CLK_DOMAIN_INDEX_INVALID 0xFF |
57 | 58 | ||
58 | #define CTRL_CLK_CLK_PROG_TYPE_1X 0x00 | 59 | #define CTRL_CLK_CLK_PROG_TYPE_1X 0x01 |
59 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x01 | 60 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER 0x02 |
60 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x02 | 61 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_RATIO 0x03 |
61 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x03 | 62 | #define CTRL_CLK_CLK_PROG_TYPE_1X_MASTER_TABLE 0x04 |
62 | #define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 | 63 | #define CTRL_CLK_CLK_PROG_TYPE_UNKNOWN 255 |
63 | 64 | ||
64 | /*! | 65 | /*! |
@@ -120,10 +121,18 @@ struct ctrl_clk_clk_prog_1x_source_pll { | |||
120 | u8 freq_step_size_mhz; | 121 | u8 freq_step_size_mhz; |
121 | }; | 122 | }; |
122 | 123 | ||
124 | union ctrl_clk_freq_delta_data { | ||
125 | s32 delta_khz; | ||
126 | s16 delta_percent; | ||
127 | }; | ||
128 | struct ctrl_clk_freq_delta { | ||
129 | u8 type; | ||
130 | union ctrl_clk_freq_delta_data data; | ||
131 | }; | ||
132 | |||
123 | struct ctrl_clk_clk_delta { | 133 | struct ctrl_clk_clk_delta { |
124 | int freq_delta_khz; | 134 | struct ctrl_clk_freq_delta freq_delta; |
125 | int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; | 135 | int volt_deltauv[CTRL_CLK_CLK_DELTA_MAX_VOLT_RAILS]; |
126 | |||
127 | }; | 136 | }; |
128 | 137 | ||
129 | union ctrl_clk_clk_prog_1x_source_data { | 138 | union ctrl_clk_clk_prog_1x_source_data { |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h index 2ea0c548..81a1d72e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -31,16 +31,34 @@ | |||
31 | #include "gpmuifvolt.h" | 31 | #include "gpmuifvolt.h" |
32 | #include <nvgpu/flcnif_cmn.h> | 32 | #include <nvgpu/flcnif_cmn.h> |
33 | 33 | ||
34 | |||
35 | /* | ||
36 | * Try to get gpc2clk, mclk, sys2clk, xbar2clk work for Pascal | ||
37 | * | ||
38 | * mclk is same for both | ||
39 | * gpc2clk is 17 for Pascal and 13 for Volta, making it 17 | ||
40 | * as volta uses gpcclk | ||
41 | * sys2clk is 20 in Pascal and 15 in Volta. | ||
42 | * Changing for Pascal would break nvdclk of Volta | ||
43 | * xbar2clk is 19 in Pascal and 14 in Volta | ||
44 | * Changing for Pascal would break pwrclk of Volta | ||
45 | */ | ||
34 | enum nv_pmu_clk_clkwhich { | 46 | enum nv_pmu_clk_clkwhich { |
35 | clkwhich_mclk = 5, | 47 | clkwhich_gpcclk = 1, |
36 | clkwhich_dispclk = 7, | 48 | clkwhich_xbarclk = 2, |
37 | clkwhich_gpc2clk = 17, | 49 | clkwhich_sysclk = 3, |
38 | clkwhich_xbar2clk = 19, | 50 | clkwhich_hubclk = 4, |
39 | clkwhich_sys2clk = 20, | 51 | clkwhich_mclk = 5, |
40 | clkwhich_hub2clk = 21, | 52 | clkwhich_hostclk = 6, |
41 | clkwhich_pwrclk = 24, | 53 | clkwhich_dispclk = 7, |
42 | clkwhich_nvdclk = 25, | 54 | clkwhich_xclk = 12, |
43 | clkwhich_pciegenclk = 31, | 55 | clkwhich_gpc2clk = 17, |
56 | clkwhich_xbar2clk = 14, | ||
57 | clkwhich_sys2clk = 15, | ||
58 | clkwhich_hub2clk = 16, | ||
59 | clkwhich_pwrclk = 19, | ||
60 | clkwhich_nvdclk = 20, | ||
61 | clkwhich_pciegenclk = 26, | ||
44 | }; | 62 | }; |
45 | 63 | ||
46 | /* | 64 | /* |
@@ -62,8 +80,10 @@ enum nv_pmu_clk_clkwhich { | |||
62 | struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { | 80 | struct nv_pmu_clk_clk_domain_boardobjgrp_set_header { |
63 | struct nv_pmu_boardobjgrp_e32 super; | 81 | struct nv_pmu_boardobjgrp_e32 super; |
64 | u32 vbios_domains; | 82 | u32 vbios_domains; |
83 | struct ctrl_boardobjgrp_mask_e32 prog_domains_mask; | ||
65 | struct ctrl_boardobjgrp_mask_e32 master_domains_mask; | 84 | struct ctrl_boardobjgrp_mask_e32 master_domains_mask; |
66 | u16 cntr_sampling_periodms; | 85 | u16 cntr_sampling_periodms; |
86 | u8 version; | ||
67 | bool b_override_o_v_o_c; | 87 | bool b_override_o_v_o_c; |
68 | bool b_debug_mode; | 88 | bool b_debug_mode; |
69 | bool b_enforce_vf_monotonicity; | 89 | bool b_enforce_vf_monotonicity; |
@@ -93,22 +113,24 @@ struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set { | |||
93 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; | 113 | struct nv_pmu_clk_clk_domain_3x_boardobj_set super; |
94 | u8 clk_prog_idx_first; | 114 | u8 clk_prog_idx_first; |
95 | u8 clk_prog_idx_last; | 115 | u8 clk_prog_idx_last; |
96 | u8 noise_unaware_ordering_index; | ||
97 | u8 noise_aware_ordering_index; | ||
98 | bool b_force_noise_unaware_ordering; | 116 | bool b_force_noise_unaware_ordering; |
99 | int factory_offset_khz; | 117 | struct ctrl_clk_freq_delta factory_delta; |
100 | short freq_delta_min_mhz; | 118 | short freq_delta_min_mhz; |
101 | short freq_delta_max_mhz; | 119 | short freq_delta_max_mhz; |
102 | struct ctrl_clk_clk_delta deltas; | 120 | struct ctrl_clk_clk_delta deltas; |
121 | u8 noise_unaware_ordering_index; | ||
122 | u8 noise_aware_ordering_index; | ||
103 | }; | 123 | }; |
104 | 124 | ||
105 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { | 125 | struct nv_pmu_clk_clk_domain_3x_master_boardobj_set { |
106 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | 126 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; |
127 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
107 | u32 slave_idxs_mask; | 128 | u32 slave_idxs_mask; |
108 | }; | 129 | }; |
109 | 130 | ||
110 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { | 131 | struct nv_pmu_clk_clk_domain_3x_slave_boardobj_set { |
111 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; | 132 | struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set super; |
133 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
112 | u8 master_idx; | 134 | u8 master_idx; |
113 | }; | 135 | }; |
114 | 136 | ||
@@ -143,21 +165,24 @@ struct nv_pmu_clk_clk_prog_1x_boardobj_set { | |||
143 | 165 | ||
144 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { | 166 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set { |
145 | struct nv_pmu_clk_clk_prog_1x_boardobj_set super; | 167 | struct nv_pmu_clk_clk_prog_1x_boardobj_set super; |
168 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
146 | bool b_o_c_o_v_enabled; | 169 | bool b_o_c_o_v_enabled; |
147 | struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ | 170 | struct ctrl_clk_clk_prog_1x_master_vf_entry vf_entries[ |
148 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; | 171 | CTRL_CLK_CLK_PROG_1X_MASTER_VF_ENTRY_MAX_ENTRIES]; |
149 | union ctrl_clk_clk_prog_1x_master_source_data source_data; | ||
150 | struct ctrl_clk_clk_delta deltas; | 172 | struct ctrl_clk_clk_delta deltas; |
173 | union ctrl_clk_clk_prog_1x_master_source_data source_data; | ||
151 | }; | 174 | }; |
152 | 175 | ||
153 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { | 176 | struct nv_pmu_clk_clk_prog_1x_master_ratio_boardobj_set { |
154 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | 177 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; |
178 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
155 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ | 179 | struct ctrl_clk_clk_prog_1x_master_ratio_slave_entry slave_entries[ |
156 | CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | 180 | CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; |
157 | }; | 181 | }; |
158 | 182 | ||
159 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { | 183 | struct nv_pmu_clk_clk_prog_1x_master_table_boardobj_set { |
160 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; | 184 | struct nv_pmu_clk_clk_prog_1x_master_boardobj_set super; |
185 | u8 rsvd; /* Stubbing for RM_PMU_BOARDOBJ_INTERFACE */ | ||
161 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry | 186 | struct ctrl_clk_clk_prog_1x_master_table_slave_entry |
162 | slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; | 187 | slave_entries[CTRL_CLK_PROG_1X_MASTER_MAX_SLAVE_ENTRIES]; |
163 | }; | 188 | }; |