diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index a4d7a0f7..6832bf41 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -202,6 +202,60 @@ static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
202 | return 0; | 202 | return 0; |
203 | } | 203 | } |
204 | 204 | ||
205 | static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, | ||
206 | void *param, u32 handle, u32 status) | ||
207 | { | ||
208 | gk20a_dbg_fn(""); | ||
209 | |||
210 | if (status != 0) { | ||
211 | gk20a_err(dev_from_gk20a(g), "GR PARAM cmd aborted"); | ||
212 | /* TBD: disable ELPG */ | ||
213 | return; | ||
214 | } | ||
215 | |||
216 | gp10b_dbg_pmu("GR PARAM is acknowledged from PMU %x \n", | ||
217 | msg->msg.pg.msg_type); | ||
218 | |||
219 | return; | ||
220 | } | ||
221 | |||
222 | static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) | ||
223 | { | ||
224 | struct pmu_gk20a *pmu = &g->pmu; | ||
225 | struct pmu_cmd cmd; | ||
226 | u32 seq; | ||
227 | |||
228 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
229 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
230 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
231 | sizeof(struct pmu_pg_cmd_gr_init_param); | ||
232 | cmd.cmd.pg.gr_init_param.cmd_type = | ||
233 | PMU_PG_CMD_ID_PG_PARAM; | ||
234 | cmd.cmd.pg.gr_init_param.sub_cmd_id = | ||
235 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; | ||
236 | cmd.cmd.pg.gr_init_param.featuremask = | ||
237 | grfeaturemask; | ||
238 | |||
239 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM %x", grfeaturemask); | ||
240 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
241 | pmu_handle_gr_param_msg, pmu, &seq, ~0); | ||
242 | |||
243 | return 0; | ||
244 | } | ||
245 | void gp10b_pmu_elpg_statistics(struct gk20a *g, | ||
246 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) | ||
247 | { | ||
248 | struct pmu_gk20a *pmu = &g->pmu; | ||
249 | struct pmu_pg_stats_v1 stats; | ||
250 | |||
251 | pmu_copy_from_dmem(pmu, pmu->stat_dmem_offset, | ||
252 | (u8 *)&stats, sizeof(struct pmu_pg_stats_v1), 0); | ||
253 | |||
254 | *ingating_time = stats.total_sleep_timeus; | ||
255 | *ungating_time = stats.total_nonsleep_timeus; | ||
256 | *gating_cnt = stats.entry_count; | ||
257 | } | ||
258 | |||
205 | static int gp10b_pmu_setup_elpg(struct gk20a *g) | 259 | static int gp10b_pmu_setup_elpg(struct gk20a *g) |
206 | { | 260 | { |
207 | int ret = 0; | 261 | int ret = 0; |
@@ -249,4 +303,6 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops) | |||
249 | gops->pmu.lspmuwprinitdone = false; | 303 | gops->pmu.lspmuwprinitdone = false; |
250 | gops->pmu.fecsbootstrapdone = false; | 304 | gops->pmu.fecsbootstrapdone = false; |
251 | gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; | 305 | gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; |
306 | gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; | ||
307 | gops->pmu.pmu_pg_grinit_param = gp10b_pg_gr_init; | ||
252 | } | 308 | } |