diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 41 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 18 |
3 files changed, 44 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 47256e24..d3dc03e7 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -187,6 +187,8 @@ struct gpu_ops { | |||
187 | void (*enable_cde_in_fecs)(void *ctx_ptr); | 187 | void (*enable_cde_in_fecs)(void *ctx_ptr); |
188 | void (*bpt_reg_info)(struct gk20a *g, | 188 | void (*bpt_reg_info)(struct gk20a *g, |
189 | struct warpstate *w_state); | 189 | struct warpstate *w_state); |
190 | void (*get_access_map)(struct gk20a *g, | ||
191 | u32 **whitelist, int *num_entries); | ||
190 | } gr; | 192 | } gr; |
191 | const char *name; | 193 | const char *name; |
192 | struct { | 194 | struct { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 9eea0a0c..adb4b276 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4280,20 +4280,6 @@ out: | |||
4280 | return 0; | 4280 | return 0; |
4281 | } | 4281 | } |
4282 | 4282 | ||
4283 | /* | ||
4284 | * XXX Merge this list with the debugger/profiler | ||
4285 | * session regops whitelists? | ||
4286 | */ | ||
4287 | static u32 wl_addr_gk20a[] = { | ||
4288 | /* this list must be sorted (low to high) */ | ||
4289 | 0x404468, /* gr_pri_mme_max_instructions */ | ||
4290 | 0x418800, /* gr_pri_gpcs_setup_debug */ | ||
4291 | 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ | ||
4292 | 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ | ||
4293 | 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ | ||
4294 | 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ | ||
4295 | }; | ||
4296 | |||
4297 | static int gr_gk20a_init_access_map(struct gk20a *g) | 4283 | static int gr_gk20a_init_access_map(struct gk20a *g) |
4298 | { | 4284 | { |
4299 | struct gr_gk20a *gr = &g->gr; | 4285 | struct gr_gk20a *gr = &g->gr; |
@@ -4302,6 +4288,8 @@ static int gr_gk20a_init_access_map(struct gk20a *g) | |||
4302 | u32 w, nr_pages = | 4288 | u32 w, nr_pages = |
4303 | DIV_ROUND_UP(gr->ctx_vars.priv_access_map_size, | 4289 | DIV_ROUND_UP(gr->ctx_vars.priv_access_map_size, |
4304 | PAGE_SIZE); | 4290 | PAGE_SIZE); |
4291 | u32 *whitelist = NULL; | ||
4292 | int num_entries = 0; | ||
4305 | 4293 | ||
4306 | data = vmap(gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.pages, | 4294 | data = vmap(gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.pages, |
4307 | PAGE_ALIGN(gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size) >> | 4295 | PAGE_ALIGN(gr->global_ctx_buffer[PRIV_ACCESS_MAP].mem.size) >> |
@@ -4315,13 +4303,15 @@ static int gr_gk20a_init_access_map(struct gk20a *g) | |||
4315 | 4303 | ||
4316 | memset(data, 0x0, PAGE_SIZE * nr_pages); | 4304 | memset(data, 0x0, PAGE_SIZE * nr_pages); |
4317 | 4305 | ||
4318 | for (w = 0; w < ARRAY_SIZE(wl_addr_gk20a); w++) { | 4306 | g->ops.gr.get_access_map(g, &whitelist, &num_entries); |
4307 | |||
4308 | for (w = 0; w < num_entries; w++) { | ||
4319 | u32 map_bit, map_byte, map_shift; | 4309 | u32 map_bit, map_byte, map_shift; |
4320 | map_bit = wl_addr_gk20a[w] >> 2; | 4310 | map_bit = whitelist[w] >> 2; |
4321 | map_byte = map_bit >> 3; | 4311 | map_byte = map_bit >> 3; |
4322 | map_shift = map_bit & 0x7; /* i.e. 0-7 */ | 4312 | map_shift = map_bit & 0x7; /* i.e. 0-7 */ |
4323 | gk20a_dbg_info("access map addr:0x%x byte:0x%x bit:%d", | 4313 | gk20a_dbg_info("access map addr:0x%x byte:0x%x bit:%d", |
4324 | wl_addr_gk20a[w], map_byte, map_shift); | 4314 | whitelist[w], map_byte, map_shift); |
4325 | ((u8 *)data)[map_byte] |= 1 << map_shift; | 4315 | ((u8 *)data)[map_byte] |= 1 << map_shift; |
4326 | } | 4316 | } |
4327 | 4317 | ||
@@ -7315,6 +7305,22 @@ void gr_gk20a_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) | |||
7315 | } | 7305 | } |
7316 | } | 7306 | } |
7317 | 7307 | ||
7308 | static void gr_gk20a_get_access_map(struct gk20a *g, | ||
7309 | u32 **whitelist, int *num_entries) | ||
7310 | { | ||
7311 | static u32 wl_addr_gk20a[] = { | ||
7312 | /* this list must be sorted (low to high) */ | ||
7313 | 0x404468, /* gr_pri_mme_max_instructions */ | ||
7314 | 0x418800, /* gr_pri_gpcs_setup_debug */ | ||
7315 | 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ | ||
7316 | 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ | ||
7317 | 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ | ||
7318 | 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ | ||
7319 | }; | ||
7320 | |||
7321 | *whitelist = wl_addr_gk20a; | ||
7322 | *num_entries = ARRAY_SIZE(wl_addr_gk20a); | ||
7323 | } | ||
7318 | 7324 | ||
7319 | void gk20a_init_gr_ops(struct gpu_ops *gops) | 7325 | void gk20a_init_gr_ops(struct gpu_ops *gops) |
7320 | { | 7326 | { |
@@ -7368,4 +7374,5 @@ void gk20a_init_gr_ops(struct gpu_ops *gops) | |||
7368 | gops->gr.wait_empty = gr_gk20a_wait_idle; | 7374 | gops->gr.wait_empty = gr_gk20a_wait_idle; |
7369 | gops->gr.init_cyclestats = gr_gk20a_init_cyclestats; | 7375 | gops->gr.init_cyclestats = gr_gk20a_init_cyclestats; |
7370 | gops->gr.bpt_reg_info = gr_gk20a_bpt_reg_info; | 7376 | gops->gr.bpt_reg_info = gr_gk20a_bpt_reg_info; |
7377 | gops->gr.get_access_map = gr_gk20a_get_access_map; | ||
7371 | } | 7378 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 512c470d..81067f0a 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1127,6 +1127,23 @@ void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) | |||
1127 | } | 1127 | } |
1128 | } | 1128 | } |
1129 | 1129 | ||
1130 | static void gr_gm20b_get_access_map(struct gk20a *g, | ||
1131 | u32 **whitelist, int *num_entries) | ||
1132 | { | ||
1133 | static u32 wl_addr_gm20b[] = { | ||
1134 | /* this list must be sorted (low to high) */ | ||
1135 | 0x404468, /* gr_pri_mme_max_instructions */ | ||
1136 | 0x418800, /* gr_pri_gpcs_setup_debug */ | ||
1137 | 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ | ||
1138 | 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ | ||
1139 | 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ | ||
1140 | 0x419f78, /* gr_pri_gpcs_tpcs_sm_disp_ctrl */ | ||
1141 | }; | ||
1142 | |||
1143 | *whitelist = wl_addr_gm20b; | ||
1144 | *num_entries = ARRAY_SIZE(wl_addr_gm20b); | ||
1145 | } | ||
1146 | |||
1130 | void gm20b_init_gr(struct gpu_ops *gops) | 1147 | void gm20b_init_gr(struct gpu_ops *gops) |
1131 | { | 1148 | { |
1132 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | 1149 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; |
@@ -1184,4 +1201,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1184 | gops->gr.init_cyclestats = gr_gm20b_init_cyclestats; | 1201 | gops->gr.init_cyclestats = gr_gm20b_init_cyclestats; |
1185 | gops->gr.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs; | 1202 | gops->gr.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs; |
1186 | gops->gr.bpt_reg_info = gr_gm20b_bpt_reg_info; | 1203 | gops->gr.bpt_reg_info = gr_gm20b_bpt_reg_info; |
1204 | gops->gr.get_access_map = gr_gm20b_get_access_map; | ||
1187 | } | 1205 | } |