diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/vm.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vm.h | 2 |
4 files changed, 22 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c index e90437a3..19cc9fc5 100644 --- a/drivers/gpu/nvgpu/common/mm/vm.c +++ b/drivers/gpu/nvgpu/common/mm/vm.c | |||
@@ -60,6 +60,26 @@ int vm_aspace_id(struct vm_gk20a *vm) | |||
60 | return vm->as_share ? vm->as_share->id : -1; | 60 | return vm->as_share ? vm->as_share->id : -1; |
61 | } | 61 | } |
62 | 62 | ||
63 | /* | ||
64 | * Determine how many bits of the address space each last level PDE covers. For | ||
65 | * example, for gp10b, with a last level address bit PDE range of 28 to 21 the | ||
66 | * amount of memory each last level PDE addresses is 21 bits - i.e 2MB. | ||
67 | */ | ||
68 | int nvgpu_vm_pde_coverage_bit_count(struct vm_gk20a *vm) | ||
69 | { | ||
70 | int final_pde_level = 0; | ||
71 | |||
72 | /* | ||
73 | * Find the second to last level of the page table programming | ||
74 | * heirarchy: the last level is PTEs so we really want the level | ||
75 | * before that which is the last level of PDEs. | ||
76 | */ | ||
77 | while (vm->mmu_levels[final_pde_level + 2].update_entry) | ||
78 | final_pde_level++; | ||
79 | |||
80 | return vm->mmu_levels[final_pde_level].lo_bit[0]; | ||
81 | } | ||
82 | |||
63 | static void __nvgpu_vm_free_entries(struct vm_gk20a *vm, | 83 | static void __nvgpu_vm_free_entries(struct vm_gk20a *vm, |
64 | struct nvgpu_gmmu_pd *pd, | 84 | struct nvgpu_gmmu_pd *pd, |
65 | int level) | 85 | int level) |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 0b383a83..35c4d688 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -116,11 +116,6 @@ int gk20a_init_mm_setup_hw(struct gk20a *g) | |||
116 | return 0; | 116 | return 0; |
117 | } | 117 | } |
118 | 118 | ||
119 | int gk20a_mm_pde_coverage_bit_count(struct vm_gk20a *vm) | ||
120 | { | ||
121 | return vm->mmu_levels[0].lo_bit[0]; | ||
122 | } | ||
123 | |||
124 | /* for gk20a the "video memory" apertures here are misnomers. */ | 119 | /* for gk20a the "video memory" apertures here are misnomers. */ |
125 | static inline u32 big_valid_pde0_bits(struct gk20a *g, | 120 | static inline u32 big_valid_pde0_bits(struct gk20a *g, |
126 | struct nvgpu_gmmu_pd *pd, u64 addr) | 121 | struct nvgpu_gmmu_pd *pd, u64 addr) |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index ee0c2a07..14629611 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -172,7 +172,6 @@ int __gk20a_vm_bind_channel(struct vm_gk20a *vm, struct channel_gk20a *ch); | |||
172 | void pde_range_from_vaddr_range(struct vm_gk20a *vm, | 172 | void pde_range_from_vaddr_range(struct vm_gk20a *vm, |
173 | u64 addr_lo, u64 addr_hi, | 173 | u64 addr_lo, u64 addr_hi, |
174 | u32 *pde_lo, u32 *pde_hi); | 174 | u32 *pde_lo, u32 *pde_hi); |
175 | int gk20a_mm_pde_coverage_bit_count(struct vm_gk20a *vm); | ||
176 | u32 gk20a_mm_get_iommu_bit(struct gk20a *g); | 175 | u32 gk20a_mm_get_iommu_bit(struct gk20a *g); |
177 | 176 | ||
178 | const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, | 177 | const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h index 1689444c..e5d0e197 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h | |||
@@ -218,6 +218,8 @@ void nvgpu_vm_put(struct vm_gk20a *vm); | |||
218 | int vm_aspace_id(struct vm_gk20a *vm); | 218 | int vm_aspace_id(struct vm_gk20a *vm); |
219 | int nvgpu_big_pages_possible(struct vm_gk20a *vm, u64 base, u64 size); | 219 | int nvgpu_big_pages_possible(struct vm_gk20a *vm, u64 base, u64 size); |
220 | 220 | ||
221 | int nvgpu_vm_pde_coverage_bit_count(struct vm_gk20a *vm); | ||
222 | |||
221 | /* batching eliminates redundant cache flushes and invalidates */ | 223 | /* batching eliminates redundant cache flushes and invalidates */ |
222 | void nvgpu_vm_mapping_batch_start(struct vm_gk20a_mapping_batch *batch); | 224 | void nvgpu_vm_mapping_batch_start(struct vm_gk20a_mapping_batch *batch); |
223 | void nvgpu_vm_mapping_batch_finish( | 225 | void nvgpu_vm_mapping_batch_finish( |