diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/clk_arb.c (renamed from drivers/gpu/nvgpu/clk/clk_arb.c) | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_arb_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/clk_arb.h (renamed from drivers/gpu/nvgpu/clk/clk_arb.h) | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/perf.c | 1 |
7 files changed, 33 insertions, 24 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index e689aa7f..1217fead 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu | |||
@@ -221,7 +221,7 @@ nvgpu-y += \ | |||
221 | clk/clk_domain.o \ | 221 | clk/clk_domain.o \ |
222 | clk/clk_prog.o \ | 222 | clk/clk_prog.o \ |
223 | clk/clk_vf_point.o \ | 223 | clk/clk_vf_point.o \ |
224 | clk/clk_arb.o \ | 224 | common/linux/clk_arb.o \ |
225 | clk/clk_freq_controller.o \ | 225 | clk/clk_freq_controller.o \ |
226 | perf/vfe_var.o \ | 226 | perf/vfe_var.o \ |
227 | perf/vfe_equ.o \ | 227 | perf/vfe_equ.o \ |
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/common/linux/clk_arb.c index 937d47db..ff26f567 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/common/linux/clk_arb.c | |||
@@ -41,9 +41,13 @@ | |||
41 | #include <nvgpu/log.h> | 41 | #include <nvgpu/log.h> |
42 | #include <nvgpu/barrier.h> | 42 | #include <nvgpu/barrier.h> |
43 | #include <nvgpu/cond.h> | 43 | #include <nvgpu/cond.h> |
44 | #include <nvgpu/clk_arb.h> | ||
44 | 45 | ||
45 | #include "gk20a/gk20a.h" | 46 | #include "gk20a/gk20a.h" |
46 | #include "clk/clk_arb.h" | 47 | #include "clk/clk.h" |
48 | #include "pstate/pstate.h" | ||
49 | #include "lpwr/lpwr.h" | ||
50 | #include "volt/volt.h" | ||
47 | 51 | ||
48 | #ifdef CONFIG_DEBUG_FS | 52 | #ifdef CONFIG_DEBUG_FS |
49 | #include "common/linux/os_linux.h" | 53 | #include "common/linux/os_linux.h" |
@@ -499,7 +503,8 @@ void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g) | |||
499 | nvgpu_kfree(g, arb->mclk_f_points); | 503 | nvgpu_kfree(g, arb->mclk_f_points); |
500 | 504 | ||
501 | for (index = 0; index < 2; index++) { | 505 | for (index = 0; index < 2; index++) { |
502 | nvgpu_kfree(g, arb->vf_table_pool[index].gpc2clk_points); | 506 | nvgpu_kfree(g, |
507 | arb->vf_table_pool[index].gpc2clk_points); | ||
503 | nvgpu_kfree(g, arb->vf_table_pool[index].mclk_points); | 508 | nvgpu_kfree(g, arb->vf_table_pool[index].mclk_points); |
504 | } | 509 | } |
505 | nvgpu_mutex_destroy(&g->clk_arb->pstate_lock); | 510 | nvgpu_mutex_destroy(&g->clk_arb->pstate_lock); |
@@ -590,7 +595,8 @@ int nvgpu_clk_arb_init_session(struct gk20a *g, | |||
590 | session->zombie = false; | 595 | session->zombie = false; |
591 | session->target_pool[0].pstate = CTRL_PERF_PSTATE_P8; | 596 | session->target_pool[0].pstate = CTRL_PERF_PSTATE_P8; |
592 | /* make sure that the initialization of the pool is visible | 597 | /* make sure that the initialization of the pool is visible |
593 | * before the update */ | 598 | * before the update |
599 | */ | ||
594 | nvgpu_smp_wmb(); | 600 | nvgpu_smp_wmb(); |
595 | session->target = &session->target_pool[0]; | 601 | session->target = &session->target_pool[0]; |
596 | 602 | ||
@@ -893,6 +899,7 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
893 | for (i = 0, j = 0; i < table->gpc2clk_num_points; i++) { | 899 | for (i = 0, j = 0; i < table->gpc2clk_num_points; i++) { |
894 | 900 | ||
895 | u16 alt_gpc2clk = table->gpc2clk_points[i].gpc_mhz; | 901 | u16 alt_gpc2clk = table->gpc2clk_points[i].gpc_mhz; |
902 | |||
896 | gpc2clk_voltuv = gpc2clk_voltuv_sram = 0; | 903 | gpc2clk_voltuv = gpc2clk_voltuv_sram = 0; |
897 | 904 | ||
898 | /* Check sysclk */ | 905 | /* Check sysclk */ |
@@ -918,9 +925,9 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
918 | 925 | ||
919 | alt_gpc2clk = alt_gpc2clk < | 926 | alt_gpc2clk = alt_gpc2clk < |
920 | table->gpc2clk_points[j]. | 927 | table->gpc2clk_points[j]. |
921 | gpc_mhz ? | 928 | gpc_mhz ? |
922 | table->gpc2clk_points[j]. | 929 | table->gpc2clk_points[j]. |
923 | gpc_mhz: | 930 | gpc_mhz : |
924 | alt_gpc2clk; | 931 | alt_gpc2clk; |
925 | break; | 932 | break; |
926 | } | 933 | } |
@@ -954,9 +961,9 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
954 | 961 | ||
955 | alt_gpc2clk = alt_gpc2clk < | 962 | alt_gpc2clk = alt_gpc2clk < |
956 | table->gpc2clk_points[j]. | 963 | table->gpc2clk_points[j]. |
957 | gpc_mhz ? | 964 | gpc_mhz ? |
958 | table->gpc2clk_points[j]. | 965 | table->gpc2clk_points[j]. |
959 | gpc_mhz: | 966 | gpc_mhz : |
960 | alt_gpc2clk; | 967 | alt_gpc2clk; |
961 | break; | 968 | break; |
962 | } | 969 | } |
@@ -1010,6 +1017,7 @@ exit_vf_table: | |||
1010 | void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g) | 1017 | void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g) |
1011 | { | 1018 | { |
1012 | struct nvgpu_clk_arb *arb = g->clk_arb; | 1019 | struct nvgpu_clk_arb *arb = g->clk_arb; |
1020 | |||
1013 | if (arb->vf_table_work_queue) | 1021 | if (arb->vf_table_work_queue) |
1014 | queue_work(arb->vf_table_work_queue, &arb->vf_table_fn_work); | 1022 | queue_work(arb->vf_table_work_queue, &arb->vf_table_fn_work); |
1015 | } | 1023 | } |
@@ -1138,7 +1146,7 @@ static void nvgpu_clk_arb_run_arbiter_cb(struct work_struct *work) | |||
1138 | if (gpc2clk_target > arb->gpc2clk_max) | 1146 | if (gpc2clk_target > arb->gpc2clk_max) |
1139 | gpc2clk_target = arb->gpc2clk_max; | 1147 | gpc2clk_target = arb->gpc2clk_max; |
1140 | 1148 | ||
1141 | mclk_target = (mclk_target > 0) ? mclk_target: | 1149 | mclk_target = (mclk_target > 0) ? mclk_target : |
1142 | arb->mclk_default_mhz; | 1150 | arb->mclk_default_mhz; |
1143 | 1151 | ||
1144 | if (mclk_target < arb->mclk_min) | 1152 | if (mclk_target < arb->mclk_min) |
@@ -1438,7 +1446,8 @@ static u32 nvgpu_clk_arb_notify(struct nvgpu_clk_dev *dev, | |||
1438 | 1446 | ||
1439 | poll_mask |= (POLLIN | POLLPRI); | 1447 | poll_mask |= (POLLIN | POLLPRI); |
1440 | /* On next run do not report global alarms that were already | 1448 | /* On next run do not report global alarms that were already |
1441 | * reported, but report SHUTDOWN always */ | 1449 | * reported, but report SHUTDOWN always |
1450 | */ | ||
1442 | dev->alarms_reported = new_alarms_reported & ~LOCAL_ALARM_MASK & | 1451 | dev->alarms_reported = new_alarms_reported & ~LOCAL_ALARM_MASK & |
1443 | ~EVENT(ALARM_GPU_LOST); | 1452 | ~EVENT(ALARM_GPU_LOST); |
1444 | } | 1453 | } |
@@ -1753,15 +1762,15 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | |||
1753 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | 1762 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, |
1754 | u32 api_domain, u16 *freq_mhz) | 1763 | u32 api_domain, u16 *freq_mhz) |
1755 | { | 1764 | { |
1756 | switch(api_domain) { | 1765 | switch (api_domain) { |
1757 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1766 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1758 | *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) / | 1767 | *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) / |
1759 | 1000000ULL; | 1768 | 1000000ULL; |
1760 | return 0; | 1769 | return 0; |
1761 | 1770 | ||
1762 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1771 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1763 | *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_GPC2CLK) / | 1772 | *freq_mhz = g->ops.clk.measure_freq(g, |
1764 | 2000000ULL; | 1773 | CTRL_CLK_DOMAIN_GPC2CLK) / 2000000ULL; |
1765 | return 0; | 1774 | return 0; |
1766 | 1775 | ||
1767 | default: | 1776 | default: |
@@ -1774,7 +1783,7 @@ int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | |||
1774 | { | 1783 | { |
1775 | int ret; | 1784 | int ret; |
1776 | 1785 | ||
1777 | switch(api_domain) { | 1786 | switch (api_domain) { |
1778 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1787 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1779 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | 1788 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, |
1780 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); | 1789 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); |
@@ -1812,7 +1821,7 @@ bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain) | |||
1812 | { | 1821 | { |
1813 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | 1822 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); |
1814 | 1823 | ||
1815 | switch(api_domain) { | 1824 | switch (api_domain) { |
1816 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1825 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1817 | return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0); | 1826 | return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0); |
1818 | 1827 | ||
@@ -1903,7 +1912,7 @@ recalculate_vf_point: | |||
1903 | 1912 | ||
1904 | if ((table->gpc2clk_points[index].gpc_mhz >= | 1913 | if ((table->gpc2clk_points[index].gpc_mhz >= |
1905 | gpc2clk_target) && | 1914 | gpc2clk_target) && |
1906 | (pstate != VF_POINT_INVALID_PSTATE)){ | 1915 | (pstate != VF_POINT_INVALID_PSTATE)) { |
1907 | gpc2clk_target = | 1916 | gpc2clk_target = |
1908 | table->gpc2clk_points[index].gpc_mhz; | 1917 | table->gpc2clk_points[index].gpc_mhz; |
1909 | *sys2clk = | 1918 | *sys2clk = |
@@ -1972,7 +1981,8 @@ find_exit: | |||
1972 | } | 1981 | } |
1973 | 1982 | ||
1974 | /* This function is inherently unsafe to call while arbiter is running | 1983 | /* This function is inherently unsafe to call while arbiter is running |
1975 | * arbiter must be blocked before calling this function */ | 1984 | * arbiter must be blocked before calling this function |
1985 | */ | ||
1976 | int nvgpu_clk_arb_get_current_pstate(struct gk20a *g) | 1986 | int nvgpu_clk_arb_get_current_pstate(struct gk20a *g) |
1977 | { | 1987 | { |
1978 | return NV_ACCESS_ONCE(g->clk_arb->actual->pstate); | 1988 | return NV_ACCESS_ONCE(g->clk_arb->actual->pstate); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4f3b34b8..13d534c4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -58,6 +58,7 @@ struct nvgpu_warpstate; | |||
58 | #include <nvgpu/atomic.h> | 58 | #include <nvgpu/atomic.h> |
59 | #include <nvgpu/barrier.h> | 59 | #include <nvgpu/barrier.h> |
60 | #include <nvgpu/rwsem.h> | 60 | #include <nvgpu/rwsem.h> |
61 | #include <nvgpu/clk_arb.h> | ||
61 | 62 | ||
62 | #include "clk_gk20a.h" | 63 | #include "clk_gk20a.h" |
63 | #include "ce2_gk20a.h" | 64 | #include "ce2_gk20a.h" |
@@ -70,7 +71,6 @@ struct nvgpu_warpstate; | |||
70 | #include "therm_gk20a.h" | 71 | #include "therm_gk20a.h" |
71 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 72 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC |
72 | #include "clk/clk.h" | 73 | #include "clk/clk.h" |
73 | #include "clk/clk_arb.h" | ||
74 | #include "perf/perf.h" | 74 | #include "perf/perf.h" |
75 | #include "pmgr/pmgr.h" | 75 | #include "pmgr/pmgr.h" |
76 | #include "therm/thrm.h" | 76 | #include "therm/thrm.h" |
diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c index 00f5a61b..ae6cd327 100644 --- a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c | |||
@@ -22,7 +22,6 @@ | |||
22 | 22 | ||
23 | #include "gk20a/gk20a.h" | 23 | #include "gk20a/gk20a.h" |
24 | 24 | ||
25 | #include "clk/clk_arb.h" | ||
26 | #include "clk_arb_gp106.h" | 25 | #include "clk_arb_gp106.h" |
27 | 26 | ||
28 | u32 gp106_get_arbiter_clk_domains(struct gk20a *g) | 27 | u32 gp106_get_arbiter_clk_domains(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index 4b941433..b8a1ba3d 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include "common/linux/os_linux.h" | 32 | #include "common/linux/os_linux.h" |
33 | 33 | ||
34 | #include "clk_gp106.h" | 34 | #include "clk_gp106.h" |
35 | #include "clk/clk_arb.h" | ||
36 | 35 | ||
37 | #include "gp106/mclk_gp106.h" | 36 | #include "gp106/mclk_gp106.h" |
38 | 37 | ||
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h index 8545e01b..09f0b0d3 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.h +++ b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h | |||
@@ -20,8 +20,10 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #ifndef _CLK_ARB_H_ | 23 | #ifndef __NVGPU_CLK_ARB_H__ |
24 | #define _CLK_ARB_H_ | 24 | #define __NVGPU_CLK_ARB_H__ |
25 | |||
26 | #include <nvgpu/types.h> | ||
25 | 27 | ||
26 | struct gk20a; | 28 | struct gk20a; |
27 | struct nvgpu_clk_session; | 29 | struct nvgpu_clk_session; |
@@ -76,5 +78,5 @@ int nvgpu_clk_arb_get_current_pstate(struct gk20a *g); | |||
76 | void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock); | 78 | void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock); |
77 | 79 | ||
78 | void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm); | 80 | void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm); |
79 | #endif /* _CLK_ARB_H_ */ | 81 | #endif /* __NVGPU_CLK_ARB_H__ */ |
80 | 82 | ||
diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c index bf5140d3..7dd435e5 100644 --- a/drivers/gpu/nvgpu/perf/perf.c +++ b/drivers/gpu/nvgpu/perf/perf.c | |||
@@ -25,7 +25,6 @@ | |||
25 | 25 | ||
26 | #include "gk20a/gk20a.h" | 26 | #include "gk20a/gk20a.h" |
27 | #include "perf.h" | 27 | #include "perf.h" |
28 | #include "clk/clk_arb.h" | ||
29 | 28 | ||
30 | struct perfrpc_pmucmdhandler_params { | 29 | struct perfrpc_pmucmdhandler_params { |
31 | struct nv_pmu_perf_rpc *prpccall; | 30 | struct nv_pmu_perf_rpc *prpccall; |