diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_arb.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 10 |
2 files changed, 4 insertions, 24 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index 062e4e2b..c00a79ec 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c | |||
@@ -1628,12 +1628,10 @@ int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session, | |||
1628 | 1628 | ||
1629 | switch (api_domain) { | 1629 | switch (api_domain) { |
1630 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1630 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1631 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1632 | dev->mclk_target_mhz = target_mhz; | 1631 | dev->mclk_target_mhz = target_mhz; |
1633 | break; | 1632 | break; |
1634 | 1633 | ||
1635 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1634 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1636 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1637 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; | 1635 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; |
1638 | break; | 1636 | break; |
1639 | 1637 | ||
@@ -1659,12 +1657,10 @@ int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session, | |||
1659 | 1657 | ||
1660 | switch (api_domain) { | 1658 | switch (api_domain) { |
1661 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1659 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1662 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1663 | *freq_mhz = target->mclk; | 1660 | *freq_mhz = target->mclk; |
1664 | break; | 1661 | break; |
1665 | 1662 | ||
1666 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1663 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1667 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1668 | *freq_mhz = target->gpc2clk / 2ULL; | 1664 | *freq_mhz = target->gpc2clk / 2ULL; |
1669 | break; | 1665 | break; |
1670 | 1666 | ||
@@ -1690,12 +1686,10 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | |||
1690 | 1686 | ||
1691 | switch (api_domain) { | 1687 | switch (api_domain) { |
1692 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1688 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1693 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1694 | *freq_mhz = actual->mclk; | 1689 | *freq_mhz = actual->mclk; |
1695 | break; | 1690 | break; |
1696 | 1691 | ||
1697 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1692 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1698 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1699 | *freq_mhz = actual->gpc2clk / 2ULL; | 1693 | *freq_mhz = actual->gpc2clk / 2ULL; |
1700 | break; | 1694 | break; |
1701 | 1695 | ||
@@ -1712,12 +1706,10 @@ int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | |||
1712 | { | 1706 | { |
1713 | switch(api_domain) { | 1707 | switch(api_domain) { |
1714 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1708 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1715 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1716 | *freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_MCLK); | 1709 | *freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_MCLK); |
1717 | return 0; | 1710 | return 0; |
1718 | 1711 | ||
1719 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1712 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1720 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1721 | *freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPC2CLK) / 2; | 1713 | *freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPC2CLK) / 2; |
1722 | return 0; | 1714 | return 0; |
1723 | 1715 | ||
@@ -1733,13 +1725,11 @@ int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | |||
1733 | 1725 | ||
1734 | switch(api_domain) { | 1726 | switch(api_domain) { |
1735 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1727 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1736 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1737 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | 1728 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, |
1738 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); | 1729 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); |
1739 | return ret; | 1730 | return ret; |
1740 | 1731 | ||
1741 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1732 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1742 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1743 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | 1733 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, |
1744 | CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); | 1734 | CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); |
1745 | if (!ret) { | 1735 | if (!ret) { |
@@ -1759,10 +1749,10 @@ u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) | |||
1759 | u32 api_domains = 0; | 1749 | u32 api_domains = 0; |
1760 | 1750 | ||
1761 | if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) | 1751 | if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) |
1762 | api_domains |= NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS; | 1752 | api_domains |= BIT(NVGPU_GPU_CLK_DOMAIN_GPCCLK); |
1763 | 1753 | ||
1764 | if (clk_domains & CTRL_CLK_DOMAIN_MCLK) | 1754 | if (clk_domains & CTRL_CLK_DOMAIN_MCLK) |
1765 | api_domains |= NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS; | 1755 | api_domains |= BIT(NVGPU_GPU_CLK_DOMAIN_MCLK); |
1766 | 1756 | ||
1767 | return api_domains; | 1757 | return api_domains; |
1768 | } | 1758 | } |
@@ -1773,11 +1763,9 @@ bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain) | |||
1773 | 1763 | ||
1774 | switch(api_domain) { | 1764 | switch(api_domain) { |
1775 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1765 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1776 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1777 | return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0); | 1766 | return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0); |
1778 | 1767 | ||
1779 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1768 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1780 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1781 | return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0); | 1769 | return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0); |
1782 | 1770 | ||
1783 | default: | 1771 | default: |
@@ -1793,7 +1781,6 @@ int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | |||
1793 | 1781 | ||
1794 | switch (api_domain) { | 1782 | switch (api_domain) { |
1795 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1783 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1796 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1797 | err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK, | 1784 | err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK, |
1798 | max_points, fpoints); | 1785 | max_points, fpoints); |
1799 | if (err || !fpoints) | 1786 | if (err || !fpoints) |
@@ -1802,7 +1789,6 @@ int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | |||
1802 | fpoints[i] /= 2; | 1789 | fpoints[i] /= 2; |
1803 | return 0; | 1790 | return 0; |
1804 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1791 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1805 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1806 | return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK, | 1792 | return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK, |
1807 | max_points, fpoints); | 1793 | max_points, fpoints); |
1808 | default: | 1794 | default: |
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 351be55e..e2a97caa 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -987,10 +987,7 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g, | |||
987 | return -EFAULT; | 987 | return -EFAULT; |
988 | } else { | 988 | } else { |
989 | bit = ffs(clk_domains) - 1; | 989 | bit = ffs(clk_domains) - 1; |
990 | if (bit <= NVGPU_GPU_CLK_DOMAIN_GPCCLK) | 990 | clk_range.clk_domain = bit; |
991 | clk_range.clk_domain = bit; | ||
992 | else | ||
993 | clk_range.clk_domain = BIT(bit); | ||
994 | clk_domains &= ~BIT(bit); | 991 | clk_domains &= ~BIT(bit); |
995 | } | 992 | } |
996 | 993 | ||
@@ -1139,10 +1136,7 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1139 | return -EFAULT; | 1136 | return -EFAULT; |
1140 | } else { | 1137 | } else { |
1141 | bit = ffs(clk_domains) - 1; | 1138 | bit = ffs(clk_domains) - 1; |
1142 | if (bit <= NVGPU_GPU_CLK_DOMAIN_GPCCLK) | 1139 | clk_info.clk_domain = bit; |
1143 | clk_info.clk_domain = bit; | ||
1144 | else | ||
1145 | clk_info.clk_domain = BIT(bit); | ||
1146 | clk_domains &= ~BIT(bit); | 1140 | clk_domains &= ~BIT(bit); |
1147 | clk_info.clk_type = args->clk_type; | 1141 | clk_info.clk_type = args->clk_type; |
1148 | } | 1142 | } |