diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 63 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 3 |
7 files changed, 74 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index 6b384c89..11f1169b 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -362,6 +362,11 @@ int gk20a_fecs_trace_poll(struct gk20a *g) | |||
362 | /* Ensure all FECS writes have made it to SYSMEM */ | 362 | /* Ensure all FECS writes have made it to SYSMEM */ |
363 | g->ops.mm.fb_flush(g); | 363 | g->ops.mm.fb_flush(g); |
364 | 364 | ||
365 | if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL)) { | ||
366 | /* Bits 30:0 of MAILBOX1 represents actual read pointer value */ | ||
367 | read = read & (~(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT))); | ||
368 | } | ||
369 | |||
365 | while (read != write) { | 370 | while (read != write) { |
366 | cnt = gk20a_fecs_trace_ring_read(g, read); | 371 | cnt = gk20a_fecs_trace_ring_read(g, read); |
367 | if (cnt <= 0) | 372 | if (cnt <= 0) |
@@ -371,6 +376,15 @@ int gk20a_fecs_trace_poll(struct gk20a *g) | |||
371 | read = (read + 1) & (GK20A_FECS_TRACE_NUM_RECORDS - 1); | 376 | read = (read + 1) & (GK20A_FECS_TRACE_NUM_RECORDS - 1); |
372 | } | 377 | } |
373 | 378 | ||
379 | if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL)) { | ||
380 | /* | ||
381 | * In the next step, read pointer is going to be updated. | ||
382 | * So, MSB of read pointer should be set back to 1. This will | ||
383 | * keep FECS trace enabled. | ||
384 | */ | ||
385 | read = read | (BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT)); | ||
386 | } | ||
387 | |||
374 | /* ensure FECS records has been updated before incrementing read index */ | 388 | /* ensure FECS records has been updated before incrementing read index */ |
375 | nvgpu_wmb(); | 389 | nvgpu_wmb(); |
376 | gk20a_fecs_trace_set_read_index(g, read); | 390 | gk20a_fecs_trace_set_read_index(g, read); |
@@ -606,8 +620,30 @@ int gk20a_fecs_trace_enable(struct gk20a *g) | |||
606 | if (g->ops.fecs_trace.flush) | 620 | if (g->ops.fecs_trace.flush) |
607 | g->ops.fecs_trace.flush(g); | 621 | g->ops.fecs_trace.flush(g); |
608 | write = gk20a_fecs_trace_get_write_index(g); | 622 | write = gk20a_fecs_trace_get_write_index(g); |
623 | |||
624 | if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL)) { | ||
625 | /* | ||
626 | * For enabling FECS trace support, MAILBOX1's MSB | ||
627 | * (Bit 31:31) should be set to 1. Bits 30:0 represents | ||
628 | * actual pointer value. | ||
629 | */ | ||
630 | write = write | | ||
631 | (BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT)); | ||
632 | } | ||
609 | gk20a_fecs_trace_set_read_index(g, write); | 633 | gk20a_fecs_trace_set_read_index(g, write); |
610 | 634 | ||
635 | /* | ||
636 | * FECS ucode does a priv holdoff around the assertion of | ||
637 | * context reset. So, pri transactions (e.g. mailbox1 register | ||
638 | * write) might fail due to this. Hence, do write with ack | ||
639 | * i.e. write and read it back to make sure write happened for | ||
640 | * mailbox1. | ||
641 | */ | ||
642 | while (gk20a_fecs_trace_get_read_index(g) != write) { | ||
643 | nvgpu_log(g, gpu_dbg_ctxsw, "mailbox1 update failed"); | ||
644 | gk20a_fecs_trace_set_read_index(g, write); | ||
645 | } | ||
646 | |||
611 | err = nvgpu_thread_create(&trace->poll_task, g, | 647 | err = nvgpu_thread_create(&trace->poll_task, g, |
612 | gk20a_fecs_trace_periodic_polling, __func__); | 648 | gk20a_fecs_trace_periodic_polling, __func__); |
613 | if (err) { | 649 | if (err) { |
@@ -622,10 +658,35 @@ int gk20a_fecs_trace_enable(struct gk20a *g) | |||
622 | int gk20a_fecs_trace_disable(struct gk20a *g) | 658 | int gk20a_fecs_trace_disable(struct gk20a *g) |
623 | { | 659 | { |
624 | struct gk20a_fecs_trace *trace = g->fecs_trace; | 660 | struct gk20a_fecs_trace *trace = g->fecs_trace; |
661 | int read = 0; | ||
625 | 662 | ||
626 | if (nvgpu_thread_is_running(&trace->poll_task)) | 663 | if (nvgpu_thread_is_running(&trace->poll_task)) |
627 | nvgpu_thread_stop(&trace->poll_task); | 664 | nvgpu_thread_stop(&trace->poll_task); |
628 | 665 | ||
666 | if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL)) { | ||
667 | /* | ||
668 | * For disabling FECS trace support, MAILBOX1's MSB | ||
669 | * (Bit 31:31) should be set to 0. | ||
670 | */ | ||
671 | read = gk20a_fecs_trace_get_read_index(g) & | ||
672 | (~(BIT32(NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT))); | ||
673 | |||
674 | gk20a_fecs_trace_set_read_index(g, read); | ||
675 | |||
676 | /* | ||
677 | * FECS ucode does a priv holdoff around the assertion | ||
678 | * of context reset. So, pri transactions (e.g. | ||
679 | * mailbox1 register write) might fail due to this. | ||
680 | * Hence, do write with ack i.e. write and read it back | ||
681 | * to make sure write happened for mailbox1. | ||
682 | */ | ||
683 | while (gk20a_fecs_trace_get_read_index(g) != read) { | ||
684 | nvgpu_log(g, gpu_dbg_ctxsw, | ||
685 | "mailbox1 update failed"); | ||
686 | gk20a_fecs_trace_set_read_index(g, read); | ||
687 | } | ||
688 | } | ||
689 | |||
629 | return -EPERM; | 690 | return -EPERM; |
630 | } | 691 | } |
631 | 692 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 113f6520..c978f9aa 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Graphics | 2 | * GM20B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -752,6 +752,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
752 | 752 | ||
753 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 753 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
754 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 754 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
755 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); | ||
755 | 756 | ||
756 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 757 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
757 | if (gops->fuse.check_priv_security(g)) { | 758 | if (gops->fuse.check_priv_security(g)) { |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 0723fa0e..561d24d8 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Tegra HAL interface | 2 | * GP10B Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -782,6 +782,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
782 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 782 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
783 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 783 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
784 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); | 784 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); |
785 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); | ||
785 | 786 | ||
786 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 787 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
787 | if (gops->fuse.check_priv_security(g)) { | 788 | if (gops->fuse.check_priv_security(g)) { |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 31ca997f..9a3d2241 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 Tegra HAL interface | 2 | * GV100 Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -1039,6 +1039,7 @@ int gv100_init_hal(struct gk20a *g) | |||
1039 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | 1039 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
1040 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); | 1040 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); |
1041 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); | 1041 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); |
1042 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); | ||
1042 | 1043 | ||
1043 | /* for now */ | 1044 | /* for now */ |
1044 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 1045 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ea9b41d8..84469fa0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B Tegra HAL interface | 2 | * GV11B Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -949,6 +949,7 @@ int gv11b_init_hal(struct gk20a *g) | |||
949 | 949 | ||
950 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | 950 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
951 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); | 951 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); |
952 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true); | ||
952 | 953 | ||
953 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); | 954 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); |
954 | 955 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h b/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h index 2da6b837..033e020a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h +++ b/drivers/gpu/nvgpu/include/nvgpu/ctxsw_trace.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -48,6 +48,7 @@ struct channel_gk20a; | |||
48 | ((p)->tag_bits[(n) / 64] & (1 << ((n) & 63))) | 48 | ((p)->tag_bits[(n) / 64] & (1 << ((n) & 63))) |
49 | 49 | ||
50 | #define NVGPU_GPU_CTXSW_FILTER_SIZE (NVGPU_GPU_CTXSW_TAG_LAST + 1) | 50 | #define NVGPU_GPU_CTXSW_FILTER_SIZE (NVGPU_GPU_CTXSW_TAG_LAST + 1) |
51 | #define NVGPU_FECS_TRACE_FEATURE_CONTROL_BIT 31 | ||
51 | 52 | ||
52 | struct nvgpu_gpu_ctxsw_trace_filter { | 53 | struct nvgpu_gpu_ctxsw_trace_filter { |
53 | u64 tag_bits[(NVGPU_GPU_CTXSW_FILTER_SIZE + 63) / 64]; | 54 | u64 tag_bits[(NVGPU_GPU_CTXSW_FILTER_SIZE + 63) / 64]; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 79bffcac..76f0f2bd 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -37,6 +37,7 @@ struct gk20a; | |||
37 | #define NVGPU_FECS_TRACE_VA 4 | 37 | #define NVGPU_FECS_TRACE_VA 4 |
38 | #define NVGPU_CAN_RAILGATE 5 | 38 | #define NVGPU_CAN_RAILGATE 5 |
39 | #define NVGPU_KERNEL_IS_DYING 6 | 39 | #define NVGPU_KERNEL_IS_DYING 6 |
40 | #define NVGPU_FECS_TRACE_FEATURE_CONTROL 7 | ||
40 | 41 | ||
41 | /* | 42 | /* |
42 | * ECC flags | 43 | * ECC flags |