diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 19 |
3 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 58558159..4878fdd6 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -408,6 +408,7 @@ struct gpu_ops { | |||
408 | void (*resume_single_sm)(struct gk20a *g, | 408 | void (*resume_single_sm)(struct gk20a *g, |
409 | u32 gpc, u32 tpc, u32 sm); | 409 | u32 gpc, u32 tpc, u32 sm); |
410 | void (*resume_all_sms)(struct gk20a *g); | 410 | void (*resume_all_sms)(struct gk20a *g); |
411 | void (*disable_rd_coalesce)(struct gk20a *g); | ||
411 | } gr; | 412 | } gr; |
412 | struct { | 413 | struct { |
413 | void (*init_hw)(struct gk20a *g); | 414 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 608b011a..cd1d31a5 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4521,6 +4521,9 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4521 | if (g->ops.fb.init_cbc) | 4521 | if (g->ops.fb.init_cbc) |
4522 | g->ops.fb.init_cbc(g, gr); | 4522 | g->ops.fb.init_cbc(g, gr); |
4523 | 4523 | ||
4524 | if (g->ops.gr.disable_rd_coalesce) | ||
4525 | g->ops.gr.disable_rd_coalesce(g); | ||
4526 | |||
4524 | /* load ctx init */ | 4527 | /* load ctx init */ |
4525 | for (i = 0; i < sw_ctx_load->count; i++) | 4528 | for (i = 0; i < sw_ctx_load->count; i++) |
4526 | gk20a_writel(g, sw_ctx_load->l[i].addr, | 4529 | gk20a_writel(g, sw_ctx_load->l[i].addr, |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 87cf3f01..56ebc8ca 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1542,6 +1542,24 @@ static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
1542 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); | 1542 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, 0); |
1543 | } | 1543 | } |
1544 | 1544 | ||
1545 | /* | ||
1546 | * Disable both surface and LG coalesce. | ||
1547 | */ | ||
1548 | void gm20a_gr_disable_rd_coalesce(struct gk20a *g) | ||
1549 | { | ||
1550 | u32 dbg2_reg; | ||
1551 | |||
1552 | dbg2_reg = gk20a_readl(g, gr_gpcs_tpcs_tex_m_dbg2_r()); | ||
1553 | dbg2_reg = set_field(dbg2_reg, | ||
1554 | gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_m(), | ||
1555 | gr_gpcs_tpcs_tex_m_dbg2_lg_rd_coalesce_en_f(0)); | ||
1556 | dbg2_reg = set_field(dbg2_reg, | ||
1557 | gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_m(), | ||
1558 | gr_gpcs_tpcs_tex_m_dbg2_su_rd_coalesce_en_f(0)); | ||
1559 | |||
1560 | gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg); | ||
1561 | } | ||
1562 | |||
1545 | void gm20b_init_gr(struct gk20a *g) | 1563 | void gm20b_init_gr(struct gk20a *g) |
1546 | { | 1564 | { |
1547 | struct gpu_ops *gops = &g->ops; | 1565 | struct gpu_ops *gops = &g->ops; |
@@ -1657,4 +1675,5 @@ void gm20b_init_gr(struct gk20a *g) | |||
1657 | gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww; | 1675 | gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww; |
1658 | gops->gr.init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf; | 1676 | gops->gr.init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf; |
1659 | gops->gr.get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs; | 1677 | gops->gr.get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs; |
1678 | gops->gr.disable_rd_coalesce = gm20a_gr_disable_rd_coalesce; | ||
1660 | } | 1679 | } |