diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 25 |
1 files changed, 7 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 9c3c8b81..f2397108 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -22,19 +22,13 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <linux/delay.h> | ||
26 | #include <linux/version.h> | ||
27 | #include <linux/vmalloc.h> | ||
28 | #include <linux/tegra_gpu_t19x.h> | ||
29 | |||
30 | #include <soc/tegra/fuse.h> | ||
31 | |||
32 | #include <nvgpu/timers.h> | 25 | #include <nvgpu/timers.h> |
33 | #include <nvgpu/gmmu.h> | 26 | #include <nvgpu/gmmu.h> |
34 | #include <nvgpu/dma.h> | 27 | #include <nvgpu/dma.h> |
35 | #include <nvgpu/log.h> | 28 | #include <nvgpu/log.h> |
36 | #include <nvgpu/debug.h> | 29 | #include <nvgpu/debug.h> |
37 | #include <nvgpu/enabled.h> | 30 | #include <nvgpu/enabled.h> |
31 | #include <nvgpu/fuse.h> | ||
38 | 32 | ||
39 | #include "gk20a/gk20a.h" | 33 | #include "gk20a/gk20a.h" |
40 | #include "gk20a/gr_gk20a.h" | 34 | #include "gk20a/gr_gk20a.h" |
@@ -1644,7 +1638,7 @@ int gr_gv11b_wait_empty(struct gk20a *g, unsigned long duration_ms, | |||
1644 | return 0; | 1638 | return 0; |
1645 | } | 1639 | } |
1646 | 1640 | ||
1647 | usleep_range(delay, delay * 2); | 1641 | nvgpu_usleep_range(delay, delay * 2); |
1648 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 1642 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
1649 | 1643 | ||
1650 | } while (!nvgpu_timeout_expired(&timeout)); | 1644 | } while (!nvgpu_timeout_expired(&timeout)); |
@@ -1686,20 +1680,15 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | |||
1686 | 1680 | ||
1687 | void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1681 | void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1688 | { | 1682 | { |
1689 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | 1683 | nvgpu_tegra_fuse_write_bypass(g, 0x1); |
1690 | tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); | 1684 | nvgpu_tegra_fuse_write_access_sw(g, 0x0); |
1691 | tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); | ||
1692 | #else | ||
1693 | tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); | ||
1694 | tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); | ||
1695 | #endif | ||
1696 | 1685 | ||
1697 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) | 1686 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) |
1698 | tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1687 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2); |
1699 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) | 1688 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) |
1700 | tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1689 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1); |
1701 | else | 1690 | else |
1702 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1691 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); |
1703 | } | 1692 | } |
1704 | 1693 | ||
1705 | void gr_gv11b_get_access_map(struct gk20a *g, | 1694 | void gr_gv11b_get_access_map(struct gk20a *g, |