diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/regops_gv100.c | 463 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/regops_gv100.h | 42 |
4 files changed, 528 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index c6958bec..0909a010 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -30,6 +30,7 @@ nvgpu-y += \ | |||
30 | $(nvgpu-t19x)/gv100/bios_gv100.o \ | 30 | $(nvgpu-t19x)/gv100/bios_gv100.o \ |
31 | $(nvgpu-t19x)/gv100/fifo_gv100.o \ | 31 | $(nvgpu-t19x)/gv100/fifo_gv100.o \ |
32 | $(nvgpu-t19x)/gv100/gr_gv100.o \ | 32 | $(nvgpu-t19x)/gv100/gr_gv100.o \ |
33 | $(nvgpu-t19x)/gv100/regops_gv100.o \ | ||
33 | $(nvgpu-t19x)/gv100/hal_gv100.o | 34 | $(nvgpu-t19x)/gv100/hal_gv100.o |
34 | 35 | ||
35 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o | 36 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index ff852168..3a8dc4b1 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -96,7 +96,7 @@ | |||
96 | #include "gv11b/regops_gv11b.h" | 96 | #include "gv11b/regops_gv11b.h" |
97 | 97 | ||
98 | #include "gv11b/gv11b_gating_reglist.h" | 98 | #include "gv11b/gv11b_gating_reglist.h" |
99 | #include "gv11b/regops_gv11b.h" | 99 | #include "gv100/regops_gv100.h" |
100 | #include "gv11b/subctx_gv11b.h" | 100 | #include "gv11b/subctx_gv11b.h" |
101 | 101 | ||
102 | #include "gv100.h" | 102 | #include "gv100.h" |
@@ -600,7 +600,27 @@ static const struct gpu_ops gv100_ops = { | |||
600 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, | 600 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, |
601 | }, | 601 | }, |
602 | .regops = { | 602 | .regops = { |
603 | .apply_smpc_war = gv11b_apply_smpc_war, | 603 | .get_global_whitelist_ranges = |
604 | gv100_get_global_whitelist_ranges, | ||
605 | .get_global_whitelist_ranges_count = | ||
606 | gv100_get_global_whitelist_ranges_count, | ||
607 | .get_context_whitelist_ranges = | ||
608 | gv100_get_context_whitelist_ranges, | ||
609 | .get_context_whitelist_ranges_count = | ||
610 | gv100_get_context_whitelist_ranges_count, | ||
611 | .get_runcontrol_whitelist = gv100_get_runcontrol_whitelist, | ||
612 | .get_runcontrol_whitelist_count = | ||
613 | gv100_get_runcontrol_whitelist_count, | ||
614 | .get_runcontrol_whitelist_ranges = | ||
615 | gv100_get_runcontrol_whitelist_ranges, | ||
616 | .get_runcontrol_whitelist_ranges_count = | ||
617 | gv100_get_runcontrol_whitelist_ranges_count, | ||
618 | .get_qctl_whitelist = gv100_get_qctl_whitelist, | ||
619 | .get_qctl_whitelist_count = gv100_get_qctl_whitelist_count, | ||
620 | .get_qctl_whitelist_ranges = gv100_get_qctl_whitelist_ranges, | ||
621 | .get_qctl_whitelist_ranges_count = | ||
622 | gv100_get_qctl_whitelist_ranges_count, | ||
623 | .apply_smpc_war = gv100_apply_smpc_war, | ||
604 | }, | 624 | }, |
605 | .mc = { | 625 | .mc = { |
606 | .intr_enable = mc_gv11b_intr_enable, | 626 | .intr_enable = mc_gv11b_intr_enable, |
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.c b/drivers/gpu/nvgpu/gv100/regops_gv100.c new file mode 100644 index 00000000..00f05418 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.c | |||
@@ -0,0 +1,463 @@ | |||
1 | /* | ||
2 | * Tegra GV100 GPU Driver Register Ops | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include "gk20a/dbg_gpu_gk20a.h" | ||
27 | #include "gk20a/regops_gk20a.h" | ||
28 | #include "regops_gv100.h" | ||
29 | |||
30 | static const struct regop_offset_range gv100_global_whitelist_ranges[] = { | ||
31 | { 0x000004f0, 1}, | ||
32 | { 0x00001a00, 3}, | ||
33 | { 0x00002800, 128}, | ||
34 | { 0x00009400, 1}, | ||
35 | { 0x00009410, 1}, | ||
36 | { 0x00009480, 1}, | ||
37 | { 0x00020200, 24}, | ||
38 | { 0x00021c00, 4}, | ||
39 | { 0x00021c14, 3}, | ||
40 | { 0x00021c24, 1}, | ||
41 | { 0x00021c2c, 69}, | ||
42 | { 0x00021d44, 1}, | ||
43 | { 0x00021d4c, 1}, | ||
44 | { 0x00021d54, 1}, | ||
45 | { 0x00021d5c, 1}, | ||
46 | { 0x00021d64, 2}, | ||
47 | { 0x00021d70, 16}, | ||
48 | { 0x00022430, 7}, | ||
49 | { 0x00022450, 1}, | ||
50 | { 0x0002245c, 2}, | ||
51 | { 0x00070000, 5}, | ||
52 | { 0x000884e0, 1}, | ||
53 | { 0x0008e00c, 1}, | ||
54 | { 0x00100c18, 3}, | ||
55 | { 0x00100c84, 1}, | ||
56 | { 0x00104038, 1}, | ||
57 | { 0x0010a0a8, 1}, | ||
58 | { 0x0010a4f0, 1}, | ||
59 | { 0x0010e490, 1}, | ||
60 | { 0x0013cc14, 1}, | ||
61 | { 0x00140028, 1}, | ||
62 | { 0x00140280, 1}, | ||
63 | { 0x001402a0, 1}, | ||
64 | { 0x00140350, 1}, | ||
65 | { 0x00140480, 1}, | ||
66 | { 0x001404a0, 1}, | ||
67 | { 0x00140550, 1}, | ||
68 | { 0x00142028, 1}, | ||
69 | { 0x00142280, 1}, | ||
70 | { 0x001422a0, 1}, | ||
71 | { 0x00142350, 1}, | ||
72 | { 0x00142480, 1}, | ||
73 | { 0x001424a0, 1}, | ||
74 | { 0x00142550, 1}, | ||
75 | { 0x0017e028, 1}, | ||
76 | { 0x0017e280, 1}, | ||
77 | { 0x0017e294, 1}, | ||
78 | { 0x0017e29c, 2}, | ||
79 | { 0x0017e2ac, 1}, | ||
80 | { 0x0017e350, 1}, | ||
81 | { 0x0017e39c, 1}, | ||
82 | { 0x0017e480, 1}, | ||
83 | { 0x0017e4a0, 1}, | ||
84 | { 0x0017e550, 1}, | ||
85 | { 0x00180040, 41}, | ||
86 | { 0x001800ec, 10}, | ||
87 | { 0x00180240, 41}, | ||
88 | { 0x001802ec, 10}, | ||
89 | { 0x00180440, 41}, | ||
90 | { 0x001804ec, 10}, | ||
91 | { 0x00180640, 41}, | ||
92 | { 0x001806ec, 10}, | ||
93 | { 0x00180840, 41}, | ||
94 | { 0x001808ec, 10}, | ||
95 | { 0x00180a40, 41}, | ||
96 | { 0x00180aec, 10}, | ||
97 | { 0x00180c40, 41}, | ||
98 | { 0x00180cec, 10}, | ||
99 | { 0x00180e40, 41}, | ||
100 | { 0x00180eec, 10}, | ||
101 | { 0x001a0040, 41}, | ||
102 | { 0x001a00ec, 10}, | ||
103 | { 0x001a0240, 41}, | ||
104 | { 0x001a02ec, 10}, | ||
105 | { 0x001a0440, 41}, | ||
106 | { 0x001a04ec, 10}, | ||
107 | { 0x001a0640, 41}, | ||
108 | { 0x001a06ec, 10}, | ||
109 | { 0x001a0840, 41}, | ||
110 | { 0x001a08ec, 10}, | ||
111 | { 0x001a0a40, 41}, | ||
112 | { 0x001a0aec, 10}, | ||
113 | { 0x001a0c40, 41}, | ||
114 | { 0x001a0cec, 10}, | ||
115 | { 0x001a0e40, 41}, | ||
116 | { 0x001a0eec, 10}, | ||
117 | { 0x001b0040, 41}, | ||
118 | { 0x001b00ec, 10}, | ||
119 | { 0x001b0240, 41}, | ||
120 | { 0x001b02ec, 10}, | ||
121 | { 0x001b0440, 41}, | ||
122 | { 0x001b04ec, 10}, | ||
123 | { 0x001b0640, 41}, | ||
124 | { 0x001b06ec, 10}, | ||
125 | { 0x001b0840, 41}, | ||
126 | { 0x001b08ec, 10}, | ||
127 | { 0x001b0a40, 41}, | ||
128 | { 0x001b0aec, 10}, | ||
129 | { 0x001b0c40, 41}, | ||
130 | { 0x001b0cec, 10}, | ||
131 | { 0x001b0e40, 41}, | ||
132 | { 0x001b0eec, 10}, | ||
133 | { 0x001b4000, 1}, | ||
134 | { 0x001b4008, 1}, | ||
135 | { 0x001b4010, 3}, | ||
136 | { 0x001b4020, 3}, | ||
137 | { 0x001b4030, 3}, | ||
138 | { 0x001b4040, 3}, | ||
139 | { 0x001b4050, 3}, | ||
140 | { 0x001b4060, 4}, | ||
141 | { 0x001b4074, 7}, | ||
142 | { 0x001b4094, 3}, | ||
143 | { 0x001b40a4, 1}, | ||
144 | { 0x001b4100, 6}, | ||
145 | { 0x001b4128, 1}, | ||
146 | { 0x001b8000, 1}, | ||
147 | { 0x001b8008, 1}, | ||
148 | { 0x001b8010, 2}, | ||
149 | { 0x001bc000, 1}, | ||
150 | { 0x001bc008, 1}, | ||
151 | { 0x001bc010, 2}, | ||
152 | { 0x001be000, 1}, | ||
153 | { 0x001be008, 1}, | ||
154 | { 0x001be010, 2}, | ||
155 | { 0x00400500, 1}, | ||
156 | { 0x0040415c, 1}, | ||
157 | { 0x00404468, 1}, | ||
158 | { 0x00404498, 1}, | ||
159 | { 0x00405800, 1}, | ||
160 | { 0x00405840, 2}, | ||
161 | { 0x00405850, 1}, | ||
162 | { 0x00405908, 1}, | ||
163 | { 0x00405b40, 1}, | ||
164 | { 0x00405b50, 1}, | ||
165 | { 0x00406024, 5}, | ||
166 | { 0x00407010, 1}, | ||
167 | { 0x00407808, 1}, | ||
168 | { 0x0040803c, 1}, | ||
169 | { 0x00408804, 1}, | ||
170 | { 0x0040880c, 1}, | ||
171 | { 0x00408900, 2}, | ||
172 | { 0x00408910, 1}, | ||
173 | { 0x00408944, 1}, | ||
174 | { 0x00408984, 1}, | ||
175 | { 0x004090a8, 1}, | ||
176 | { 0x004098a0, 1}, | ||
177 | { 0x00409b00, 1}, | ||
178 | { 0x0041000c, 1}, | ||
179 | { 0x00410110, 1}, | ||
180 | { 0x00410184, 1}, | ||
181 | { 0x0041040c, 1}, | ||
182 | { 0x00410510, 1}, | ||
183 | { 0x00410584, 1}, | ||
184 | { 0x00418000, 1}, | ||
185 | { 0x00418008, 1}, | ||
186 | { 0x00418380, 2}, | ||
187 | { 0x00418400, 2}, | ||
188 | { 0x004184a0, 1}, | ||
189 | { 0x00418604, 1}, | ||
190 | { 0x00418680, 1}, | ||
191 | { 0x00418704, 1}, | ||
192 | { 0x00418714, 1}, | ||
193 | { 0x00418800, 1}, | ||
194 | { 0x0041881c, 1}, | ||
195 | { 0x00418830, 1}, | ||
196 | { 0x00418884, 1}, | ||
197 | { 0x004188b0, 1}, | ||
198 | { 0x004188c8, 3}, | ||
199 | { 0x004188fc, 1}, | ||
200 | { 0x00418b04, 1}, | ||
201 | { 0x00418c04, 1}, | ||
202 | { 0x00418c10, 8}, | ||
203 | { 0x00418c88, 1}, | ||
204 | { 0x00418d00, 1}, | ||
205 | { 0x00418e00, 1}, | ||
206 | { 0x00418e08, 1}, | ||
207 | { 0x00418e34, 1}, | ||
208 | { 0x00418e40, 4}, | ||
209 | { 0x00418e58, 16}, | ||
210 | { 0x00418f08, 1}, | ||
211 | { 0x00419000, 1}, | ||
212 | { 0x0041900c, 1}, | ||
213 | { 0x00419018, 1}, | ||
214 | { 0x00419854, 1}, | ||
215 | { 0x00419864, 1}, | ||
216 | { 0x00419a04, 2}, | ||
217 | { 0x00419a14, 1}, | ||
218 | { 0x00419ab0, 1}, | ||
219 | { 0x00419ab8, 3}, | ||
220 | { 0x00419c0c, 1}, | ||
221 | { 0x00419c8c, 2}, | ||
222 | { 0x00419d00, 1}, | ||
223 | { 0x00419d08, 2}, | ||
224 | { 0x00419e00, 11}, | ||
225 | { 0x00419e34, 2}, | ||
226 | { 0x00419e44, 11}, | ||
227 | { 0x00419e74, 10}, | ||
228 | { 0x00419ea4, 1}, | ||
229 | { 0x00419eac, 2}, | ||
230 | { 0x00419ee8, 1}, | ||
231 | { 0x00419ef0, 28}, | ||
232 | { 0x00419f70, 1}, | ||
233 | { 0x00419f78, 2}, | ||
234 | { 0x00419f98, 2}, | ||
235 | { 0x0041a02c, 2}, | ||
236 | { 0x0041a0a8, 1}, | ||
237 | { 0x0041a8a0, 3}, | ||
238 | { 0x0041b014, 1}, | ||
239 | { 0x0041b0a0, 1}, | ||
240 | { 0x0041b0cc, 1}, | ||
241 | { 0x0041b1dc, 1}, | ||
242 | { 0x0041be0c, 3}, | ||
243 | { 0x0041bea0, 1}, | ||
244 | { 0x0041becc, 1}, | ||
245 | { 0x0041bfdc, 1}, | ||
246 | { 0x0041c054, 1}, | ||
247 | { 0x0041c2b0, 1}, | ||
248 | { 0x0041c2b8, 3}, | ||
249 | { 0x0041c40c, 1}, | ||
250 | { 0x0041c48c, 2}, | ||
251 | { 0x0041c500, 1}, | ||
252 | { 0x0041c508, 2}, | ||
253 | { 0x0041c600, 11}, | ||
254 | { 0x0041c634, 2}, | ||
255 | { 0x0041c644, 11}, | ||
256 | { 0x0041c674, 10}, | ||
257 | { 0x0041c6a4, 1}, | ||
258 | { 0x0041c6ac, 2}, | ||
259 | { 0x0041c6e8, 1}, | ||
260 | { 0x0041c6f0, 28}, | ||
261 | { 0x0041c770, 1}, | ||
262 | { 0x0041c778, 2}, | ||
263 | { 0x0041c798, 2}, | ||
264 | { 0x0041c854, 1}, | ||
265 | { 0x0041cab0, 1}, | ||
266 | { 0x0041cab8, 3}, | ||
267 | { 0x0041cc0c, 1}, | ||
268 | { 0x0041cc8c, 2}, | ||
269 | { 0x0041cd00, 1}, | ||
270 | { 0x0041cd08, 2}, | ||
271 | { 0x0041ce00, 11}, | ||
272 | { 0x0041ce34, 2}, | ||
273 | { 0x0041ce44, 11}, | ||
274 | { 0x0041ce74, 10}, | ||
275 | { 0x0041cea4, 1}, | ||
276 | { 0x0041ceac, 2}, | ||
277 | { 0x0041cee8, 1}, | ||
278 | { 0x0041cef0, 28}, | ||
279 | { 0x0041cf70, 1}, | ||
280 | { 0x0041cf78, 2}, | ||
281 | { 0x0041cf98, 2}, | ||
282 | { 0x00500384, 1}, | ||
283 | { 0x005004a0, 1}, | ||
284 | { 0x00500604, 1}, | ||
285 | { 0x00500680, 1}, | ||
286 | { 0x00500714, 1}, | ||
287 | { 0x0050081c, 1}, | ||
288 | { 0x00500884, 1}, | ||
289 | { 0x005008b0, 1}, | ||
290 | { 0x005008c8, 3}, | ||
291 | { 0x005008fc, 1}, | ||
292 | { 0x00500b04, 1}, | ||
293 | { 0x00500c04, 1}, | ||
294 | { 0x00500c10, 8}, | ||
295 | { 0x00500c88, 1}, | ||
296 | { 0x00500d00, 1}, | ||
297 | { 0x00500e08, 1}, | ||
298 | { 0x00500f08, 1}, | ||
299 | { 0x00501000, 1}, | ||
300 | { 0x0050100c, 1}, | ||
301 | { 0x00501018, 1}, | ||
302 | { 0x00501854, 1}, | ||
303 | { 0x00501ab0, 1}, | ||
304 | { 0x00501ab8, 3}, | ||
305 | { 0x00501c0c, 1}, | ||
306 | { 0x00501c8c, 2}, | ||
307 | { 0x00501d00, 1}, | ||
308 | { 0x00501d08, 2}, | ||
309 | { 0x00501e00, 11}, | ||
310 | { 0x00501e34, 2}, | ||
311 | { 0x00501e44, 11}, | ||
312 | { 0x00501e74, 10}, | ||
313 | { 0x00501ea4, 1}, | ||
314 | { 0x00501eac, 2}, | ||
315 | { 0x00501ee8, 1}, | ||
316 | { 0x00501ef0, 28}, | ||
317 | { 0x00501f70, 1}, | ||
318 | { 0x00501f78, 2}, | ||
319 | { 0x00501f98, 2}, | ||
320 | { 0x0050202c, 2}, | ||
321 | { 0x005020a8, 1}, | ||
322 | { 0x005028a0, 3}, | ||
323 | { 0x00503014, 1}, | ||
324 | { 0x005030a0, 1}, | ||
325 | { 0x005030cc, 1}, | ||
326 | { 0x005031dc, 1}, | ||
327 | { 0x00503e14, 1}, | ||
328 | { 0x00503ea0, 1}, | ||
329 | { 0x00503ecc, 1}, | ||
330 | { 0x00503fdc, 1}, | ||
331 | { 0x00504054, 1}, | ||
332 | { 0x005042b0, 1}, | ||
333 | { 0x005042b8, 3}, | ||
334 | { 0x0050440c, 1}, | ||
335 | { 0x0050448c, 2}, | ||
336 | { 0x00504500, 1}, | ||
337 | { 0x00504508, 2}, | ||
338 | { 0x00504600, 11}, | ||
339 | { 0x00504634, 2}, | ||
340 | { 0x00504644, 11}, | ||
341 | { 0x00504674, 10}, | ||
342 | { 0x005046a4, 1}, | ||
343 | { 0x005046ac, 2}, | ||
344 | { 0x005046e8, 1}, | ||
345 | { 0x005046f0, 28}, | ||
346 | { 0x00504770, 1}, | ||
347 | { 0x00504778, 2}, | ||
348 | { 0x00504798, 2}, | ||
349 | { 0x00504854, 1}, | ||
350 | { 0x00504ab0, 1}, | ||
351 | { 0x00504ab8, 3}, | ||
352 | { 0x00504c0c, 1}, | ||
353 | { 0x00504c8c, 2}, | ||
354 | { 0x00504d00, 1}, | ||
355 | { 0x00504d08, 2}, | ||
356 | { 0x00504e00, 11}, | ||
357 | { 0x00504e34, 2}, | ||
358 | { 0x00504e44, 11}, | ||
359 | { 0x00504e74, 10}, | ||
360 | { 0x00504ea4, 1}, | ||
361 | { 0x00504eac, 2}, | ||
362 | { 0x00504ee8, 1}, | ||
363 | { 0x00504ef0, 28}, | ||
364 | { 0x00504f70, 1}, | ||
365 | { 0x00504f78, 2}, | ||
366 | { 0x00504f98, 2}, | ||
367 | { 0x00900100, 1}, | ||
368 | { 0x009a0100, 1},}; | ||
369 | |||
370 | |||
371 | static const u32 gv100_global_whitelist_ranges_count = | ||
372 | ARRAY_SIZE(gv100_global_whitelist_ranges); | ||
373 | |||
374 | /* context */ | ||
375 | |||
376 | /* runcontrol */ | ||
377 | static const u32 gv100_runcontrol_whitelist[] = { | ||
378 | }; | ||
379 | static const u32 gv100_runcontrol_whitelist_count = | ||
380 | ARRAY_SIZE(gv100_runcontrol_whitelist); | ||
381 | |||
382 | static const struct regop_offset_range gv100_runcontrol_whitelist_ranges[] = { | ||
383 | }; | ||
384 | static const u32 gv100_runcontrol_whitelist_ranges_count = | ||
385 | ARRAY_SIZE(gv100_runcontrol_whitelist_ranges); | ||
386 | |||
387 | |||
388 | /* quad ctl */ | ||
389 | static const u32 gv100_qctl_whitelist[] = { | ||
390 | }; | ||
391 | static const u32 gv100_qctl_whitelist_count = | ||
392 | ARRAY_SIZE(gv100_qctl_whitelist); | ||
393 | |||
394 | static const struct regop_offset_range gv100_qctl_whitelist_ranges[] = { | ||
395 | }; | ||
396 | static const u32 gv100_qctl_whitelist_ranges_count = | ||
397 | ARRAY_SIZE(gv100_qctl_whitelist_ranges); | ||
398 | |||
399 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void) | ||
400 | { | ||
401 | return gv100_global_whitelist_ranges; | ||
402 | } | ||
403 | |||
404 | int gv100_get_global_whitelist_ranges_count(void) | ||
405 | { | ||
406 | return gv100_global_whitelist_ranges_count; | ||
407 | } | ||
408 | |||
409 | const struct regop_offset_range *gv100_get_context_whitelist_ranges(void) | ||
410 | { | ||
411 | return gv100_global_whitelist_ranges; | ||
412 | } | ||
413 | |||
414 | int gv100_get_context_whitelist_ranges_count(void) | ||
415 | { | ||
416 | return gv100_global_whitelist_ranges_count; | ||
417 | } | ||
418 | |||
419 | const u32 *gv100_get_runcontrol_whitelist(void) | ||
420 | { | ||
421 | return gv100_runcontrol_whitelist; | ||
422 | } | ||
423 | |||
424 | int gv100_get_runcontrol_whitelist_count(void) | ||
425 | { | ||
426 | return gv100_runcontrol_whitelist_count; | ||
427 | } | ||
428 | |||
429 | const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void) | ||
430 | { | ||
431 | return gv100_runcontrol_whitelist_ranges; | ||
432 | } | ||
433 | |||
434 | int gv100_get_runcontrol_whitelist_ranges_count(void) | ||
435 | { | ||
436 | return gv100_runcontrol_whitelist_ranges_count; | ||
437 | } | ||
438 | |||
439 | const u32 *gv100_get_qctl_whitelist(void) | ||
440 | { | ||
441 | return gv100_qctl_whitelist; | ||
442 | } | ||
443 | |||
444 | int gv100_get_qctl_whitelist_count(void) | ||
445 | { | ||
446 | return gv100_qctl_whitelist_count; | ||
447 | } | ||
448 | |||
449 | const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void) | ||
450 | { | ||
451 | return gv100_qctl_whitelist_ranges; | ||
452 | } | ||
453 | |||
454 | int gv100_get_qctl_whitelist_ranges_count(void) | ||
455 | { | ||
456 | return gv100_qctl_whitelist_ranges_count; | ||
457 | } | ||
458 | |||
459 | int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s) | ||
460 | { | ||
461 | /* Not needed on gv100 */ | ||
462 | return 0; | ||
463 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/regops_gv100.h b/drivers/gpu/nvgpu/gv100/regops_gv100.h new file mode 100644 index 00000000..06e5b8e1 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/regops_gv100.h | |||
@@ -0,0 +1,42 @@ | |||
1 | /* | ||
2 | * | ||
3 | * Tegra GV100 GPU Driver Register Ops | ||
4 | * | ||
5 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
6 | * | ||
7 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
8 | * copy of this software and associated documentation files (the "Software"), | ||
9 | * to deal in the Software without restriction, including without limitation | ||
10 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
11 | * and/or sell copies of the Software, and to permit persons to whom the | ||
12 | * Software is furnished to do so, subject to the following conditions: | ||
13 | * | ||
14 | * The above copyright notice and this permission notice shall be included in | ||
15 | * all copies or substantial portions of the Software. | ||
16 | * | ||
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
22 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
23 | * DEALINGS IN THE SOFTWARE. | ||
24 | */ | ||
25 | #ifndef __REGOPS_GV100_H_ | ||
26 | #define __REGOPS_GV100_H_ | ||
27 | |||
28 | const struct regop_offset_range *gv100_get_global_whitelist_ranges(void); | ||
29 | int gv100_get_global_whitelist_ranges_count(void); | ||
30 | const struct regop_offset_range *gv100_get_context_whitelist_ranges(void); | ||
31 | int gv100_get_context_whitelist_ranges_count(void); | ||
32 | const u32 *gv100_get_runcontrol_whitelist(void); | ||
33 | int gv100_get_runcontrol_whitelist_count(void); | ||
34 | const struct regop_offset_range *gv100_get_runcontrol_whitelist_ranges(void); | ||
35 | int gv100_get_runcontrol_whitelist_ranges_count(void); | ||
36 | const u32 *gv100_get_qctl_whitelist(void); | ||
37 | int gv100_get_qctl_whitelist_count(void); | ||
38 | const struct regop_offset_range *gv100_get_qctl_whitelist_ranges(void); | ||
39 | int gv100_get_qctl_whitelist_ranges_count(void); | ||
40 | int gv100_apply_smpc_war(struct dbg_session_gk20a *dbg_s); | ||
41 | |||
42 | #endif /* __REGOPS_GV11B_H_ */ | ||