diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/bios_gv100.c | 108 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/bios_gv100.h | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.c | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/mm_gv11b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | 4 |
8 files changed, 227 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index bbc1118d..1ca21fb5 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -22,6 +22,8 @@ nvgpu-y += \ | |||
22 | $(nvgpu-t19x)/gv100/mm_gv100.o \ | 22 | $(nvgpu-t19x)/gv100/mm_gv100.o \ |
23 | $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \ | 23 | $(nvgpu-t19x)/gv100/gr_ctx_gv100.o \ |
24 | $(nvgpu-t19x)/gv100/fb_gv100.o \ | 24 | $(nvgpu-t19x)/gv100/fb_gv100.o \ |
25 | $(nvgpu-t19x)/gv100/bios_gv100.o \ | ||
26 | $(nvgpu-t19x)/gv100/fifo_gv100.o \ | ||
25 | $(nvgpu-t19x)/gv100/hal_gv100.o | 27 | $(nvgpu-t19x)/gv100/hal_gv100.o |
26 | 28 | ||
27 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o | 29 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t19x)/gv11b/platform_gv11b_tegra.o |
diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.c b/drivers/gpu/nvgpu/gv100/bios_gv100.c new file mode 100644 index 00000000..9ca05a11 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.c | |||
@@ -0,0 +1,108 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/bios.h> | ||
24 | #include <nvgpu/nvgpu_common.h> | ||
25 | #include <nvgpu/timers.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | #include "gp106/bios_gp106.h" | ||
29 | #include "bios_gv100.h" | ||
30 | |||
31 | #include <nvgpu/hw/gv100/hw_pwr_gv100.h> | ||
32 | #include <nvgpu/hw/gv100/hw_bus_gv100.h> | ||
33 | |||
34 | #define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ | ||
35 | #define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */ | ||
36 | |||
37 | #define SCRATCH_PREOS_PROGRESS 6 | ||
38 | #define PREOS_PROGRESS_MASK(r) ((r >> 12) & 0xf) | ||
39 | #define PREOS_PROGRESS_NOT_STARTED 0 | ||
40 | #define PREOS_PROGRESS_STARTED 1 | ||
41 | #define PREOS_PROGRESS_EXIT 2 | ||
42 | #define PREOS_PROGRESS_EXIT_SECUREMODE 3 | ||
43 | #define PREOS_PROGRESS_ABORTED 6 | ||
44 | |||
45 | #define SCRATCH_PMU_EXIT_AND_HALT 1 | ||
46 | #define PMU_EXIT_AND_HALT_SET(r, v) ((r & ~0x200UL) | v) | ||
47 | #define PMU_EXIT_AND_HALT_YES (0x1UL << 9) | ||
48 | |||
49 | #define SCRATCH_PRE_OS_RELOAD 1 | ||
50 | #define PRE_OS_RELOAD_SET(r, v) ((r & ~0x100UL) | v) | ||
51 | #define PRE_OS_RELOAD_YES (0x1UL << 8) | ||
52 | |||
53 | |||
54 | void gv100_bios_preos_reload_check(struct gk20a *g) | ||
55 | { | ||
56 | u32 progress = gk20a_readl(g, | ||
57 | bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); | ||
58 | |||
59 | if (PREOS_PROGRESS_MASK(progress) != PREOS_PROGRESS_NOT_STARTED) { | ||
60 | u32 reload = gk20a_readl(g, | ||
61 | bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD)); | ||
62 | |||
63 | gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PRE_OS_RELOAD), | ||
64 | PRE_OS_RELOAD_SET(reload, PRE_OS_RELOAD_YES)); | ||
65 | } | ||
66 | } | ||
67 | |||
68 | int gv100_bios_preos_wait_for_halt(struct gk20a *g) | ||
69 | { | ||
70 | int err = -EINVAL; | ||
71 | u32 progress; | ||
72 | u32 tmp; | ||
73 | int preos_completed; | ||
74 | struct nvgpu_timeout timeout; | ||
75 | |||
76 | nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); | ||
77 | |||
78 | /* Check the progress */ | ||
79 | progress = gk20a_readl(g, bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); | ||
80 | |||
81 | if (PREOS_PROGRESS_MASK(progress) == PREOS_PROGRESS_STARTED) { | ||
82 | err = 0; | ||
83 | |||
84 | /* Complete the handshake */ | ||
85 | tmp = gk20a_readl(g, | ||
86 | bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT)); | ||
87 | |||
88 | gk20a_writel(g, bus_sw_scratch_r(SCRATCH_PMU_EXIT_AND_HALT), | ||
89 | PMU_EXIT_AND_HALT_SET(tmp, PMU_EXIT_AND_HALT_YES)); | ||
90 | |||
91 | nvgpu_timeout_init(g, &timeout, | ||
92 | PMU_BOOT_TIMEOUT_MAX / | ||
93 | PMU_BOOT_TIMEOUT_DEFAULT, | ||
94 | NVGPU_TIMER_RETRY_TIMER); | ||
95 | |||
96 | do { | ||
97 | progress = gk20a_readl(g, | ||
98 | bus_sw_scratch_r(SCRATCH_PREOS_PROGRESS)); | ||
99 | preos_completed = pwr_falcon_cpuctl_halt_intr_v( | ||
100 | gk20a_readl(g, pwr_falcon_cpuctl_r())) && | ||
101 | (PREOS_PROGRESS_MASK(progress) == | ||
102 | PREOS_PROGRESS_EXIT); | ||
103 | nvgpu_udelay(PMU_BOOT_TIMEOUT_DEFAULT); | ||
104 | } while (!preos_completed && !nvgpu_timeout_expired(&timeout)); | ||
105 | } | ||
106 | |||
107 | return err; | ||
108 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/bios_gv100.h b/drivers/gpu/nvgpu/gv100/bios_gv100.h new file mode 100644 index 00000000..c6433f57 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/bios_gv100.h | |||
@@ -0,0 +1,31 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef NVGPU_BIOS_GV100_H | ||
24 | #define NVGPU_BIOS_GV100_H | ||
25 | |||
26 | struct gk20a; | ||
27 | |||
28 | void gv100_bios_preos_reload_check(struct gk20a *g); | ||
29 | int gv100_bios_preos_wait_for_halt(struct gk20a *g); | ||
30 | |||
31 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c new file mode 100644 index 00000000..e19301e6 --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * GV100 fifo | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "fifo_gv100.h" | ||
26 | |||
27 | #include <nvgpu/hw/gv100/hw_ccsr_gv100.h> | ||
28 | |||
29 | u32 gv100_fifo_get_num_fifos(struct gk20a *g) | ||
30 | { | ||
31 | return ccsr_channel__size_1_v(); | ||
32 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h new file mode 100644 index 00000000..3ffb417c --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * GV100 Fifo | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef FIFO_GV100_H | ||
26 | #define FIFO_GV100_H | ||
27 | |||
28 | #include <nvgpu/types.h> | ||
29 | struct gk20a; | ||
30 | |||
31 | u32 gv100_fifo_get_num_fifos(struct gk20a *g); | ||
32 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 028c9d84..7f7ab785 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -61,6 +61,7 @@ | |||
61 | #include "gp106/acr_gp106.h" | 61 | #include "gp106/acr_gp106.h" |
62 | #include "gp106/sec2_gp106.h" | 62 | #include "gp106/sec2_gp106.h" |
63 | #include "gp106/bios_gp106.h" | 63 | #include "gp106/bios_gp106.h" |
64 | #include "gv100/bios_gv100.h" | ||
64 | #include "gp106/therm_gp106.h" | 65 | #include "gp106/therm_gp106.h" |
65 | #include "gp106/xve_gp106.h" | 66 | #include "gp106/xve_gp106.h" |
66 | #include "gp106/clk_gp106.h" | 67 | #include "gp106/clk_gp106.h" |
@@ -85,6 +86,10 @@ | |||
85 | #include "gv11b/mm_gv11b.h" | 86 | #include "gv11b/mm_gv11b.h" |
86 | #include "gv11b/pmu_gv11b.h" | 87 | #include "gv11b/pmu_gv11b.h" |
87 | #include "gv11b/fb_gv11b.h" | 88 | #include "gv11b/fb_gv11b.h" |
89 | #include "gv100/mm_gv100.h" | ||
90 | #include "gv11b/pmu_gv11b.h" | ||
91 | #include "gv100/fb_gv100.h" | ||
92 | #include "gv100/fifo_gv100.h" | ||
88 | #include "gv11b/fifo_gv11b.h" | 93 | #include "gv11b/fifo_gv11b.h" |
89 | #include "gv11b/gv11b_gating_reglist.h" | 94 | #include "gv11b/gv11b_gating_reglist.h" |
90 | #include "gv11b/regops_gv11b.h" | 95 | #include "gv11b/regops_gv11b.h" |
@@ -208,6 +213,11 @@ int gv100_init_gpu_characteristics(struct gk20a *g) | |||
208 | 213 | ||
209 | 214 | ||
210 | static const struct gpu_ops gv100_ops = { | 215 | static const struct gpu_ops gv100_ops = { |
216 | .bios = { | ||
217 | .init = gp106_bios_init, | ||
218 | .preos_wait_for_halt = gv100_bios_preos_wait_for_halt, | ||
219 | .preos_reload_check = gv100_bios_preos_reload_check, | ||
220 | }, | ||
211 | .ltc = { | 221 | .ltc = { |
212 | .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, | 222 | .determine_L2_size_bytes = gp10b_determine_L2_size_bytes, |
213 | .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, | 223 | .set_zbc_s_entry = gv11b_ltc_set_zbc_stencil_entry, |
@@ -218,7 +228,7 @@ static const struct gpu_ops gv100_ops = { | |||
218 | .init_comptags = gp10b_ltc_init_comptags, | 228 | .init_comptags = gp10b_ltc_init_comptags, |
219 | .cbc_ctrl = gm20b_ltc_cbc_ctrl, | 229 | .cbc_ctrl = gm20b_ltc_cbc_ctrl, |
220 | .isr = gv11b_ltc_isr, | 230 | .isr = gv11b_ltc_isr, |
221 | .cbc_fix_config = gv11b_ltc_cbc_fix_config, | 231 | .cbc_fix_config = NULL, |
222 | .flush = gm20b_flush_ltc, | 232 | .flush = gm20b_flush_ltc, |
223 | .set_enabled = gp10b_ltc_set_enabled, | 233 | .set_enabled = gp10b_ltc_set_enabled, |
224 | }, | 234 | }, |
@@ -374,8 +384,7 @@ static const struct gpu_ops gv100_ops = { | |||
374 | .fb = { | 384 | .fb = { |
375 | .reset = gv100_fb_reset, | 385 | .reset = gv100_fb_reset, |
376 | .init_hw = gk20a_fb_init_hw, | 386 | .init_hw = gk20a_fb_init_hw, |
377 | .init_fs_state = gv11b_fb_init_fs_state, | 387 | .init_fs_state = NULL, |
378 | .init_cbc = gv11b_fb_init_cbc, | ||
379 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | 388 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, |
380 | .set_use_full_comp_tag_line = | 389 | .set_use_full_comp_tag_line = |
381 | gm20b_fb_set_use_full_comp_tag_line, | 390 | gm20b_fb_set_use_full_comp_tag_line, |
@@ -417,7 +426,7 @@ static const struct gpu_ops gv100_ops = { | |||
417 | .trigger_mmu_fault = NULL, | 426 | .trigger_mmu_fault = NULL, |
418 | .get_mmu_fault_info = NULL, | 427 | .get_mmu_fault_info = NULL, |
419 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | 428 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, |
420 | .get_num_fifos = gv11b_fifo_get_num_fifos, | 429 | .get_num_fifos = gv100_fifo_get_num_fifos, |
421 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, | 430 | .get_pbdma_signature = gp10b_fifo_get_pbdma_signature, |
422 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | 431 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, |
423 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | 432 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, |
@@ -633,7 +642,6 @@ static const struct gpu_ops gv100_ops = { | |||
633 | }, | 642 | }, |
634 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, | 643 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, |
635 | .get_litter_value = gv100_get_litter_value, | 644 | .get_litter_value = gv100_get_litter_value, |
636 | .bios_init = gp106_bios_init, | ||
637 | }; | 645 | }; |
638 | 646 | ||
639 | int gv100_init_hal(struct gk20a *g) | 647 | int gv100_init_hal(struct gk20a *g) |
@@ -641,6 +649,7 @@ int gv100_init_hal(struct gk20a *g) | |||
641 | struct gpu_ops *gops = &g->ops; | 649 | struct gpu_ops *gops = &g->ops; |
642 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; | 650 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; |
643 | 651 | ||
652 | gops->bios = gv100_ops.bios; | ||
644 | gops->ltc = gv100_ops.ltc; | 653 | gops->ltc = gv100_ops.ltc; |
645 | gops->ce2 = gv100_ops.ce2; | 654 | gops->ce2 = gv100_ops.ce2; |
646 | gops->gr = gv100_ops.gr; | 655 | gops->gr = gv100_ops.gr; |
@@ -674,7 +683,6 @@ int gv100_init_hal(struct gk20a *g) | |||
674 | gops->chip_init_gpu_characteristics = | 683 | gops->chip_init_gpu_characteristics = |
675 | gv100_ops.chip_init_gpu_characteristics; | 684 | gv100_ops.chip_init_gpu_characteristics; |
676 | gops->get_litter_value = gv100_ops.get_litter_value; | 685 | gops->get_litter_value = gv100_ops.get_litter_value; |
677 | gops->bios_init = gv100_ops.bios_init; | ||
678 | 686 | ||
679 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 687 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
680 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 688 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
@@ -689,6 +697,8 @@ int gv100_init_hal(struct gk20a *g) | |||
689 | gv11b_init_uncompressed_kind_map(); | 697 | gv11b_init_uncompressed_kind_map(); |
690 | gv11b_init_kind_attr(); | 698 | gv11b_init_kind_attr(); |
691 | 699 | ||
700 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | ||
701 | |||
692 | g->name = "gv10x"; | 702 | g->name = "gv10x"; |
693 | 703 | ||
694 | c->twod_class = FERMI_TWOD_A; | 704 | c->twod_class = FERMI_TWOD_A; |
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index 6df29cb0..e452462e 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c | |||
@@ -118,7 +118,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, | |||
118 | fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * | 118 | fb_size = (g->ops.fifo.get_num_fifos(g) + 1) * |
119 | gmmu_fault_buf_size_v(); | 119 | gmmu_fault_buf_size_v(); |
120 | 120 | ||
121 | err = nvgpu_dma_alloc_map_sys(vm, fb_size, | 121 | err = nvgpu_dma_alloc_map(vm, fb_size, |
122 | &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); | 122 | &g->mm.hw_fault_buf[FAULT_TYPE_OTHER_AND_NONREPLAY]); |
123 | if (err) { | 123 | if (err) { |
124 | nvgpu_err(g, | 124 | nvgpu_err(g, |
@@ -131,7 +131,7 @@ static void gv11b_mm_mmu_hw_fault_buf_init(struct gk20a *g, | |||
131 | HW_FAULT_BUF_STATUS_ALLOC_TRUE; | 131 | HW_FAULT_BUF_STATUS_ALLOC_TRUE; |
132 | *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; | 132 | *hub_intr_types |= HUB_INTR_TYPE_NONREPLAY; |
133 | 133 | ||
134 | err = nvgpu_dma_alloc_map_sys(vm, fb_size, | 134 | err = nvgpu_dma_alloc_map(vm, fb_size, |
135 | &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); | 135 | &g->mm.hw_fault_buf[FAULT_TYPE_REPLAY]); |
136 | if (err) { | 136 | if (err) { |
137 | nvgpu_err(g, | 137 | nvgpu_err(g, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h index bc4f7f28..2c89ccd6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_bus_gv100.h | |||
@@ -56,6 +56,10 @@ | |||
56 | #ifndef _hw_bus_gv100_h_ | 56 | #ifndef _hw_bus_gv100_h_ |
57 | #define _hw_bus_gv100_h_ | 57 | #define _hw_bus_gv100_h_ |
58 | 58 | ||
59 | static inline u32 bus_sw_scratch_r(u32 i) | ||
60 | { | ||
61 | return 0x00001580 + i*4; | ||
62 | } | ||
59 | static inline u32 bus_bar0_window_r(void) | 63 | static inline u32 bus_bar0_window_r(void) |
60 | { | 64 | { |
61 | return 0x00001700; | 65 | return 0x00001700; |