diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
75 files changed, 418 insertions, 1096 deletions
diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig index 01744453..9e75339f 100644 --- a/drivers/gpu/nvgpu/Kconfig +++ b/drivers/gpu/nvgpu/Kconfig | |||
@@ -128,10 +128,3 @@ config GK20A_VIDMEM | |||
128 | Enable support for using and allocating buffers in a distinct video | 128 | Enable support for using and allocating buffers in a distinct video |
129 | memory aperture (in contrast to general system memory), available on | 129 | memory aperture (in contrast to general system memory), available on |
130 | GPUs that have their own banks. PCIe GPUs have this, for example. | 130 | GPUs that have their own banks. PCIe GPUs have this, for example. |
131 | |||
132 | config TEGRA_19x_GPU | ||
133 | bool "Tegra 19x family GPU" | ||
134 | depends on GK20A && ARCH_TEGRA_19x_SOC | ||
135 | default y | ||
136 | help | ||
137 | Support for NVIDIA Tegra 19x family of GPU | ||
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 8b366538..0ad630ff 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -18,6 +18,7 @@ obj-$(CONFIG_GK20A) := nvgpu.o | |||
18 | 18 | ||
19 | nvgpu-y := \ | 19 | nvgpu-y := \ |
20 | common/linux/module.o \ | 20 | common/linux/module.o \ |
21 | common/linux/module_usermode.o \ | ||
21 | common/linux/kmem.o \ | 22 | common/linux/kmem.o \ |
22 | common/linux/timers.o \ | 23 | common/linux/timers.o \ |
23 | common/linux/ioctl.o \ | 24 | common/linux/ioctl.o \ |
@@ -40,6 +41,7 @@ nvgpu-y := \ | |||
40 | common/linux/sysfs.o \ | 41 | common/linux/sysfs.o \ |
41 | common/linux/cde.o \ | 42 | common/linux/cde.o \ |
42 | common/linux/io.o \ | 43 | common/linux/io.o \ |
44 | common/linux/io_usermode.o \ | ||
43 | common/linux/rwsem.o \ | 45 | common/linux/rwsem.o \ |
44 | common/linux/cde_gm20b.o \ | 46 | common/linux/cde_gm20b.o \ |
45 | common/linux/cde_gp10b.o \ | 47 | common/linux/cde_gp10b.o \ |
@@ -148,9 +150,16 @@ endif | |||
148 | nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \ | 150 | nvgpu-$(CONFIG_GK20A_CTXSW_TRACE) += \ |
149 | common/linux/ctxsw_trace.o | 151 | common/linux/ctxsw_trace.o |
150 | 152 | ||
151 | nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gk20a_tegra.o | 153 | nvgpu-$(CONFIG_TEGRA_GK20A) += \ |
154 | common/linux/platform_gk20a_tegra.o \ | ||
155 | common/linux/platform_gp10b_tegra.o \ | ||
156 | common/linux/platform_gv11b_tegra.o | ||
157 | |||
152 | nvgpu-$(CONFIG_SYNC) += gk20a/sync_gk20a.o | 158 | nvgpu-$(CONFIG_SYNC) += gk20a/sync_gk20a.o |
153 | nvgpu-$(CONFIG_GK20A_PCI) += common/linux/pci.o | 159 | |
160 | nvgpu-$(CONFIG_GK20A_PCI) += common/linux/pci.o \ | ||
161 | common/linux/pci_usermode.o \ | ||
162 | |||
154 | nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += common/linux/nvhost.o | 163 | nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += common/linux/nvhost.o |
155 | 164 | ||
156 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | 165 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ |
@@ -211,6 +220,32 @@ nvgpu-y += \ | |||
211 | gp106/regops_gp106.o \ | 220 | gp106/regops_gp106.o \ |
212 | gp106/bios_gp106.o \ | 221 | gp106/bios_gp106.o \ |
213 | gp106/fuse_gp106.o \ | 222 | gp106/fuse_gp106.o \ |
223 | gv11b/gv11b.o \ | ||
224 | gv11b/css_gr_gv11b.o \ | ||
225 | gv11b/dbg_gpu_gv11b.o \ | ||
226 | gv11b/mc_gv11b.o \ | ||
227 | gv11b/ltc_gv11b.o \ | ||
228 | gv11b/hal_gv11b.o \ | ||
229 | gv11b/gv11b_gating_reglist.o \ | ||
230 | gv11b/gr_gv11b.o \ | ||
231 | gv11b/fb_gv11b.o \ | ||
232 | gv11b/fifo_gv11b.o \ | ||
233 | gv11b/mm_gv11b.o \ | ||
234 | gv11b/ce_gv11b.o \ | ||
235 | gv11b/gr_ctx_gv11b.o \ | ||
236 | gv11b/pmu_gv11b.o \ | ||
237 | gv11b/acr_gv11b.o \ | ||
238 | gv11b/subctx_gv11b.o \ | ||
239 | gv11b/regops_gv11b.o \ | ||
240 | gv11b/therm_gv11b.o \ | ||
241 | gv100/mm_gv100.o \ | ||
242 | gv100/gr_ctx_gv100.o \ | ||
243 | gv100/fb_gv100.o \ | ||
244 | gv100/bios_gv100.o \ | ||
245 | gv100/fifo_gv100.o \ | ||
246 | gv100/gr_gv100.o \ | ||
247 | gv100/regops_gv100.o \ | ||
248 | gv100/hal_gv100.o \ | ||
214 | pstate/pstate.o \ | 249 | pstate/pstate.o \ |
215 | clk/clk_vin.o \ | 250 | clk/clk_vin.o \ |
216 | clk/clk_fll.o \ | 251 | clk/clk_fll.o \ |
@@ -245,7 +280,6 @@ nvgpu-y += \ | |||
245 | lpwr/rppg.o \ | 280 | lpwr/rppg.o \ |
246 | lpwr/lpwr.o | 281 | lpwr/lpwr.o |
247 | 282 | ||
248 | nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gp10b_tegra.o | ||
249 | 283 | ||
250 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | 284 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ |
251 | common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ | 285 | common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ |
@@ -253,43 +287,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
253 | common/linux/vgpu/gp10b/vgpu_fuse_gp10b.o \ | 287 | common/linux/vgpu/gp10b/vgpu_fuse_gp10b.o \ |
254 | common/linux/vgpu/gp10b/vgpu_mm_gp10b.o | 288 | common/linux/vgpu/gp10b/vgpu_mm_gp10b.o |
255 | 289 | ||
256 | ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) | ||
257 | nvgpu-y += \ | ||
258 | common/mm/gmmu_t19x.o \ | ||
259 | common/linux/ioctl_tsg_t19x.o \ | ||
260 | common/linux/ioctl_ctrl_t19x.o \ | ||
261 | common/linux/io_t19x.o \ | ||
262 | common/linux/module_t19x.o \ | ||
263 | common/linux/pci_t19x.o \ | ||
264 | gv11b/gv11b.o \ | ||
265 | gv11b/css_gr_gv11b.o \ | ||
266 | gv11b/dbg_gpu_gv11b.o \ | ||
267 | gv11b/mc_gv11b.o \ | ||
268 | gv11b/ltc_gv11b.o \ | ||
269 | gv11b/hal_gv11b.o \ | ||
270 | gv11b/gv11b_gating_reglist.o \ | ||
271 | gv11b/gr_gv11b.o \ | ||
272 | gv11b/fb_gv11b.o \ | ||
273 | gv11b/fifo_gv11b.o \ | ||
274 | gv11b/mm_gv11b.o \ | ||
275 | gv11b/ce_gv11b.o \ | ||
276 | gv11b/gr_ctx_gv11b.o \ | ||
277 | gv11b/pmu_gv11b.o \ | ||
278 | gv11b/acr_gv11b.o \ | ||
279 | gv11b/subctx_gv11b.o \ | ||
280 | gv11b/regops_gv11b.o \ | ||
281 | gv11b/therm_gv11b.o \ | ||
282 | gv100/mm_gv100.o \ | ||
283 | gv100/gr_ctx_gv100.o \ | ||
284 | gv100/fb_gv100.o \ | ||
285 | gv100/bios_gv100.o \ | ||
286 | gv100/fifo_gv100.o \ | ||
287 | gv100/gr_gv100.o \ | ||
288 | gv100/regops_gv100.o \ | ||
289 | gv100/hal_gv100.o | ||
290 | |||
291 | nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gv11b_tegra.o | ||
292 | nvgpu-$(CONFIG_TEGRA_GK20A_NVHOST) += common/linux/nvhost_t19x.o | ||
293 | 290 | ||
294 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | 291 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ |
295 | common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.o \ | 292 | common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.o \ |
@@ -299,4 +296,3 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
299 | common/linux/vgpu/gv11b/vgpu_fifo_gv11b.o \ | 296 | common/linux/vgpu/gv11b/vgpu_fifo_gv11b.o \ |
300 | common/linux/vgpu/gv11b/vgpu_subctx_gv11b.o \ | 297 | common/linux/vgpu/gv11b/vgpu_subctx_gv11b.o \ |
301 | common/linux/vgpu/gv11b/vgpu_tsg_gv11b.o | 298 | common/linux/vgpu/gv11b/vgpu_tsg_gv11b.o |
302 | endif | ||
diff --git a/drivers/gpu/nvgpu/channel_t19x.h b/drivers/gpu/nvgpu/channel_t19x.h deleted file mode 100644 index d3cb71a1..00000000 --- a/drivers/gpu/nvgpu/channel_t19x.h +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | /* | ||
2 | * NVIDIA T19x Channel info | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_CHANNEL_T19X_H_ | ||
26 | #define _NVGPU_CHANNEL_T19X_H_ | ||
27 | |||
28 | struct channel_t19x { | ||
29 | u32 subctx_id; | ||
30 | u32 runqueue_sel; | ||
31 | }; | ||
32 | |||
33 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/io_t19x.c b/drivers/gpu/nvgpu/common/linux/io_usermode.c index 5c6b76ba..888be318 100644 --- a/drivers/gpu/nvgpu/common/linux/io_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/io_usermode.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -19,10 +19,10 @@ | |||
19 | 19 | ||
20 | #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h> | 20 | #include <nvgpu/hw/gv11b/hw_usermode_gv11b.h> |
21 | 21 | ||
22 | void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v) | 22 | void nvgpu_usermode_writel(struct gk20a *g, u32 r, u32 v) |
23 | { | 23 | { |
24 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 24 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
25 | void __iomem *reg = l->t19x.usermode_regs + (r - usermode_cfg0_r()); | 25 | void __iomem *reg = l->usermode_regs + (r - usermode_cfg0_r()); |
26 | 26 | ||
27 | writel_relaxed(v, reg); | 27 | writel_relaxed(v, reg); |
28 | gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); | 28 | gk20a_dbg(gpu_dbg_reg, "usermode r=0x%x v=0x%x", r, v); |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c index 866ac39e..ebbe7dda 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2017, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -35,9 +35,6 @@ | |||
35 | #include "ioctl_ctrl.h" | 35 | #include "ioctl_ctrl.h" |
36 | #include "ioctl_dbg.h" | 36 | #include "ioctl_dbg.h" |
37 | #include "ioctl_as.h" | 37 | #include "ioctl_as.h" |
38 | #ifdef CONFIG_TEGRA_19x_GPU | ||
39 | #include "common/linux/ioctl_ctrl_t19x.h" | ||
40 | #endif | ||
41 | #include "ioctl_tsg.h" | 38 | #include "ioctl_tsg.h" |
42 | #include "ioctl_channel.h" | 39 | #include "ioctl_channel.h" |
43 | #include "gk20a/gk20a.h" | 40 | #include "gk20a/gk20a.h" |
@@ -173,6 +170,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = { | |||
173 | NVGPU_ECC_ENABLED_TEX}, | 170 | NVGPU_ECC_ENABLED_TEX}, |
174 | {NVGPU_GPU_FLAGS_ECC_ENABLED_LTC, | 171 | {NVGPU_GPU_FLAGS_ECC_ENABLED_LTC, |
175 | NVGPU_ECC_ENABLED_LTC}, | 172 | NVGPU_ECC_ENABLED_LTC}, |
173 | {NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS, | ||
174 | NVGPU_SUPPORT_TSG_SUBCONTEXTS}, | ||
176 | }; | 175 | }; |
177 | 176 | ||
178 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) | 177 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) |
@@ -240,9 +239,7 @@ gk20a_ctrl_ioctl_gpu_characteristics( | |||
240 | gpu.gpc_mask = (1 << g->gr.gpc_count)-1; | 239 | gpu.gpc_mask = (1 << g->gr.gpc_count)-1; |
241 | 240 | ||
242 | gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); | 241 | gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); |
243 | #ifdef CONFIG_TEGRA_19x_GPU | 242 | |
244 | gpu.flags |= nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(g); | ||
245 | #endif | ||
246 | gpu.arch = g->params.gpu_arch; | 243 | gpu.arch = g->params.gpu_arch; |
247 | gpu.impl = g->params.gpu_impl; | 244 | gpu.impl = g->params.gpu_impl; |
248 | gpu.rev = g->params.gpu_rev; | 245 | gpu.rev = g->params.gpu_rev; |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c deleted file mode 100644 index a04fb5c9..00000000 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.c +++ /dev/null | |||
@@ -1,33 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include <uapi/linux/nvgpu.h> | ||
15 | |||
16 | #include <nvgpu/types.h> | ||
17 | #include <nvgpu/enabled.h> | ||
18 | #include <nvgpu/enabled_t19x.h> | ||
19 | |||
20 | #include "ioctl_ctrl_t19x.h" | ||
21 | #include "common/linux/os_linux.h" | ||
22 | #include "gk20a/gk20a.h" | ||
23 | |||
24 | u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(struct gk20a *g) | ||
25 | { | ||
26 | u64 ioctl_flags = 0; | ||
27 | |||
28 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_TSG_SUBCONTEXTS)) | ||
29 | ioctl_flags |= NVGPU_GPU_FLAGS_SUPPORT_TSG_SUBCONTEXTS; | ||
30 | |||
31 | return ioctl_flags; | ||
32 | } | ||
33 | |||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h deleted file mode 100644 index 64141223..00000000 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl_t19x.h +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef _NVGPU_IOCTL_CTRL_T19X | ||
15 | #define _NVGPU_IOCTL_CTRL_T19X | ||
16 | |||
17 | #include <nvgpu/types.h> | ||
18 | |||
19 | struct gk20a; | ||
20 | |||
21 | u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(struct gk20a *g); | ||
22 | |||
23 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c index 03577b97..60aca5ec 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_tsg.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -27,13 +27,11 @@ | |||
27 | 27 | ||
28 | #include "gk20a/gk20a.h" | 28 | #include "gk20a/gk20a.h" |
29 | #include "gk20a/tsg_gk20a.h" | 29 | #include "gk20a/tsg_gk20a.h" |
30 | #include "gv11b/fifo_gv11b.h" | ||
30 | #include "platform_gk20a.h" | 31 | #include "platform_gk20a.h" |
31 | #include "ioctl_tsg.h" | 32 | #include "ioctl_tsg.h" |
32 | #include "ioctl_channel.h" | 33 | #include "ioctl_channel.h" |
33 | #include "os_linux.h" | 34 | #include "os_linux.h" |
34 | #ifdef CONFIG_TEGRA_19x_GPU | ||
35 | #include "common/linux/ioctl_tsg_t19x.h" | ||
36 | #endif | ||
37 | 35 | ||
38 | struct tsg_private { | 36 | struct tsg_private { |
39 | struct gk20a *g; | 37 | struct gk20a *g; |
@@ -55,6 +53,72 @@ static int gk20a_tsg_bind_channel_fd(struct tsg_gk20a *tsg, int ch_fd) | |||
55 | return err; | 53 | return err; |
56 | } | 54 | } |
57 | 55 | ||
56 | static int gk20a_tsg_ioctl_bind_channel_ex(struct gk20a *g, | ||
57 | struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) | ||
58 | { | ||
59 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
60 | struct gk20a_sched_ctrl *sched = &l->sched_ctrl; | ||
61 | struct channel_gk20a *ch; | ||
62 | struct gr_gk20a *gr = &g->gr; | ||
63 | int err = 0; | ||
64 | |||
65 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); | ||
66 | |||
67 | nvgpu_mutex_acquire(&sched->control_lock); | ||
68 | if (sched->control_locked) { | ||
69 | err = -EPERM; | ||
70 | goto mutex_release; | ||
71 | } | ||
72 | err = gk20a_busy(g); | ||
73 | if (err) { | ||
74 | nvgpu_err(g, "failed to power on gpu"); | ||
75 | goto mutex_release; | ||
76 | } | ||
77 | |||
78 | ch = gk20a_get_channel_from_file(arg->channel_fd); | ||
79 | if (!ch) { | ||
80 | err = -EINVAL; | ||
81 | goto idle; | ||
82 | } | ||
83 | |||
84 | if (arg->tpc_pg_enabled && (!tsg->tpc_num_initialized)) { | ||
85 | if ((arg->num_active_tpcs > gr->max_tpc_count) || | ||
86 | !(arg->num_active_tpcs)) { | ||
87 | nvgpu_err(g, "Invalid num of active TPCs"); | ||
88 | err = -EINVAL; | ||
89 | goto ch_put; | ||
90 | } | ||
91 | tsg->tpc_num_initialized = true; | ||
92 | tsg->num_active_tpcs = arg->num_active_tpcs; | ||
93 | tsg->tpc_pg_enabled = true; | ||
94 | } else { | ||
95 | tsg->tpc_pg_enabled = false; nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled"); | ||
96 | } | ||
97 | |||
98 | if (arg->subcontext_id < g->fifo.max_subctx_count) { | ||
99 | ch->subctx_id = arg->subcontext_id; | ||
100 | } else { | ||
101 | err = -EINVAL; | ||
102 | goto ch_put; | ||
103 | } | ||
104 | |||
105 | nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d", | ||
106 | ch->chid, ch->subctx_id); | ||
107 | |||
108 | /* Use runqueue selector 1 for all ASYNC ids */ | ||
109 | if (ch->subctx_id > CHANNEL_INFO_VEID0) | ||
110 | ch->runqueue_sel = 1; | ||
111 | |||
112 | err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch); | ||
113 | ch_put: | ||
114 | gk20a_channel_put(ch); | ||
115 | idle: | ||
116 | gk20a_idle(g); | ||
117 | mutex_release: | ||
118 | nvgpu_mutex_release(&sched->control_lock); | ||
119 | return err; | ||
120 | } | ||
121 | |||
58 | static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg, | 122 | static int gk20a_tsg_get_event_data_from_id(struct tsg_gk20a *tsg, |
59 | unsigned int event_id, | 123 | unsigned int event_id, |
60 | struct gk20a_event_id_data **event_id_data) | 124 | struct gk20a_event_id_data **event_id_data) |
@@ -478,6 +542,13 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | |||
478 | break; | 542 | break; |
479 | } | 543 | } |
480 | 544 | ||
545 | case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX: | ||
546 | { | ||
547 | err = gk20a_tsg_ioctl_bind_channel_ex(g, tsg, | ||
548 | (struct nvgpu_tsg_bind_channel_ex_args *)buf); | ||
549 | break; | ||
550 | } | ||
551 | |||
481 | case NVGPU_TSG_IOCTL_UNBIND_CHANNEL: | 552 | case NVGPU_TSG_IOCTL_UNBIND_CHANNEL: |
482 | /* We do not support explicitly unbinding channel from TSG. | 553 | /* We do not support explicitly unbinding channel from TSG. |
483 | * Channel will be unbounded from TSG when it is closed. | 554 | * Channel will be unbounded from TSG when it is closed. |
@@ -550,13 +621,9 @@ long nvgpu_ioctl_tsg_dev_ioctl(struct file *filp, unsigned int cmd, | |||
550 | } | 621 | } |
551 | 622 | ||
552 | default: | 623 | default: |
553 | #ifdef CONFIG_TEGRA_19x_GPU | ||
554 | err = t19x_tsg_ioctl_handler(g, tsg, cmd, buf); | ||
555 | #else | ||
556 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", | 624 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", |
557 | cmd); | 625 | cmd); |
558 | err = -ENOTTY; | 626 | err = -ENOTTY; |
559 | #endif | ||
560 | break; | 627 | break; |
561 | } | 628 | } |
562 | 629 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c deleted file mode 100644 index 1c96db69..00000000 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.c +++ /dev/null | |||
@@ -1,115 +0,0 @@ | |||
1 | /* | ||
2 | * GV11B TSG IOCTL Handler | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | #include <uapi/linux/nvgpu.h> | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | |||
21 | #include "gv11b/fifo_gv11b.h" | ||
22 | #include "gv11b/subctx_gv11b.h" | ||
23 | #include "ioctl_tsg_t19x.h" | ||
24 | #include "common/linux/os_linux.h" | ||
25 | |||
26 | static int gv11b_tsg_ioctl_bind_channel_ex(struct gk20a *g, | ||
27 | struct tsg_gk20a *tsg, struct nvgpu_tsg_bind_channel_ex_args *arg) | ||
28 | { | ||
29 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | ||
30 | struct gk20a_sched_ctrl *sched = &l->sched_ctrl; | ||
31 | struct channel_gk20a *ch; | ||
32 | struct gr_gk20a *gr = &g->gr; | ||
33 | int err = 0; | ||
34 | |||
35 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_sched, "tsgid=%u", tsg->tsgid); | ||
36 | |||
37 | nvgpu_mutex_acquire(&sched->control_lock); | ||
38 | if (sched->control_locked) { | ||
39 | err = -EPERM; | ||
40 | goto mutex_release; | ||
41 | } | ||
42 | err = gk20a_busy(g); | ||
43 | if (err) { | ||
44 | nvgpu_err(g, "failed to power on gpu"); | ||
45 | goto mutex_release; | ||
46 | } | ||
47 | |||
48 | ch = gk20a_get_channel_from_file(arg->channel_fd); | ||
49 | if (!ch) { | ||
50 | err = -EINVAL; | ||
51 | goto idle; | ||
52 | } | ||
53 | |||
54 | if (arg->tpc_pg_enabled && (!tsg->t19x.tpc_num_initialized)) { | ||
55 | if ((arg->num_active_tpcs > gr->max_tpc_count) || | ||
56 | !(arg->num_active_tpcs)) { | ||
57 | nvgpu_err(g, "Invalid num of active TPCs"); | ||
58 | err = -EINVAL; | ||
59 | goto ch_put; | ||
60 | } | ||
61 | tsg->t19x.tpc_num_initialized = true; | ||
62 | tsg->t19x.num_active_tpcs = arg->num_active_tpcs; | ||
63 | tsg->t19x.tpc_pg_enabled = true; | ||
64 | } else { | ||
65 | tsg->t19x.tpc_pg_enabled = false; | ||
66 | nvgpu_log(g, gpu_dbg_info, "dynamic TPC-PG not enabled"); | ||
67 | } | ||
68 | |||
69 | if (arg->subcontext_id < g->fifo.t19x.max_subctx_count) { | ||
70 | ch->t19x.subctx_id = arg->subcontext_id; | ||
71 | } else { | ||
72 | err = -EINVAL; | ||
73 | goto ch_put; | ||
74 | } | ||
75 | |||
76 | nvgpu_log(g, gpu_dbg_info, "channel id : %d : subctx: %d", | ||
77 | ch->chid, ch->t19x.subctx_id); | ||
78 | |||
79 | /* Use runqueue selector 1 for all ASYNC ids */ | ||
80 | if (ch->t19x.subctx_id > CHANNEL_INFO_VEID0) | ||
81 | ch->t19x.runqueue_sel = 1; | ||
82 | |||
83 | err = ch->g->ops.fifo.tsg_bind_channel(tsg, ch); | ||
84 | ch_put: | ||
85 | gk20a_channel_put(ch); | ||
86 | idle: | ||
87 | gk20a_idle(g); | ||
88 | mutex_release: | ||
89 | nvgpu_mutex_release(&sched->control_lock); | ||
90 | return err; | ||
91 | } | ||
92 | |||
93 | int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg, | ||
94 | unsigned int cmd, u8 *buf) | ||
95 | { | ||
96 | int err = 0; | ||
97 | |||
98 | nvgpu_log(g, gpu_dbg_fn, "t19x_tsg_ioctl_handler"); | ||
99 | |||
100 | switch (cmd) { | ||
101 | case NVGPU_TSG_IOCTL_BIND_CHANNEL_EX: | ||
102 | { | ||
103 | err = gv11b_tsg_ioctl_bind_channel_ex(g, tsg, | ||
104 | (struct nvgpu_tsg_bind_channel_ex_args *)buf); | ||
105 | break; | ||
106 | } | ||
107 | |||
108 | default: | ||
109 | nvgpu_err(g, "unrecognized tsg gpu ioctl cmd: 0x%x", | ||
110 | cmd); | ||
111 | err = -ENOTTY; | ||
112 | break; | ||
113 | } | ||
114 | return err; | ||
115 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h b/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h deleted file mode 100644 index 3376ffce..00000000 --- a/drivers/gpu/nvgpu/common/linux/ioctl_tsg_t19x.h +++ /dev/null | |||
@@ -1,21 +0,0 @@ | |||
1 | /* | ||
2 | * GV11B TSG IOCTL handler | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #ifndef _NVGPU_IOCTL_TSG_T19X | ||
17 | #define _NVGPU_IOCTL_TSG_T19X | ||
18 | |||
19 | int t19x_tsg_ioctl_handler(struct gk20a *g, struct tsg_gk20a *tsg, | ||
20 | unsigned int cmd, u8 *arg); | ||
21 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c index c153b56f..d22455ff 100644 --- a/drivers/gpu/nvgpu/common/linux/module.c +++ b/drivers/gpu/nvgpu/common/linux/module.c | |||
@@ -46,13 +46,11 @@ | |||
46 | #include "scale.h" | 46 | #include "scale.h" |
47 | #include "pci.h" | 47 | #include "pci.h" |
48 | #include "module.h" | 48 | #include "module.h" |
49 | #include "module_usermode.h" | ||
49 | #include "intr.h" | 50 | #include "intr.h" |
50 | #include "cde.h" | 51 | #include "cde.h" |
51 | #include "ioctl.h" | 52 | #include "ioctl.h" |
52 | #include "sim.h" | 53 | #include "sim.h" |
53 | #ifdef CONFIG_TEGRA_19x_GPU | ||
54 | #include "nvgpu_gpuid_t19x.h" | ||
55 | #endif | ||
56 | 54 | ||
57 | #include "os_linux.h" | 55 | #include "os_linux.h" |
58 | #include "cde_gm20b.h" | 56 | #include "cde_gm20b.h" |
@@ -175,9 +173,7 @@ static int gk20a_restore_registers(struct gk20a *g) | |||
175 | l->regs = l->regs_saved; | 173 | l->regs = l->regs_saved; |
176 | l->bar1 = l->bar1_saved; | 174 | l->bar1 = l->bar1_saved; |
177 | 175 | ||
178 | #ifdef CONFIG_TEGRA_19x_GPU | 176 | nvgpu_restore_usermode_registers(g); |
179 | t19x_restore_registers(g); | ||
180 | #endif | ||
181 | 177 | ||
182 | return 0; | 178 | return 0; |
183 | } | 179 | } |
@@ -313,9 +309,7 @@ static int gk20a_lockout_registers(struct gk20a *g) | |||
313 | l->regs = NULL; | 309 | l->regs = NULL; |
314 | l->bar1 = NULL; | 310 | l->bar1 = NULL; |
315 | 311 | ||
316 | #ifdef CONFIG_TEGRA_19x_GPU | 312 | nvgpu_lockout_usermode_registers(g); |
317 | t19x_lockout_registers(g); | ||
318 | #endif | ||
319 | 313 | ||
320 | return 0; | 314 | return 0; |
321 | } | 315 | } |
@@ -384,14 +378,12 @@ static struct of_device_id tegra_gk20a_of_match[] = { | |||
384 | .data = &gm20b_tegra_platform }, | 378 | .data = &gm20b_tegra_platform }, |
385 | { .compatible = "nvidia,tegra186-gp10b", | 379 | { .compatible = "nvidia,tegra186-gp10b", |
386 | .data = &gp10b_tegra_platform }, | 380 | .data = &gp10b_tegra_platform }, |
387 | #ifdef CONFIG_TEGRA_19x_GPU | 381 | { .compatible = "nvidia,gv11b", |
388 | { .compatible = TEGRA_19x_GPU_COMPAT_TEGRA, | 382 | .data = &gv11b_tegra_platform }, |
389 | .data = &t19x_gpu_tegra_platform }, | ||
390 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 383 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
391 | { .compatible = "nvidia,gv11b-vgpu", | 384 | { .compatible = "nvidia,gv11b-vgpu", |
392 | .data = &gv11b_vgpu_tegra_platform}, | 385 | .data = &gv11b_vgpu_tegra_platform}, |
393 | #endif | 386 | #endif |
394 | #endif | ||
395 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 387 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
396 | { .compatible = "nvidia,tegra124-gk20a-vgpu", | 388 | { .compatible = "nvidia,tegra124-gk20a-vgpu", |
397 | .data = &vgpu_tegra_platform }, | 389 | .data = &vgpu_tegra_platform }, |
@@ -669,9 +661,7 @@ void gk20a_remove_support(struct gk20a *g) | |||
669 | l->bar1 = NULL; | 661 | l->bar1 = NULL; |
670 | } | 662 | } |
671 | 663 | ||
672 | #ifdef CONFIG_TEGRA_19x_GPU | 664 | nvgpu_remove_usermode_support(g); |
673 | t19x_remove_support(g); | ||
674 | #endif | ||
675 | 665 | ||
676 | nvgpu_free_enabled_flags(g); | 666 | nvgpu_free_enabled_flags(g); |
677 | } | 667 | } |
@@ -721,9 +711,7 @@ static int gk20a_init_support(struct platform_device *dev) | |||
721 | goto fail; | 711 | goto fail; |
722 | } | 712 | } |
723 | 713 | ||
724 | #ifdef CONFIG_TEGRA_19x_GPU | 714 | nvgpu_init_usermode_support(g); |
725 | t19x_init_support(g); | ||
726 | #endif | ||
727 | 715 | ||
728 | return 0; | 716 | return 0; |
729 | 717 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/module.h b/drivers/gpu/nvgpu/common/linux/module.h index 934c895d..e6aa9ef8 100644 --- a/drivers/gpu/nvgpu/common/linux/module.h +++ b/drivers/gpu/nvgpu/common/linux/module.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -13,10 +13,6 @@ | |||
13 | #ifndef __NVGPU_COMMON_LINUX_MODULE_H__ | 13 | #ifndef __NVGPU_COMMON_LINUX_MODULE_H__ |
14 | #define __NVGPU_COMMON_LINUX_MODULE_H__ | 14 | #define __NVGPU_COMMON_LINUX_MODULE_H__ |
15 | 15 | ||
16 | #ifdef CONFIG_TEGRA_19x_GPU | ||
17 | #include <nvgpu/linux/module_t19x.h> | ||
18 | #endif | ||
19 | |||
20 | struct gk20a; | 16 | struct gk20a; |
21 | struct device; | 17 | struct device; |
22 | struct nvgpu_os_linux; | 18 | struct nvgpu_os_linux; |
diff --git a/drivers/gpu/nvgpu/common/linux/module_t19x.c b/drivers/gpu/nvgpu/common/linux/module_usermode.c index f0e3d438..61cb4e87 100644 --- a/drivers/gpu/nvgpu/common/linux/module_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/module_usermode.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -27,36 +27,36 @@ | |||
27 | * after the GPU has been turned off. On older chips these reads and writes can | 27 | * after the GPU has been turned off. On older chips these reads and writes can |
28 | * also lock the entire CPU up. | 28 | * also lock the entire CPU up. |
29 | */ | 29 | */ |
30 | void t19x_lockout_registers(struct gk20a *g) | 30 | void nvgpu_lockout_usermode_registers(struct gk20a *g) |
31 | { | 31 | { |
32 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 32 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
33 | 33 | ||
34 | l->t19x.usermode_regs = NULL; | 34 | l->usermode_regs = NULL; |
35 | } | 35 | } |
36 | 36 | ||
37 | /* | 37 | /* |
38 | * Undoes t19x_lockout_registers(). | 38 | * Undoes t19x_lockout_registers(). |
39 | */ | 39 | */ |
40 | void t19x_restore_registers(struct gk20a *g) | 40 | void nvgpu_restore_usermode_registers(struct gk20a *g) |
41 | { | 41 | { |
42 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 42 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
43 | 43 | ||
44 | l->t19x.usermode_regs = l->t19x.usermode_regs_saved; | 44 | l->usermode_regs = l->usermode_regs_saved; |
45 | } | 45 | } |
46 | 46 | ||
47 | void t19x_remove_support(struct gk20a *g) | 47 | void nvgpu_remove_usermode_support(struct gk20a *g) |
48 | { | 48 | { |
49 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 49 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
50 | 50 | ||
51 | if (l->t19x.usermode_regs) { | 51 | if (l->usermode_regs) { |
52 | l->t19x.usermode_regs = NULL; | 52 | l->usermode_regs = NULL; |
53 | } | 53 | } |
54 | } | 54 | } |
55 | 55 | ||
56 | void t19x_init_support(struct gk20a *g) | 56 | void nvgpu_init_usermode_support(struct gk20a *g) |
57 | { | 57 | { |
58 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); | 58 | struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); |
59 | 59 | ||
60 | l->t19x.usermode_regs = l->regs + usermode_cfg0_r(); | 60 | l->usermode_regs = l->regs + usermode_cfg0_r(); |
61 | l->t19x.usermode_regs_saved = l->t19x.usermode_regs; | 61 | l->usermode_regs_saved = l->usermode_regs; |
62 | } | 62 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h b/drivers/gpu/nvgpu/common/linux/module_usermode.h index a105c6dc..b17053ca 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/linux/module_t19x.h +++ b/drivers/gpu/nvgpu/common/linux/module_usermode.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -19,9 +19,9 @@ | |||
19 | 19 | ||
20 | struct gk20a; | 20 | struct gk20a; |
21 | 21 | ||
22 | void t19x_init_support(struct gk20a *g); | 22 | void nvgpu_init_usermode_support(struct gk20a *g); |
23 | void t19x_remove_support(struct gk20a *g); | 23 | void nvgpu_remove_usermode_support(struct gk20a *g); |
24 | void t19x_lockout_registers(struct gk20a *g); | 24 | void nvgpu_lockout_usermode_registers(struct gk20a *g); |
25 | void t19x_restore_registers(struct gk20a *g); | 25 | void nvgpu_restore_usermode_registers(struct gk20a *g); |
26 | 26 | ||
27 | #endif | 27 | #endif |
diff --git a/drivers/gpu/nvgpu/common/linux/nvhost.c b/drivers/gpu/nvgpu/common/linux/nvhost.c index 511cffc4..e0f83612 100644 --- a/drivers/gpu/nvgpu/common/linux/nvhost.c +++ b/drivers/gpu/nvgpu/common/linux/nvhost.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -15,6 +15,7 @@ | |||
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/nvhost.h> | 17 | #include <linux/nvhost.h> |
18 | #include <linux/nvhost_t194.h> | ||
18 | #include <linux/nvhost_ioctl.h> | 19 | #include <linux/nvhost_ioctl.h> |
19 | #include <linux/of_platform.h> | 20 | #include <linux/of_platform.h> |
20 | 21 | ||
@@ -210,3 +211,18 @@ struct sync_fence *nvgpu_nvhost_sync_create_fence( | |||
210 | return nvhost_sync_create_fence(nvhost_dev->host1x_pdev, &pt, 1, name); | 211 | return nvhost_sync_create_fence(nvhost_dev->host1x_pdev, &pt, 1, name); |
211 | } | 212 | } |
212 | #endif /* CONFIG_SYNC */ | 213 | #endif /* CONFIG_SYNC */ |
214 | |||
215 | #ifdef CONFIG_TEGRA_T19X_GRHOST | ||
216 | int nvgpu_nvhost_syncpt_unit_interface_get_aperture( | ||
217 | struct nvgpu_nvhost_dev *nvhost_dev, | ||
218 | u64 *base, size_t *size) | ||
219 | { | ||
220 | return nvhost_syncpt_unit_interface_get_aperture( | ||
221 | nvhost_dev->host1x_pdev, (phys_addr_t *)base, size); | ||
222 | } | ||
223 | |||
224 | u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) | ||
225 | { | ||
226 | return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); | ||
227 | } | ||
228 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c b/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c deleted file mode 100644 index 21cf62ec..00000000 --- a/drivers/gpu/nvgpu/common/linux/nvhost_t19x.c +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/nvhost.h> | ||
18 | #include <linux/nvhost_t194.h> | ||
19 | |||
20 | #include <nvgpu/nvhost_t19x.h> | ||
21 | |||
22 | #include "common/linux/nvhost_priv.h" | ||
23 | |||
24 | int nvgpu_nvhost_syncpt_unit_interface_get_aperture( | ||
25 | struct nvgpu_nvhost_dev *nvhost_dev, | ||
26 | u64 *base, size_t *size) | ||
27 | { | ||
28 | return nvhost_syncpt_unit_interface_get_aperture( | ||
29 | nvhost_dev->host1x_pdev, (phys_addr_t *)base, size); | ||
30 | } | ||
31 | |||
32 | u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) | ||
33 | { | ||
34 | return nvhost_syncpt_unit_interface_get_byte_offset(syncpt_id); | ||
35 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/os_linux.h b/drivers/gpu/nvgpu/common/linux/os_linux.h index 9b95ed84..a2181c05 100644 --- a/drivers/gpu/nvgpu/common/linux/os_linux.h +++ b/drivers/gpu/nvgpu/common/linux/os_linux.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -20,9 +20,6 @@ | |||
20 | #include <linux/cdev.h> | 20 | #include <linux/cdev.h> |
21 | #include <linux/iommu.h> | 21 | #include <linux/iommu.h> |
22 | 22 | ||
23 | #ifdef CONFIG_TEGRA_19x_GPU | ||
24 | #include <nvgpu/linux/os_linux_t19x.h> | ||
25 | #endif | ||
26 | #include "gk20a/gk20a.h" | 23 | #include "gk20a/gk20a.h" |
27 | #include "cde.h" | 24 | #include "cde.h" |
28 | #include "sched.h" | 25 | #include "sched.h" |
@@ -114,9 +111,8 @@ struct nvgpu_os_linux { | |||
114 | void __iomem *bar1; | 111 | void __iomem *bar1; |
115 | void __iomem *bar1_saved; | 112 | void __iomem *bar1_saved; |
116 | 113 | ||
117 | #ifdef CONFIG_TEGRA_19x_GPU | 114 | void __iomem *usermode_regs; |
118 | struct nvgpu_os_linux_t19x t19x; | 115 | void __iomem *usermode_regs_saved; |
119 | #endif | ||
120 | 116 | ||
121 | struct nvgpu_os_linux_ops ops; | 117 | struct nvgpu_os_linux_ops ops; |
122 | 118 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/pci.c b/drivers/gpu/nvgpu/common/linux/pci.c index 7c853b14..9c18fbc9 100644 --- a/drivers/gpu/nvgpu/common/linux/pci.c +++ b/drivers/gpu/nvgpu/common/linux/pci.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -34,9 +34,7 @@ | |||
34 | #include "platform_gk20a.h" | 34 | #include "platform_gk20a.h" |
35 | 35 | ||
36 | #include "pci.h" | 36 | #include "pci.h" |
37 | #ifdef CONFIG_TEGRA_19x_GPU | 37 | #include "pci_usermode.h" |
38 | #include <nvgpu/linux/pci_t19x.h> | ||
39 | #endif | ||
40 | 38 | ||
41 | #include "os_linux.h" | 39 | #include "os_linux.h" |
42 | #include "driver_common.h" | 40 | #include "driver_common.h" |
@@ -453,9 +451,7 @@ static int nvgpu_pci_init_support(struct pci_dev *pdev) | |||
453 | goto fail; | 451 | goto fail; |
454 | } | 452 | } |
455 | 453 | ||
456 | #ifdef CONFIG_TEGRA_19x_GPU | 454 | nvgpu_pci_init_usermode_support(l); |
457 | t19x_nvgpu_pci_init_support(l); | ||
458 | #endif | ||
459 | 455 | ||
460 | return 0; | 456 | return 0; |
461 | 457 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/pci_t19x.c b/drivers/gpu/nvgpu/common/linux/pci_usermode.c index 54efd68e..f474bd10 100644 --- a/drivers/gpu/nvgpu/common/linux/pci_t19x.c +++ b/drivers/gpu/nvgpu/common/linux/pci_usermode.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -17,8 +17,8 @@ | |||
17 | 17 | ||
18 | #include "common/linux/os_linux.h" | 18 | #include "common/linux/os_linux.h" |
19 | 19 | ||
20 | void t19x_nvgpu_pci_init_support(struct nvgpu_os_linux *l) | 20 | void nvgpu_pci_init_usermode_support(struct nvgpu_os_linux *l) |
21 | { | 21 | { |
22 | l->t19x.usermode_regs = l->regs + usermode_cfg0_r(); | 22 | l->usermode_regs = l->regs + usermode_cfg0_r(); |
23 | l->t19x.usermode_regs_saved = l->t19x.usermode_regs; | 23 | l->usermode_regs_saved = l->usermode_regs; |
24 | } | 24 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h b/drivers/gpu/nvgpu/common/linux/pci_usermode.h index c94176cc..25a08d28 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/linux/pci_t19x.h +++ b/drivers/gpu/nvgpu/common/linux/pci_usermode.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -13,11 +13,11 @@ | |||
13 | * You should have received a copy of the GNU General Public License | 13 | * You should have received a copy of the GNU General Public License |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
15 | */ | 15 | */ |
16 | #ifndef __NVGPU_PCI_T19X_H__ | 16 | #ifndef __NVGPU_PCI_USERMODE_H__ |
17 | #define __NVGPU_PCI_T19X_H__ | 17 | #define __NVGPU_PCI_USERMODE_H__ |
18 | 18 | ||
19 | struct nvgpu_os_linux; | 19 | struct nvgpu_os_linux; |
20 | 20 | ||
21 | void t19x_nvgpu_pci_init_support(struct nvgpu_os_linux *l); | 21 | void nvgpu_pci_init_usermode_support(struct nvgpu_os_linux *l); |
22 | 22 | ||
23 | #endif | 23 | #endif |
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h index 37c80a70..9325eab7 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h +++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Platform (SoC) Interface | 2 | * GK20A Platform (SoC) Interface |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -250,6 +250,7 @@ static inline struct gk20a_platform *gk20a_get_platform( | |||
250 | #ifdef CONFIG_TEGRA_GK20A | 250 | #ifdef CONFIG_TEGRA_GK20A |
251 | extern struct gk20a_platform gm20b_tegra_platform; | 251 | extern struct gk20a_platform gm20b_tegra_platform; |
252 | extern struct gk20a_platform gp10b_tegra_platform; | 252 | extern struct gk20a_platform gp10b_tegra_platform; |
253 | extern struct gk20a_platform gv11b_tegra_platform; | ||
253 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | 254 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION |
254 | extern struct gk20a_platform vgpu_tegra_platform; | 255 | extern struct gk20a_platform vgpu_tegra_platform; |
255 | extern struct gk20a_platform gv11b_vgpu_tegra_platform; | 256 | extern struct gk20a_platform gv11b_vgpu_tegra_platform; |
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c index 81b6204d..aad94cd2 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gv11b_tegra.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include <linux/platform/tegra/emc_bwmgr.h> | 26 | #include <linux/platform/tegra/emc_bwmgr.h> |
27 | 27 | ||
28 | #include <nvgpu/nvhost.h> | 28 | #include <nvgpu/nvhost.h> |
29 | #include <nvgpu/nvhost_t19x.h> | ||
30 | 29 | ||
31 | #include <uapi/linux/nvgpu.h> | 30 | #include <uapi/linux/nvgpu.h> |
32 | 31 | ||
@@ -44,7 +43,6 @@ | |||
44 | #include "os_linux.h" | 43 | #include "os_linux.h" |
45 | #include "platform_gk20a_tegra.h" | 44 | #include "platform_gk20a_tegra.h" |
46 | #include "gv11b/gr_gv11b.h" | 45 | #include "gv11b/gr_gv11b.h" |
47 | #include "nvgpu_gpuid_t19x.h" | ||
48 | 46 | ||
49 | static void gr_gv11b_remove_sysfs(struct device *dev); | 47 | static void gr_gv11b_remove_sysfs(struct device *dev); |
50 | 48 | ||
@@ -203,7 +201,7 @@ static int gv11b_tegra_suspend(struct device *dev) | |||
203 | return 0; | 201 | return 0; |
204 | } | 202 | } |
205 | 203 | ||
206 | struct gk20a_platform t19x_gpu_tegra_platform = { | 204 | struct gk20a_platform gv11b_tegra_platform = { |
207 | .has_syncpoints = true, | 205 | .has_syncpoints = true, |
208 | 206 | ||
209 | /* no cde. use sysmem compression */ | 207 | /* no cde. use sysmem compression */ |
@@ -297,7 +295,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
297 | initialized multiple times but we only need to create the ECC | 295 | initialized multiple times but we only need to create the ECC |
298 | stats once. Therefore, add the following check to avoid | 296 | stats once. Therefore, add the following check to avoid |
299 | creating duplicate stat sysfs nodes. */ | 297 | creating duplicate stat sysfs nodes. */ |
300 | if (g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters != NULL) | 298 | if (g->ecc.gr.sm_l1_tag_corrected_err_count.counters != NULL) |
301 | return; | 299 | return; |
302 | 300 | ||
303 | gr_gp10b_create_sysfs(g); | 301 | gr_gp10b_create_sysfs(g); |
@@ -305,61 +303,61 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
305 | error |= gr_gp10b_ecc_stat_create(dev, | 303 | error |= gr_gp10b_ecc_stat_create(dev, |
306 | 0, | 304 | 0, |
307 | "sm_l1_tag_ecc_corrected_err_count", | 305 | "sm_l1_tag_ecc_corrected_err_count", |
308 | &g->ecc.gr.t19x.sm_l1_tag_corrected_err_count, | 306 | &g->ecc.gr.sm_l1_tag_corrected_err_count, |
309 | &dev_attr_sm_l1_tag_ecc_corrected_err_count_array); | 307 | &dev_attr_sm_l1_tag_ecc_corrected_err_count_array); |
310 | 308 | ||
311 | error |= gr_gp10b_ecc_stat_create(dev, | 309 | error |= gr_gp10b_ecc_stat_create(dev, |
312 | 0, | 310 | 0, |
313 | "sm_l1_tag_ecc_uncorrected_err_count", | 311 | "sm_l1_tag_ecc_uncorrected_err_count", |
314 | &g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count, | 312 | &g->ecc.gr.sm_l1_tag_uncorrected_err_count, |
315 | &dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); | 313 | &dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); |
316 | 314 | ||
317 | error |= gr_gp10b_ecc_stat_create(dev, | 315 | error |= gr_gp10b_ecc_stat_create(dev, |
318 | 0, | 316 | 0, |
319 | "sm_cbu_ecc_corrected_err_count", | 317 | "sm_cbu_ecc_corrected_err_count", |
320 | &g->ecc.gr.t19x.sm_cbu_corrected_err_count, | 318 | &g->ecc.gr.sm_cbu_corrected_err_count, |
321 | &dev_attr_sm_cbu_ecc_corrected_err_count_array); | 319 | &dev_attr_sm_cbu_ecc_corrected_err_count_array); |
322 | 320 | ||
323 | error |= gr_gp10b_ecc_stat_create(dev, | 321 | error |= gr_gp10b_ecc_stat_create(dev, |
324 | 0, | 322 | 0, |
325 | "sm_cbu_ecc_uncorrected_err_count", | 323 | "sm_cbu_ecc_uncorrected_err_count", |
326 | &g->ecc.gr.t19x.sm_cbu_uncorrected_err_count, | 324 | &g->ecc.gr.sm_cbu_uncorrected_err_count, |
327 | &dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | 325 | &dev_attr_sm_cbu_ecc_uncorrected_err_count_array); |
328 | 326 | ||
329 | error |= gr_gp10b_ecc_stat_create(dev, | 327 | error |= gr_gp10b_ecc_stat_create(dev, |
330 | 0, | 328 | 0, |
331 | "sm_l1_data_ecc_corrected_err_count", | 329 | "sm_l1_data_ecc_corrected_err_count", |
332 | &g->ecc.gr.t19x.sm_l1_data_corrected_err_count, | 330 | &g->ecc.gr.sm_l1_data_corrected_err_count, |
333 | &dev_attr_sm_l1_data_ecc_corrected_err_count_array); | 331 | &dev_attr_sm_l1_data_ecc_corrected_err_count_array); |
334 | 332 | ||
335 | error |= gr_gp10b_ecc_stat_create(dev, | 333 | error |= gr_gp10b_ecc_stat_create(dev, |
336 | 0, | 334 | 0, |
337 | "sm_l1_data_ecc_uncorrected_err_count", | 335 | "sm_l1_data_ecc_uncorrected_err_count", |
338 | &g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count, | 336 | &g->ecc.gr.sm_l1_data_uncorrected_err_count, |
339 | &dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); | 337 | &dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); |
340 | 338 | ||
341 | error |= gr_gp10b_ecc_stat_create(dev, | 339 | error |= gr_gp10b_ecc_stat_create(dev, |
342 | 0, | 340 | 0, |
343 | "sm_icache_ecc_corrected_err_count", | 341 | "sm_icache_ecc_corrected_err_count", |
344 | &g->ecc.gr.t19x.sm_icache_corrected_err_count, | 342 | &g->ecc.gr.sm_icache_corrected_err_count, |
345 | &dev_attr_sm_icache_ecc_corrected_err_count_array); | 343 | &dev_attr_sm_icache_ecc_corrected_err_count_array); |
346 | 344 | ||
347 | error |= gr_gp10b_ecc_stat_create(dev, | 345 | error |= gr_gp10b_ecc_stat_create(dev, |
348 | 0, | 346 | 0, |
349 | "sm_icache_ecc_uncorrected_err_count", | 347 | "sm_icache_ecc_uncorrected_err_count", |
350 | &g->ecc.gr.t19x.sm_icache_uncorrected_err_count, | 348 | &g->ecc.gr.sm_icache_uncorrected_err_count, |
351 | &dev_attr_sm_icache_ecc_uncorrected_err_count_array); | 349 | &dev_attr_sm_icache_ecc_uncorrected_err_count_array); |
352 | 350 | ||
353 | error |= gr_gp10b_ecc_stat_create(dev, | 351 | error |= gr_gp10b_ecc_stat_create(dev, |
354 | 0, | 352 | 0, |
355 | "gcc_l15_ecc_corrected_err_count", | 353 | "gcc_l15_ecc_corrected_err_count", |
356 | &g->ecc.gr.t19x.gcc_l15_corrected_err_count, | 354 | &g->ecc.gr.gcc_l15_corrected_err_count, |
357 | &dev_attr_gcc_l15_ecc_corrected_err_count_array); | 355 | &dev_attr_gcc_l15_ecc_corrected_err_count_array); |
358 | 356 | ||
359 | error |= gr_gp10b_ecc_stat_create(dev, | 357 | error |= gr_gp10b_ecc_stat_create(dev, |
360 | 0, | 358 | 0, |
361 | "gcc_l15_ecc_uncorrected_err_count", | 359 | "gcc_l15_ecc_uncorrected_err_count", |
362 | &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, | 360 | &g->ecc.gr.gcc_l15_uncorrected_err_count, |
363 | &dev_attr_gcc_l15_ecc_uncorrected_err_count_array); | 361 | &dev_attr_gcc_l15_ecc_uncorrected_err_count_array); |
364 | 362 | ||
365 | error |= gp10b_ecc_stat_create(dev, | 363 | error |= gp10b_ecc_stat_create(dev, |
@@ -368,7 +366,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
368 | "ltc", | 366 | "ltc", |
369 | NULL, | 367 | NULL, |
370 | "l2_cache_uncorrected_err_count", | 368 | "l2_cache_uncorrected_err_count", |
371 | &g->ecc.ltc.t19x.l2_cache_uncorrected_err_count, | 369 | &g->ecc.ltc.l2_cache_uncorrected_err_count, |
372 | &dev_attr_l2_cache_ecc_uncorrected_err_count_array); | 370 | &dev_attr_l2_cache_ecc_uncorrected_err_count_array); |
373 | 371 | ||
374 | error |= gp10b_ecc_stat_create(dev, | 372 | error |= gp10b_ecc_stat_create(dev, |
@@ -377,7 +375,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
377 | "ltc", | 375 | "ltc", |
378 | NULL, | 376 | NULL, |
379 | "l2_cache_corrected_err_count", | 377 | "l2_cache_corrected_err_count", |
380 | &g->ecc.ltc.t19x.l2_cache_corrected_err_count, | 378 | &g->ecc.ltc.l2_cache_corrected_err_count, |
381 | &dev_attr_l2_cache_ecc_corrected_err_count_array); | 379 | &dev_attr_l2_cache_ecc_corrected_err_count_array); |
382 | 380 | ||
383 | error |= gp10b_ecc_stat_create(dev, | 381 | error |= gp10b_ecc_stat_create(dev, |
@@ -386,7 +384,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
386 | "gpc", | 384 | "gpc", |
387 | NULL, | 385 | NULL, |
388 | "fecs_ecc_uncorrected_err_count", | 386 | "fecs_ecc_uncorrected_err_count", |
389 | &g->ecc.gr.t19x.fecs_uncorrected_err_count, | 387 | &g->ecc.gr.fecs_uncorrected_err_count, |
390 | &dev_attr_fecs_ecc_uncorrected_err_count_array); | 388 | &dev_attr_fecs_ecc_uncorrected_err_count_array); |
391 | 389 | ||
392 | error |= gp10b_ecc_stat_create(dev, | 390 | error |= gp10b_ecc_stat_create(dev, |
@@ -395,7 +393,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
395 | "gpc", | 393 | "gpc", |
396 | NULL, | 394 | NULL, |
397 | "fecs_ecc_corrected_err_count", | 395 | "fecs_ecc_corrected_err_count", |
398 | &g->ecc.gr.t19x.fecs_corrected_err_count, | 396 | &g->ecc.gr.fecs_corrected_err_count, |
399 | &dev_attr_fecs_ecc_corrected_err_count_array); | 397 | &dev_attr_fecs_ecc_corrected_err_count_array); |
400 | 398 | ||
401 | error |= gp10b_ecc_stat_create(dev, | 399 | error |= gp10b_ecc_stat_create(dev, |
@@ -404,7 +402,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
404 | "gpc", | 402 | "gpc", |
405 | NULL, | 403 | NULL, |
406 | "gpccs_ecc_uncorrected_err_count", | 404 | "gpccs_ecc_uncorrected_err_count", |
407 | &g->ecc.gr.t19x.gpccs_uncorrected_err_count, | 405 | &g->ecc.gr.gpccs_uncorrected_err_count, |
408 | &dev_attr_gpccs_ecc_uncorrected_err_count_array); | 406 | &dev_attr_gpccs_ecc_uncorrected_err_count_array); |
409 | 407 | ||
410 | error |= gp10b_ecc_stat_create(dev, | 408 | error |= gp10b_ecc_stat_create(dev, |
@@ -413,7 +411,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
413 | "gpc", | 411 | "gpc", |
414 | NULL, | 412 | NULL, |
415 | "gpccs_ecc_corrected_err_count", | 413 | "gpccs_ecc_corrected_err_count", |
416 | &g->ecc.gr.t19x.gpccs_corrected_err_count, | 414 | &g->ecc.gr.gpccs_corrected_err_count, |
417 | &dev_attr_gpccs_ecc_corrected_err_count_array); | 415 | &dev_attr_gpccs_ecc_corrected_err_count_array); |
418 | 416 | ||
419 | error |= gp10b_ecc_stat_create(dev, | 417 | error |= gp10b_ecc_stat_create(dev, |
@@ -422,7 +420,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
422 | "gpc", | 420 | "gpc", |
423 | NULL, | 421 | NULL, |
424 | "mmu_l1tlb_ecc_uncorrected_err_count", | 422 | "mmu_l1tlb_ecc_uncorrected_err_count", |
425 | &g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count, | 423 | &g->ecc.gr.mmu_l1tlb_uncorrected_err_count, |
426 | &dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); | 424 | &dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); |
427 | 425 | ||
428 | error |= gp10b_ecc_stat_create(dev, | 426 | error |= gp10b_ecc_stat_create(dev, |
@@ -431,7 +429,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
431 | "gpc", | 429 | "gpc", |
432 | NULL, | 430 | NULL, |
433 | "mmu_l1tlb_ecc_corrected_err_count", | 431 | "mmu_l1tlb_ecc_corrected_err_count", |
434 | &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, | 432 | &g->ecc.gr.mmu_l1tlb_corrected_err_count, |
435 | &dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); | 433 | &dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); |
436 | 434 | ||
437 | error |= gp10b_ecc_stat_create(dev, | 435 | error |= gp10b_ecc_stat_create(dev, |
@@ -440,7 +438,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
440 | "eng", | 438 | "eng", |
441 | NULL, | 439 | NULL, |
442 | "mmu_l2tlb_ecc_uncorrected_err_count", | 440 | "mmu_l2tlb_ecc_uncorrected_err_count", |
443 | &g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count, | 441 | &g->ecc.fb.mmu_l2tlb_uncorrected_err_count, |
444 | &dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); | 442 | &dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); |
445 | 443 | ||
446 | error |= gp10b_ecc_stat_create(dev, | 444 | error |= gp10b_ecc_stat_create(dev, |
@@ -449,7 +447,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
449 | "eng", | 447 | "eng", |
450 | NULL, | 448 | NULL, |
451 | "mmu_l2tlb_ecc_corrected_err_count", | 449 | "mmu_l2tlb_ecc_corrected_err_count", |
452 | &g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count, | 450 | &g->ecc.fb.mmu_l2tlb_corrected_err_count, |
453 | &dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); | 451 | &dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); |
454 | 452 | ||
455 | error |= gp10b_ecc_stat_create(dev, | 453 | error |= gp10b_ecc_stat_create(dev, |
@@ -458,7 +456,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
458 | "eng", | 456 | "eng", |
459 | NULL, | 457 | NULL, |
460 | "mmu_hubtlb_ecc_uncorrected_err_count", | 458 | "mmu_hubtlb_ecc_uncorrected_err_count", |
461 | &g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count, | 459 | &g->ecc.fb.mmu_hubtlb_uncorrected_err_count, |
462 | &dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); | 460 | &dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); |
463 | 461 | ||
464 | error |= gp10b_ecc_stat_create(dev, | 462 | error |= gp10b_ecc_stat_create(dev, |
@@ -467,7 +465,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
467 | "eng", | 465 | "eng", |
468 | NULL, | 466 | NULL, |
469 | "mmu_hubtlb_ecc_corrected_err_count", | 467 | "mmu_hubtlb_ecc_corrected_err_count", |
470 | &g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count, | 468 | &g->ecc.fb.mmu_hubtlb_corrected_err_count, |
471 | &dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); | 469 | &dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); |
472 | 470 | ||
473 | error |= gp10b_ecc_stat_create(dev, | 471 | error |= gp10b_ecc_stat_create(dev, |
@@ -476,7 +474,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
476 | "eng", | 474 | "eng", |
477 | NULL, | 475 | NULL, |
478 | "mmu_fillunit_ecc_uncorrected_err_count", | 476 | "mmu_fillunit_ecc_uncorrected_err_count", |
479 | &g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count, | 477 | &g->ecc.fb.mmu_fillunit_uncorrected_err_count, |
480 | &dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); | 478 | &dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); |
481 | 479 | ||
482 | error |= gp10b_ecc_stat_create(dev, | 480 | error |= gp10b_ecc_stat_create(dev, |
@@ -485,7 +483,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
485 | "eng", | 483 | "eng", |
486 | NULL, | 484 | NULL, |
487 | "mmu_fillunit_ecc_corrected_err_count", | 485 | "mmu_fillunit_ecc_corrected_err_count", |
488 | &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count, | 486 | &g->ecc.fb.mmu_fillunit_corrected_err_count, |
489 | &dev_attr_mmu_fillunit_ecc_corrected_err_count_array); | 487 | &dev_attr_mmu_fillunit_ecc_corrected_err_count_array); |
490 | 488 | ||
491 | error |= gp10b_ecc_stat_create(dev, | 489 | error |= gp10b_ecc_stat_create(dev, |
@@ -494,7 +492,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
494 | "eng", | 492 | "eng", |
495 | NULL, | 493 | NULL, |
496 | "pmu_ecc_uncorrected_err_count", | 494 | "pmu_ecc_uncorrected_err_count", |
497 | &g->ecc.eng.t19x.pmu_uncorrected_err_count, | 495 | &g->ecc.pmu.pmu_uncorrected_err_count, |
498 | &dev_attr_pmu_ecc_uncorrected_err_count_array); | 496 | &dev_attr_pmu_ecc_uncorrected_err_count_array); |
499 | 497 | ||
500 | error |= gp10b_ecc_stat_create(dev, | 498 | error |= gp10b_ecc_stat_create(dev, |
@@ -503,7 +501,7 @@ void gr_gv11b_create_sysfs(struct gk20a *g) | |||
503 | "eng", | 501 | "eng", |
504 | NULL, | 502 | NULL, |
505 | "pmu_ecc_corrected_err_count", | 503 | "pmu_ecc_corrected_err_count", |
506 | &g->ecc.eng.t19x.pmu_corrected_err_count, | 504 | &g->ecc.pmu.pmu_corrected_err_count, |
507 | &dev_attr_pmu_ecc_corrected_err_count_array); | 505 | &dev_attr_pmu_ecc_corrected_err_count_array); |
508 | 506 | ||
509 | 507 | ||
@@ -517,131 +515,131 @@ static void gr_gv11b_remove_sysfs(struct device *dev) | |||
517 | 515 | ||
518 | gr_gp10b_ecc_stat_remove(dev, | 516 | gr_gp10b_ecc_stat_remove(dev, |
519 | 0, | 517 | 0, |
520 | &g->ecc.gr.t19x.sm_l1_tag_corrected_err_count, | 518 | &g->ecc.gr.sm_l1_tag_corrected_err_count, |
521 | dev_attr_sm_l1_tag_ecc_corrected_err_count_array); | 519 | dev_attr_sm_l1_tag_ecc_corrected_err_count_array); |
522 | 520 | ||
523 | gr_gp10b_ecc_stat_remove(dev, | 521 | gr_gp10b_ecc_stat_remove(dev, |
524 | 0, | 522 | 0, |
525 | &g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count, | 523 | &g->ecc.gr.sm_l1_tag_uncorrected_err_count, |
526 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); | 524 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); |
527 | 525 | ||
528 | gr_gp10b_ecc_stat_remove(dev, | 526 | gr_gp10b_ecc_stat_remove(dev, |
529 | 0, | 527 | 0, |
530 | &g->ecc.gr.t19x.sm_cbu_corrected_err_count, | 528 | &g->ecc.gr.sm_cbu_corrected_err_count, |
531 | dev_attr_sm_cbu_ecc_corrected_err_count_array); | 529 | dev_attr_sm_cbu_ecc_corrected_err_count_array); |
532 | 530 | ||
533 | gr_gp10b_ecc_stat_remove(dev, | 531 | gr_gp10b_ecc_stat_remove(dev, |
534 | 0, | 532 | 0, |
535 | &g->ecc.gr.t19x.sm_cbu_uncorrected_err_count, | 533 | &g->ecc.gr.sm_cbu_uncorrected_err_count, |
536 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | 534 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); |
537 | 535 | ||
538 | gr_gp10b_ecc_stat_remove(dev, | 536 | gr_gp10b_ecc_stat_remove(dev, |
539 | 0, | 537 | 0, |
540 | &g->ecc.gr.t19x.sm_l1_data_corrected_err_count, | 538 | &g->ecc.gr.sm_l1_data_corrected_err_count, |
541 | dev_attr_sm_l1_data_ecc_corrected_err_count_array); | 539 | dev_attr_sm_l1_data_ecc_corrected_err_count_array); |
542 | 540 | ||
543 | gr_gp10b_ecc_stat_remove(dev, | 541 | gr_gp10b_ecc_stat_remove(dev, |
544 | 0, | 542 | 0, |
545 | &g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count, | 543 | &g->ecc.gr.sm_l1_data_uncorrected_err_count, |
546 | dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); | 544 | dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); |
547 | 545 | ||
548 | gr_gp10b_ecc_stat_remove(dev, | 546 | gr_gp10b_ecc_stat_remove(dev, |
549 | 0, | 547 | 0, |
550 | &g->ecc.gr.t19x.sm_icache_corrected_err_count, | 548 | &g->ecc.gr.sm_icache_corrected_err_count, |
551 | dev_attr_sm_icache_ecc_corrected_err_count_array); | 549 | dev_attr_sm_icache_ecc_corrected_err_count_array); |
552 | 550 | ||
553 | gr_gp10b_ecc_stat_remove(dev, | 551 | gr_gp10b_ecc_stat_remove(dev, |
554 | 0, | 552 | 0, |
555 | &g->ecc.gr.t19x.sm_icache_uncorrected_err_count, | 553 | &g->ecc.gr.sm_icache_uncorrected_err_count, |
556 | dev_attr_sm_icache_ecc_uncorrected_err_count_array); | 554 | dev_attr_sm_icache_ecc_uncorrected_err_count_array); |
557 | 555 | ||
558 | gr_gp10b_ecc_stat_remove(dev, | 556 | gr_gp10b_ecc_stat_remove(dev, |
559 | 0, | 557 | 0, |
560 | &g->ecc.gr.t19x.gcc_l15_corrected_err_count, | 558 | &g->ecc.gr.gcc_l15_corrected_err_count, |
561 | dev_attr_gcc_l15_ecc_corrected_err_count_array); | 559 | dev_attr_gcc_l15_ecc_corrected_err_count_array); |
562 | 560 | ||
563 | gr_gp10b_ecc_stat_remove(dev, | 561 | gr_gp10b_ecc_stat_remove(dev, |
564 | 0, | 562 | 0, |
565 | &g->ecc.gr.t19x.gcc_l15_uncorrected_err_count, | 563 | &g->ecc.gr.gcc_l15_uncorrected_err_count, |
566 | dev_attr_gcc_l15_ecc_uncorrected_err_count_array); | 564 | dev_attr_gcc_l15_ecc_uncorrected_err_count_array); |
567 | 565 | ||
568 | gp10b_ecc_stat_remove(dev, | 566 | gp10b_ecc_stat_remove(dev, |
569 | g->ltc_count, | 567 | g->ltc_count, |
570 | &g->ecc.ltc.t19x.l2_cache_uncorrected_err_count, | 568 | &g->ecc.ltc.l2_cache_uncorrected_err_count, |
571 | dev_attr_l2_cache_ecc_uncorrected_err_count_array); | 569 | dev_attr_l2_cache_ecc_uncorrected_err_count_array); |
572 | 570 | ||
573 | gp10b_ecc_stat_remove(dev, | 571 | gp10b_ecc_stat_remove(dev, |
574 | g->ltc_count, | 572 | g->ltc_count, |
575 | &g->ecc.ltc.t19x.l2_cache_corrected_err_count, | 573 | &g->ecc.ltc.l2_cache_corrected_err_count, |
576 | dev_attr_l2_cache_ecc_corrected_err_count_array); | 574 | dev_attr_l2_cache_ecc_corrected_err_count_array); |
577 | 575 | ||
578 | gp10b_ecc_stat_remove(dev, | 576 | gp10b_ecc_stat_remove(dev, |
579 | 1, | 577 | 1, |
580 | &g->ecc.gr.t19x.fecs_uncorrected_err_count, | 578 | &g->ecc.gr.fecs_uncorrected_err_count, |
581 | dev_attr_fecs_ecc_uncorrected_err_count_array); | 579 | dev_attr_fecs_ecc_uncorrected_err_count_array); |
582 | 580 | ||
583 | gp10b_ecc_stat_remove(dev, | 581 | gp10b_ecc_stat_remove(dev, |
584 | 1, | 582 | 1, |
585 | &g->ecc.gr.t19x.fecs_corrected_err_count, | 583 | &g->ecc.gr.fecs_corrected_err_count, |
586 | dev_attr_fecs_ecc_corrected_err_count_array); | 584 | dev_attr_fecs_ecc_corrected_err_count_array); |
587 | 585 | ||
588 | gp10b_ecc_stat_remove(dev, | 586 | gp10b_ecc_stat_remove(dev, |
589 | g->gr.gpc_count, | 587 | g->gr.gpc_count, |
590 | &g->ecc.gr.t19x.gpccs_uncorrected_err_count, | 588 | &g->ecc.gr.gpccs_uncorrected_err_count, |
591 | dev_attr_gpccs_ecc_uncorrected_err_count_array); | 589 | dev_attr_gpccs_ecc_uncorrected_err_count_array); |
592 | 590 | ||
593 | gp10b_ecc_stat_remove(dev, | 591 | gp10b_ecc_stat_remove(dev, |
594 | g->gr.gpc_count, | 592 | g->gr.gpc_count, |
595 | &g->ecc.gr.t19x.gpccs_corrected_err_count, | 593 | &g->ecc.gr.gpccs_corrected_err_count, |
596 | dev_attr_gpccs_ecc_corrected_err_count_array); | 594 | dev_attr_gpccs_ecc_corrected_err_count_array); |
597 | 595 | ||
598 | gp10b_ecc_stat_remove(dev, | 596 | gp10b_ecc_stat_remove(dev, |
599 | g->gr.gpc_count, | 597 | g->gr.gpc_count, |
600 | &g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count, | 598 | &g->ecc.gr.mmu_l1tlb_uncorrected_err_count, |
601 | dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); | 599 | dev_attr_mmu_l1tlb_ecc_uncorrected_err_count_array); |
602 | 600 | ||
603 | gp10b_ecc_stat_remove(dev, | 601 | gp10b_ecc_stat_remove(dev, |
604 | g->gr.gpc_count, | 602 | g->gr.gpc_count, |
605 | &g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count, | 603 | &g->ecc.gr.mmu_l1tlb_corrected_err_count, |
606 | dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); | 604 | dev_attr_mmu_l1tlb_ecc_corrected_err_count_array); |
607 | 605 | ||
608 | gp10b_ecc_stat_remove(dev, | 606 | gp10b_ecc_stat_remove(dev, |
609 | 1, | 607 | 1, |
610 | &g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count, | 608 | &g->ecc.fb.mmu_l2tlb_uncorrected_err_count, |
611 | dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); | 609 | dev_attr_mmu_l2tlb_ecc_uncorrected_err_count_array); |
612 | 610 | ||
613 | gp10b_ecc_stat_remove(dev, | 611 | gp10b_ecc_stat_remove(dev, |
614 | 1, | 612 | 1, |
615 | &g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count, | 613 | &g->ecc.fb.mmu_l2tlb_corrected_err_count, |
616 | dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); | 614 | dev_attr_mmu_l2tlb_ecc_corrected_err_count_array); |
617 | 615 | ||
618 | gp10b_ecc_stat_remove(dev, | 616 | gp10b_ecc_stat_remove(dev, |
619 | 1, | 617 | 1, |
620 | &g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count, | 618 | &g->ecc.fb.mmu_hubtlb_uncorrected_err_count, |
621 | dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); | 619 | dev_attr_mmu_hubtlb_ecc_uncorrected_err_count_array); |
622 | 620 | ||
623 | gp10b_ecc_stat_remove(dev, | 621 | gp10b_ecc_stat_remove(dev, |
624 | 1, | 622 | 1, |
625 | &g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count, | 623 | &g->ecc.fb.mmu_hubtlb_corrected_err_count, |
626 | dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); | 624 | dev_attr_mmu_hubtlb_ecc_corrected_err_count_array); |
627 | 625 | ||
628 | gp10b_ecc_stat_remove(dev, | 626 | gp10b_ecc_stat_remove(dev, |
629 | 1, | 627 | 1, |
630 | &g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count, | 628 | &g->ecc.fb.mmu_fillunit_uncorrected_err_count, |
631 | dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); | 629 | dev_attr_mmu_fillunit_ecc_uncorrected_err_count_array); |
632 | 630 | ||
633 | gp10b_ecc_stat_remove(dev, | 631 | gp10b_ecc_stat_remove(dev, |
634 | 1, | 632 | 1, |
635 | &g->ecc.eng.t19x.mmu_fillunit_corrected_err_count, | 633 | &g->ecc.fb.mmu_fillunit_corrected_err_count, |
636 | dev_attr_mmu_fillunit_ecc_corrected_err_count_array); | 634 | dev_attr_mmu_fillunit_ecc_corrected_err_count_array); |
637 | 635 | ||
638 | gp10b_ecc_stat_remove(dev, | 636 | gp10b_ecc_stat_remove(dev, |
639 | 1, | 637 | 1, |
640 | &g->ecc.eng.t19x.pmu_uncorrected_err_count, | 638 | &g->ecc.pmu.pmu_uncorrected_err_count, |
641 | dev_attr_pmu_ecc_uncorrected_err_count_array); | 639 | dev_attr_pmu_ecc_uncorrected_err_count_array); |
642 | 640 | ||
643 | gp10b_ecc_stat_remove(dev, | 641 | gp10b_ecc_stat_remove(dev, |
644 | 1, | 642 | 1, |
645 | &g->ecc.eng.t19x.pmu_corrected_err_count, | 643 | &g->ecc.pmu.pmu_corrected_err_count, |
646 | dev_attr_pmu_ecc_corrected_err_count_array); | 644 | dev_attr_pmu_ecc_corrected_err_count_array); |
647 | } | 645 | } |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c index d343da03..5e880261 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_mm_gp10b.c | |||
@@ -169,10 +169,8 @@ u64 vgpu_gp10b_locked_gmmu_map(struct vm_gk20a *vm, | |||
169 | p->flags = TEGRA_VGPU_MAP_CACHEABLE; | 169 | p->flags = TEGRA_VGPU_MAP_CACHEABLE; |
170 | if (flags & NVGPU_VM_MAP_IO_COHERENT) | 170 | if (flags & NVGPU_VM_MAP_IO_COHERENT) |
171 | p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; | 171 | p->flags |= TEGRA_VGPU_MAP_IO_COHERENT; |
172 | #ifdef CONFIG_TEGRA_19x_GPU | ||
173 | if (flags & NVGPU_VM_MAP_L3_ALLOC) | 172 | if (flags & NVGPU_VM_MAP_L3_ALLOC) |
174 | p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; | 173 | p->flags |= TEGRA_VGPU_MAP_L3_ALLOC; |
175 | #endif | ||
176 | p->prot = prot; | 174 | p->prot = prot; |
177 | p->ctag_offset = ctag_offset; | 175 | p->ctag_offset = ctag_offset; |
178 | p->clear_ctags = clear_ctags; | 176 | p->clear_ctags = clear_ctags; |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c index 3b9d63e8..4d796f67 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/platform_gv11b_vgpu_tegra.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -20,7 +20,6 @@ | |||
20 | #include "common/linux/os_linux.h" | 20 | #include "common/linux/os_linux.h" |
21 | 21 | ||
22 | #include <nvgpu/nvhost.h> | 22 | #include <nvgpu/nvhost.h> |
23 | #include <nvgpu/nvhost_t19x.h> | ||
24 | 23 | ||
25 | #include <linux/platform_device.h> | 24 | #include <linux/platform_device.h> |
26 | 25 | ||
@@ -44,12 +43,12 @@ static int gv11b_vgpu_probe(struct device *dev) | |||
44 | dev_err(dev, "failed to map usermode regs\n"); | 43 | dev_err(dev, "failed to map usermode regs\n"); |
45 | return PTR_ERR(regs); | 44 | return PTR_ERR(regs); |
46 | } | 45 | } |
47 | l->t19x.usermode_regs = regs; | 46 | l->usermode_regs = regs; |
48 | 47 | ||
49 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 48 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
50 | ret = nvgpu_get_nvhost_dev(g); | 49 | ret = nvgpu_get_nvhost_dev(g); |
51 | if (ret) { | 50 | if (ret) { |
52 | l->t19x.usermode_regs = NULL; | 51 | l->usermode_regs = NULL; |
53 | return ret; | 52 | return ret; |
54 | } | 53 | } |
55 | 54 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c index 475036ee..134ca67a 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_fifo_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -18,7 +18,7 @@ | |||
18 | 18 | ||
19 | #include "common/linux/vgpu/vgpu.h" | 19 | #include "common/linux/vgpu/vgpu.h" |
20 | #include "gv11b/fifo_gv11b.h" | 20 | #include "gv11b/fifo_gv11b.h" |
21 | #include <nvgpu/nvhost_t19x.h> | 21 | #include <nvgpu/nvhost.h> |
22 | 22 | ||
23 | #include <linux/tegra_vgpu.h> | 23 | #include <linux/tegra_vgpu.h> |
24 | 24 | ||
@@ -99,7 +99,7 @@ int vgpu_gv11b_init_fifo_setup_hw(struct gk20a *g) | |||
99 | struct fifo_gk20a *f = &g->fifo; | 99 | struct fifo_gk20a *f = &g->fifo; |
100 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); | 100 | struct vgpu_priv_data *priv = vgpu_get_priv_data(g); |
101 | 101 | ||
102 | f->t19x.max_subctx_count = priv->constants.max_subctx_count; | 102 | f->max_subctx_count = priv->constants.max_subctx_count; |
103 | 103 | ||
104 | return 0; | 104 | return 0; |
105 | } | 105 | } |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c index 93e26541..749e9e81 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -17,7 +17,6 @@ | |||
17 | #include "gk20a/gk20a.h" | 17 | #include "gk20a/gk20a.h" |
18 | 18 | ||
19 | #include <nvgpu/enabled.h> | 19 | #include <nvgpu/enabled.h> |
20 | #include <nvgpu/enabled_t19x.h> | ||
21 | 20 | ||
22 | #include "common/linux/vgpu/vgpu.h" | 21 | #include "common/linux/vgpu/vgpu.h" |
23 | #include "vgpu_gv11b.h" | 22 | #include "vgpu_gv11b.h" |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index d205f039..88d6bde0 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -68,8 +68,7 @@ | |||
68 | #include <gv11b/gr_ctx_gv11b.h> | 68 | #include <gv11b/gr_ctx_gv11b.h> |
69 | #include <gv11b/ltc_gv11b.h> | 69 | #include <gv11b/ltc_gv11b.h> |
70 | #include <gv11b/gv11b_gating_reglist.h> | 70 | #include <gv11b/gv11b_gating_reglist.h> |
71 | 71 | #include <gv11b/gr_gv11b.h> | |
72 | #include <gv100/gr_gv100.h> | ||
73 | 72 | ||
74 | #include <nvgpu/enabled.h> | 73 | #include <nvgpu/enabled.h> |
75 | 74 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c index c2e01218..8b060b24 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_tsg_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -38,8 +38,8 @@ int vgpu_gv11b_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
38 | msg.handle = vgpu_get_handle(tsg->g); | 38 | msg.handle = vgpu_get_handle(tsg->g); |
39 | p->tsg_id = tsg->tsgid; | 39 | p->tsg_id = tsg->tsgid; |
40 | p->ch_handle = ch->virt_ctx; | 40 | p->ch_handle = ch->virt_ctx; |
41 | p->subctx_id = ch->t19x.subctx_id; | 41 | p->subctx_id = ch->subctx_id; |
42 | p->runqueue_sel = ch->t19x.runqueue_sel; | 42 | p->runqueue_sel = ch->runqueue_sel; |
43 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 43 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
44 | err = err ? err : msg.ret; | 44 | err = err ? err : msg.ret; |
45 | if (err) { | 45 | if (err) { |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c index d0c9e66d..cdf3ef1c 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU | 2 | * Virtualized GPU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -47,10 +47,6 @@ | |||
47 | #include "common/linux/scale.h" | 47 | #include "common/linux/scale.h" |
48 | #include "common/linux/driver_common.h" | 48 | #include "common/linux/driver_common.h" |
49 | 49 | ||
50 | #ifdef CONFIG_TEGRA_19x_GPU | ||
51 | #include <nvgpu_gpuid_t19x.h> | ||
52 | #endif | ||
53 | |||
54 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 50 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
55 | 51 | ||
56 | static inline int vgpu_comm_init(struct platform_device *pdev) | 52 | static inline int vgpu_comm_init(struct platform_device *pdev) |
@@ -436,11 +432,9 @@ static int vgpu_init_hal(struct gk20a *g) | |||
436 | gk20a_dbg_info("gp10b detected"); | 432 | gk20a_dbg_info("gp10b detected"); |
437 | err = vgpu_gp10b_init_hal(g); | 433 | err = vgpu_gp10b_init_hal(g); |
438 | break; | 434 | break; |
439 | #ifdef CONFIG_TEGRA_19x_GPU | 435 | case NVGPU_GPUID_GV11B: |
440 | case TEGRA_19x_GPUID: | ||
441 | err = vgpu_gv11b_init_hal(g); | 436 | err = vgpu_gv11b_init_hal(g); |
442 | break; | 437 | break; |
443 | #endif | ||
444 | default: | 438 | default: |
445 | nvgpu_err(g, "no support for %x", ver); | 439 | nvgpu_err(g, "no support for %x", ver); |
446 | err = -ENODEV; | 440 | err = -ENODEV; |
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu.c b/drivers/gpu/nvgpu/common/mm/gmmu.c index 1455822c..53ec3029 100644 --- a/drivers/gpu/nvgpu/common/mm/gmmu.c +++ b/drivers/gpu/nvgpu/common/mm/gmmu.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -700,9 +700,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, | |||
700 | if (attrs.ctag) | 700 | if (attrs.ctag) |
701 | attrs.ctag += buffer_offset & (ctag_granularity - 1U); | 701 | attrs.ctag += buffer_offset & (ctag_granularity - 1U); |
702 | 702 | ||
703 | #ifdef CONFIG_TEGRA_19x_GPU | 703 | attrs.l3_alloc = (bool)(flags & NVGPU_VM_MAP_L3_ALLOC); |
704 | nvgpu_gmmu_add_t19x_attrs(&attrs, flags); | ||
705 | #endif | ||
706 | 704 | ||
707 | /* | 705 | /* |
708 | * Only allocate a new GPU VA range if we haven't already been passed a | 706 | * Only allocate a new GPU VA range if we haven't already been passed a |
diff --git a/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c b/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c deleted file mode 100644 index f2386b3f..00000000 --- a/drivers/gpu/nvgpu/common/mm/gmmu_t19x.c +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/gmmu.h> | ||
24 | #include <nvgpu/vm.h> | ||
25 | |||
26 | void nvgpu_gmmu_add_t19x_attrs(struct nvgpu_gmmu_attrs *attrs, u32 flags) | ||
27 | { | ||
28 | attrs->t19x_attrs.l3_alloc = (bool)(flags & NVGPU_VM_MAP_L3_ALLOC); | ||
29 | } | ||
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c index 19cc9fc5..f2d04dab 100644 --- a/drivers/gpu/nvgpu/common/mm/vm.c +++ b/drivers/gpu/nvgpu/common/mm/vm.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -577,11 +577,9 @@ static void __nvgpu_vm_remove(struct vm_gk20a *vm) | |||
577 | } | 577 | } |
578 | } | 578 | } |
579 | 579 | ||
580 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU) | ||
581 | if (nvgpu_mem_is_valid(&g->syncpt_mem) && vm->syncpt_ro_map_gpu_va) | 580 | if (nvgpu_mem_is_valid(&g->syncpt_mem) && vm->syncpt_ro_map_gpu_va) |
582 | nvgpu_gmmu_unmap(vm, &g->syncpt_mem, | 581 | nvgpu_gmmu_unmap(vm, &g->syncpt_mem, |
583 | vm->syncpt_ro_map_gpu_va); | 582 | vm->syncpt_ro_map_gpu_va); |
584 | #endif | ||
585 | 583 | ||
586 | nvgpu_mutex_acquire(&vm->update_gmmu_lock); | 584 | nvgpu_mutex_acquire(&vm->update_gmmu_lock); |
587 | 585 | ||
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 25d81b60..964b1488 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,10 +28,6 @@ | |||
28 | 28 | ||
29 | #include "gk20a/gk20a.h" | 29 | #include "gk20a/gk20a.h" |
30 | 30 | ||
31 | #ifdef CONFIG_TEGRA_19x_GPU | ||
32 | #include "nvgpu_gpuid_t19x.h" | ||
33 | #endif | ||
34 | |||
35 | static u8 get_perfmon_id(struct nvgpu_pmu *pmu) | 31 | static u8 get_perfmon_id(struct nvgpu_pmu *pmu) |
36 | { | 32 | { |
37 | struct gk20a *g = gk20a_from_pmu(pmu); | 33 | struct gk20a *g = gk20a_from_pmu(pmu); |
@@ -49,11 +45,9 @@ static u8 get_perfmon_id(struct nvgpu_pmu *pmu) | |||
49 | case NVGPU_GPUID_GP106: | 45 | case NVGPU_GPUID_GP106: |
50 | unit_id = PMU_UNIT_PERFMON_T18X; | 46 | unit_id = PMU_UNIT_PERFMON_T18X; |
51 | break; | 47 | break; |
52 | #if defined(CONFIG_TEGRA_19x_GPU) | 48 | case NVGPU_GPUID_GV11B: |
53 | case TEGRA_19x_GPUID: | ||
54 | unit_id = PMU_UNIT_PERFMON_T18X; | 49 | unit_id = PMU_UNIT_PERFMON_T18X; |
55 | break; | 50 | break; |
56 | #endif | ||
57 | default: | 51 | default: |
58 | unit_id = PMU_UNIT_INVALID; | 52 | unit_id = PMU_UNIT_INVALID; |
59 | nvgpu_err(g, "no support for %x", ver); | 53 | nvgpu_err(g, "no support for %x", ver); |
diff --git a/drivers/gpu/nvgpu/ecc_t19x.h b/drivers/gpu/nvgpu/ecc_t19x.h deleted file mode 100644 index 5b571ce1..00000000 --- a/drivers/gpu/nvgpu/ecc_t19x.h +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * NVIDIA T19x ECC | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef _NVGPU_ECC_T19X_H_ | ||
25 | #define _NVGPU_ECC_T19X_H_ | ||
26 | |||
27 | #include "gv11b/ecc_gv11b.h" | ||
28 | |||
29 | #endif | ||
diff --git a/drivers/gpu/nvgpu/fifo_t19x.h b/drivers/gpu/nvgpu/fifo_t19x.h deleted file mode 100644 index 7274d1fe..00000000 --- a/drivers/gpu/nvgpu/fifo_t19x.h +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef _FIFO_T19X_H_ | ||
24 | #define _FIFO_T19X_H_ | ||
25 | |||
26 | struct fifo_t19x { | ||
27 | u32 max_subctx_count; | ||
28 | }; | ||
29 | |||
30 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 371793ef..2949c426 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics channel | 2 | * GK20A Graphics channel |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -700,10 +700,8 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, | |||
700 | ch->has_timedout = false; | 700 | ch->has_timedout = false; |
701 | ch->wdt_enabled = true; | 701 | ch->wdt_enabled = true; |
702 | ch->obj_class = 0; | 702 | ch->obj_class = 0; |
703 | #ifdef CONFIG_TEGRA_19x_GPU | 703 | ch->subctx_id = 0; |
704 | memset(&ch->t19x, 0, sizeof(struct channel_t19x)); | 704 | ch->runqueue_sel = 0; |
705 | #endif | ||
706 | |||
707 | 705 | ||
708 | /* The channel is *not* runnable at this point. It still needs to have | 706 | /* The channel is *not* runnable at this point. It still needs to have |
709 | * an address space bound and allocate a gpfifo and grctx. */ | 707 | * an address space bound and allocate a gpfifo and grctx. */ |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 29fa302f..db1404a3 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A graphics channel | 2 | * GK20A graphics channel |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -40,9 +40,6 @@ struct fifo_profile_gk20a; | |||
40 | #include "mm_gk20a.h" | 40 | #include "mm_gk20a.h" |
41 | #include "gr_gk20a.h" | 41 | #include "gr_gk20a.h" |
42 | #include "fence_gk20a.h" | 42 | #include "fence_gk20a.h" |
43 | #ifdef CONFIG_TEGRA_19x_GPU | ||
44 | #include "channel_t19x.h" | ||
45 | #endif | ||
46 | 43 | ||
47 | /* Flags to be passed to gk20a_channel_alloc_gpfifo() */ | 44 | /* Flags to be passed to gk20a_channel_alloc_gpfifo() */ |
48 | #define NVGPU_GPFIFO_FLAGS_SUPPORT_VPR (1 << 0) | 45 | #define NVGPU_GPFIFO_FLAGS_SUPPORT_VPR (1 << 0) |
@@ -237,9 +234,8 @@ struct channel_gk20a { | |||
237 | u32 runlist_id; | 234 | u32 runlist_id; |
238 | 235 | ||
239 | bool is_privileged_channel; | 236 | bool is_privileged_channel; |
240 | #ifdef CONFIG_TEGRA_19x_GPU | 237 | u32 subctx_id; |
241 | struct channel_t19x t19x; | 238 | u32 runqueue_sel; |
242 | #endif | ||
243 | 239 | ||
244 | struct ctx_header_desc ctx_header; | 240 | struct ctx_header_desc ctx_header; |
245 | 241 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h index 57eec1e0..fba8ba7d 100644 --- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A ECC | 2 | * GK20A ECC |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -33,10 +33,6 @@ struct gk20a_ecc_stat { | |||
33 | #endif | 33 | #endif |
34 | }; | 34 | }; |
35 | 35 | ||
36 | #ifdef CONFIG_TEGRA_19x_GPU | ||
37 | #include "ecc_t19x.h" | ||
38 | #endif | ||
39 | |||
40 | struct ecc_gk20a { | 36 | struct ecc_gk20a { |
41 | /* Stats per engine */ | 37 | /* Stats per engine */ |
42 | struct { | 38 | struct { |
@@ -56,24 +52,44 @@ struct ecc_gk20a { | |||
56 | struct gk20a_ecc_stat tex_unique_sec_pipe1_count; | 52 | struct gk20a_ecc_stat tex_unique_sec_pipe1_count; |
57 | struct gk20a_ecc_stat tex_unique_ded_pipe1_count; | 53 | struct gk20a_ecc_stat tex_unique_ded_pipe1_count; |
58 | 54 | ||
59 | #ifdef CONFIG_TEGRA_19x_GPU | 55 | struct gk20a_ecc_stat sm_l1_tag_corrected_err_count; |
60 | struct ecc_gr_t19x t19x; | 56 | struct gk20a_ecc_stat sm_l1_tag_uncorrected_err_count; |
61 | #endif | 57 | struct gk20a_ecc_stat sm_cbu_corrected_err_count; |
58 | struct gk20a_ecc_stat sm_cbu_uncorrected_err_count; | ||
59 | struct gk20a_ecc_stat sm_l1_data_corrected_err_count; | ||
60 | struct gk20a_ecc_stat sm_l1_data_uncorrected_err_count; | ||
61 | struct gk20a_ecc_stat sm_icache_corrected_err_count; | ||
62 | struct gk20a_ecc_stat sm_icache_uncorrected_err_count; | ||
63 | struct gk20a_ecc_stat gcc_l15_corrected_err_count; | ||
64 | struct gk20a_ecc_stat gcc_l15_uncorrected_err_count; | ||
65 | struct gk20a_ecc_stat fecs_corrected_err_count; | ||
66 | struct gk20a_ecc_stat fecs_uncorrected_err_count; | ||
67 | struct gk20a_ecc_stat gpccs_corrected_err_count; | ||
68 | struct gk20a_ecc_stat gpccs_uncorrected_err_count; | ||
69 | struct gk20a_ecc_stat mmu_l1tlb_corrected_err_count; | ||
70 | struct gk20a_ecc_stat mmu_l1tlb_uncorrected_err_count; | ||
62 | } gr; | 71 | } gr; |
63 | 72 | ||
64 | struct { | 73 | struct { |
65 | struct gk20a_ecc_stat l2_sec_count; | 74 | struct gk20a_ecc_stat l2_sec_count; |
66 | struct gk20a_ecc_stat l2_ded_count; | 75 | struct gk20a_ecc_stat l2_ded_count; |
67 | #ifdef CONFIG_TEGRA_19x_GPU | 76 | struct gk20a_ecc_stat l2_cache_corrected_err_count; |
68 | struct ecc_ltc_t19x t19x; | 77 | struct gk20a_ecc_stat l2_cache_uncorrected_err_count; |
69 | #endif | ||
70 | } ltc; | 78 | } ltc; |
71 | 79 | ||
72 | struct { | 80 | struct { |
73 | #ifdef CONFIG_TEGRA_19x_GPU | 81 | struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count; |
74 | struct ecc_eng_t19x t19x; | 82 | struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count; |
75 | #endif | 83 | struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count; |
76 | } eng; | 84 | struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count; |
85 | struct gk20a_ecc_stat mmu_fillunit_corrected_err_count; | ||
86 | struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count; | ||
87 | } fb; | ||
88 | |||
89 | struct { | ||
90 | struct gk20a_ecc_stat pmu_corrected_err_count; | ||
91 | struct gk20a_ecc_stat pmu_uncorrected_err_count; | ||
92 | } pmu; | ||
77 | 93 | ||
78 | }; | 94 | }; |
79 | 95 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index af0630d2..a925b1e2 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -1,9 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * drivers/video/tegra/host/gk20a/fifo_gk20a.h | ||
3 | * | ||
4 | * GK20A graphics fifo (gr host) | 2 | * GK20A graphics fifo (gr host) |
5 | * | 3 | * |
6 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
7 | * | 5 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -29,10 +27,6 @@ | |||
29 | #include "channel_gk20a.h" | 27 | #include "channel_gk20a.h" |
30 | #include "tsg_gk20a.h" | 28 | #include "tsg_gk20a.h" |
31 | 29 | ||
32 | #ifdef CONFIG_TEGRA_19x_GPU | ||
33 | #include "fifo_t19x.h" | ||
34 | #endif | ||
35 | |||
36 | #include <nvgpu/kref.h> | 30 | #include <nvgpu/kref.h> |
37 | 31 | ||
38 | struct gk20a_debug_output; | 32 | struct gk20a_debug_output; |
@@ -213,9 +207,7 @@ struct fifo_gk20a { | |||
213 | bool deferred_reset_pending; | 207 | bool deferred_reset_pending; |
214 | struct nvgpu_mutex deferred_reset_mutex; | 208 | struct nvgpu_mutex deferred_reset_mutex; |
215 | 209 | ||
216 | #ifdef CONFIG_TEGRA_19x_GPU | 210 | u32 max_subctx_count; |
217 | struct fifo_t19x t19x; | ||
218 | #endif | ||
219 | u32 channel_base; | 211 | u32 channel_base; |
220 | }; | 212 | }; |
221 | 213 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index c967b69b..b4886e31 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics | 2 | * GK20A Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -48,10 +48,6 @@ | |||
48 | #include "bus_gk20a.h" | 48 | #include "bus_gk20a.h" |
49 | #include "pstate/pstate.h" | 49 | #include "pstate/pstate.h" |
50 | 50 | ||
51 | #ifdef CONFIG_TEGRA_19x_GPU | ||
52 | #include "nvgpu_gpuid_t19x.h" | ||
53 | #endif | ||
54 | |||
55 | void __nvgpu_check_gpu_state(struct gk20a *g) | 51 | void __nvgpu_check_gpu_state(struct gk20a *g) |
56 | { | 52 | { |
57 | u32 boot_0 = 0xffffffff; | 53 | u32 boot_0 = 0xffffffff; |
@@ -127,7 +123,7 @@ int gk20a_prepare_poweroff(struct gk20a *g) | |||
127 | int gk20a_finalize_poweron(struct gk20a *g) | 123 | int gk20a_finalize_poweron(struct gk20a *g) |
128 | { | 124 | { |
129 | int err; | 125 | int err; |
130 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU) | 126 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) |
131 | u32 nr_pages; | 127 | u32 nr_pages; |
132 | #endif | 128 | #endif |
133 | 129 | ||
@@ -319,7 +315,7 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
319 | } | 315 | } |
320 | } | 316 | } |
321 | 317 | ||
322 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU) | 318 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) |
323 | if (gk20a_platform_has_syncpoints(g) && g->syncpt_unit_size) { | 319 | if (gk20a_platform_has_syncpoints(g) && g->syncpt_unit_size) { |
324 | if (!nvgpu_mem_is_valid(&g->syncpt_mem)) { | 320 | if (!nvgpu_mem_is_valid(&g->syncpt_mem)) { |
325 | nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE); | 321 | nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 50f827a9..cc62865c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1342,7 +1342,7 @@ struct gk20a { | |||
1342 | 1342 | ||
1343 | u64 dma_memory_used; | 1343 | u64 dma_memory_used; |
1344 | 1344 | ||
1345 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU) | 1345 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) |
1346 | u64 syncpt_unit_base; | 1346 | u64 syncpt_unit_base; |
1347 | size_t syncpt_unit_size; | 1347 | size_t syncpt_unit_size; |
1348 | u32 syncpt_size; | 1348 | u32 syncpt_size; |
@@ -1479,6 +1479,8 @@ int gk20a_wait_for_idle(struct gk20a *g); | |||
1479 | #define NVGPU_GPUID_GP10B 0x0000013B | 1479 | #define NVGPU_GPUID_GP10B 0x0000013B |
1480 | #define NVGPU_GPUID_GP104 0x00000134 | 1480 | #define NVGPU_GPUID_GP104 0x00000134 |
1481 | #define NVGPU_GPUID_GP106 0x00000136 | 1481 | #define NVGPU_GPUID_GP106 0x00000136 |
1482 | #define NVGPU_GPUID_GV11B 0x0000015B | ||
1483 | #define NVGPU_GPUID_GV100 0x00000140 | ||
1482 | 1484 | ||
1483 | int gk20a_init_gpu_characteristics(struct gk20a *g); | 1485 | int gk20a_init_gpu_characteristics(struct gk20a *g); |
1484 | 1486 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 6cc15c94..d1c32c03 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -24,10 +24,6 @@ | |||
24 | #ifndef GR_GK20A_H | 24 | #ifndef GR_GK20A_H |
25 | #define GR_GK20A_H | 25 | #define GR_GK20A_H |
26 | 26 | ||
27 | #ifdef CONFIG_TEGRA_19x_GPU | ||
28 | #include "gr_t19x.h" | ||
29 | #endif | ||
30 | |||
31 | #include "gr_ctx_gk20a.h" | 27 | #include "gr_ctx_gk20a.h" |
32 | #include "mm_gk20a.h" | 28 | #include "mm_gk20a.h" |
33 | 29 | ||
@@ -199,6 +195,12 @@ struct zbc_depth_table { | |||
199 | u32 ref_cnt; | 195 | u32 ref_cnt; |
200 | }; | 196 | }; |
201 | 197 | ||
198 | struct zbc_s_table { | ||
199 | u32 stencil; | ||
200 | u32 format; | ||
201 | u32 ref_cnt; | ||
202 | }; | ||
203 | |||
202 | struct zbc_entry { | 204 | struct zbc_entry { |
203 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; | 205 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; |
204 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; | 206 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; |
@@ -393,20 +395,14 @@ struct gr_gk20a { | |||
393 | struct nvgpu_mutex zbc_lock; | 395 | struct nvgpu_mutex zbc_lock; |
394 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; | 396 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; |
395 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; | 397 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; |
396 | #ifdef CONFIG_TEGRA_19x_GPU | ||
397 | struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; | 398 | struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; |
398 | #endif | ||
399 | s32 max_default_color_index; | 399 | s32 max_default_color_index; |
400 | s32 max_default_depth_index; | 400 | s32 max_default_depth_index; |
401 | #ifdef CONFIG_TEGRA_19x_GPU | ||
402 | s32 max_default_s_index; | 401 | s32 max_default_s_index; |
403 | #endif | ||
404 | 402 | ||
405 | u32 max_used_color_index; | 403 | u32 max_used_color_index; |
406 | u32 max_used_depth_index; | 404 | u32 max_used_depth_index; |
407 | #ifdef CONFIG_TEGRA_19x_GPU | ||
408 | u32 max_used_s_index; | 405 | u32 max_used_s_index; |
409 | #endif | ||
410 | 406 | ||
411 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ | 407 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ |
412 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; | 408 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; |
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c index d24d4bc5..ec6816c6 100644 --- a/drivers/gpu/nvgpu/gk20a/hal.c +++ b/drivers/gpu/nvgpu/gk20a/hal.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * NVIDIA GPU HAL interface. | 2 | * NVIDIA GPU HAL interface. |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -27,10 +27,8 @@ | |||
27 | #include "gm20b/hal_gm20b.h" | 27 | #include "gm20b/hal_gm20b.h" |
28 | #include "gp10b/hal_gp10b.h" | 28 | #include "gp10b/hal_gp10b.h" |
29 | #include "gp106/hal_gp106.h" | 29 | #include "gp106/hal_gp106.h" |
30 | 30 | #include "gv100/hal_gv100.h" | |
31 | #ifdef CONFIG_TEGRA_19x_GPU | 31 | #include "gv11b/hal_gv11b.h" |
32 | #include "nvgpu_gpuid_t19x.h" | ||
33 | #endif | ||
34 | 32 | ||
35 | #include <nvgpu/log.h> | 33 | #include <nvgpu/log.h> |
36 | 34 | ||
@@ -53,17 +51,15 @@ int gpu_init_hal(struct gk20a *g) | |||
53 | if (gp106_init_hal(g)) | 51 | if (gp106_init_hal(g)) |
54 | return -ENODEV; | 52 | return -ENODEV; |
55 | break; | 53 | break; |
56 | #ifdef CONFIG_TEGRA_19x_GPU | 54 | case NVGPU_GPUID_GV11B: |
57 | case TEGRA_19x_GPUID: | 55 | if (gv11b_init_hal(g)) |
58 | if (TEGRA_19x_GPUID_HAL(g)) | ||
59 | return -ENODEV; | 56 | return -ENODEV; |
60 | break; | 57 | break; |
61 | case BIGGPU_19x_GPUID: | 58 | case NVGPU_GPUID_GV100: |
62 | if (BIGGPU_19x_GPUID_HAL(g)) | 59 | if (gv100_init_hal(g)) |
63 | return -ENODEV; | 60 | return -ENODEV; |
64 | break; | 61 | break; |
65 | 62 | ||
66 | #endif | ||
67 | default: | 63 | default: |
68 | nvgpu_err(g, "no support for %x", ver); | 64 | nvgpu_err(g, "no support for %x", ver); |
69 | return -ENODEV; | 65 | return -ENODEV; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 9c2f72fb..603d25fe 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A PMU (aka. gPMU outside gk20a context) | 2 | * GK20A PMU (aka. gPMU outside gk20a context) |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -39,10 +39,6 @@ | |||
39 | #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> | 39 | #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> |
40 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 40 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
41 | 41 | ||
42 | #ifdef CONFIG_TEGRA_19x_GPU | ||
43 | #include "nvgpu_gpuid_t19x.h" | ||
44 | #endif | ||
45 | |||
46 | #define gk20a_dbg_pmu(fmt, arg...) \ | 42 | #define gk20a_dbg_pmu(fmt, arg...) \ |
47 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 43 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
48 | 44 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index 2168cb4f..438002e4 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,9 +28,6 @@ | |||
28 | 28 | ||
29 | #include "gr_gk20a.h" | 29 | #include "gr_gk20a.h" |
30 | 30 | ||
31 | #ifdef CONFIG_TEGRA_19x_GPU | ||
32 | #include "tsg_t19x.h" | ||
33 | #endif | ||
34 | #define NVGPU_INVALID_TSG_ID (-1) | 31 | #define NVGPU_INVALID_TSG_ID (-1) |
35 | 32 | ||
36 | struct channel_gk20a; | 33 | struct channel_gk20a; |
@@ -68,9 +65,9 @@ struct tsg_gk20a { | |||
68 | u32 runlist_id; | 65 | u32 runlist_id; |
69 | pid_t tgid; | 66 | pid_t tgid; |
70 | struct nvgpu_mem *eng_method_buffers; | 67 | struct nvgpu_mem *eng_method_buffers; |
71 | #ifdef CONFIG_TEGRA_19x_GPU | 68 | u32 num_active_tpcs; |
72 | struct tsg_t19x t19x; | 69 | u8 tpc_pg_enabled; |
73 | #endif | 70 | bool tpc_num_initialized; |
74 | 71 | ||
75 | struct nvgpu_gr_ctx gr_ctx; | 72 | struct nvgpu_gr_ctx gr_ctx; |
76 | }; | 73 | }; |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 0dfa8e0e..31ddecf0 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -35,17 +35,13 @@ | |||
35 | #include "gm20b/acr_gm20b.h" | 35 | #include "gm20b/acr_gm20b.h" |
36 | #include "gp106/acr_gp106.h" | 36 | #include "gp106/acr_gp106.h" |
37 | #include "gp106/pmu_gp106.h" | 37 | #include "gp106/pmu_gp106.h" |
38 | #include "gv100/acr_gv100.h" | ||
38 | 39 | ||
39 | #include "sec2_gp106.h" | 40 | #include "sec2_gp106.h" |
40 | 41 | ||
41 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> | 42 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> |
42 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 43 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
43 | 44 | ||
44 | #ifdef CONFIG_TEGRA_19x_GPU | ||
45 | #include "nvgpu_gpuid_t19x.h" | ||
46 | #include "acr_t19x.h" | ||
47 | #endif | ||
48 | |||
49 | /*Defines*/ | 45 | /*Defines*/ |
50 | #define gp106_dbg_pmu(fmt, arg...) \ | 46 | #define gp106_dbg_pmu(fmt, arg...) \ |
51 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 47 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
@@ -200,17 +196,15 @@ int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
200 | GP106_FECS_UCODE_SIG, | 196 | GP106_FECS_UCODE_SIG, |
201 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | 197 | NVGPU_REQUEST_FIRMWARE_NO_SOC); |
202 | break; | 198 | break; |
203 | #if defined(CONFIG_TEGRA_19x_GPU) | 199 | case NVGPU_GPUID_GV11B: |
204 | case TEGRA_19x_GPUID: | ||
205 | fecs_sig = nvgpu_request_firmware(g, | 200 | fecs_sig = nvgpu_request_firmware(g, |
206 | GM20B_FECS_UCODE_SIG, 0); | 201 | GM20B_FECS_UCODE_SIG, 0); |
207 | break; | 202 | break; |
208 | case BIGGPU_19x_GPUID: | 203 | case NVGPU_GPUID_GV100: |
209 | fecs_sig = nvgpu_request_firmware(g, | 204 | fecs_sig = nvgpu_request_firmware(g, |
210 | BIGGPU_FECS_UCODE_SIG, | 205 | GV100_FECS_UCODE_SIG, |
211 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | 206 | NVGPU_REQUEST_FIRMWARE_NO_SOC); |
212 | break; | 207 | break; |
213 | #endif | ||
214 | default: | 208 | default: |
215 | nvgpu_err(g, "no support for GPUID %x", ver); | 209 | nvgpu_err(g, "no support for GPUID %x", ver); |
216 | } | 210 | } |
@@ -297,17 +291,15 @@ int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img_v1 *p_img) | |||
297 | GP106_GPCCS_UCODE_SIG, | 291 | GP106_GPCCS_UCODE_SIG, |
298 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | 292 | NVGPU_REQUEST_FIRMWARE_NO_SOC); |
299 | break; | 293 | break; |
300 | #if defined(CONFIG_TEGRA_19x_GPU) | 294 | case NVGPU_GPUID_GV11B: |
301 | case TEGRA_19x_GPUID: | ||
302 | gpccs_sig = nvgpu_request_firmware(g, | 295 | gpccs_sig = nvgpu_request_firmware(g, |
303 | T18x_GPCCS_UCODE_SIG, 0); | 296 | T18x_GPCCS_UCODE_SIG, 0); |
304 | break; | 297 | break; |
305 | case BIGGPU_19x_GPUID: | 298 | case NVGPU_GPUID_GV100: |
306 | gpccs_sig = nvgpu_request_firmware(g, | 299 | gpccs_sig = nvgpu_request_firmware(g, |
307 | BIGGPU_GPCCS_UCODE_SIG, | 300 | GV100_GPCCS_UCODE_SIG, |
308 | NVGPU_REQUEST_FIRMWARE_NO_SOC); | 301 | NVGPU_REQUEST_FIRMWARE_NO_SOC); |
309 | break; | 302 | break; |
310 | #endif | ||
311 | default: | 303 | default: |
312 | nvgpu_err(g, "no support for GPUID %x", ver); | 304 | nvgpu_err(g, "no support for GPUID %x", ver); |
313 | } | 305 | } |
diff --git a/drivers/gpu/nvgpu/acr_t19x.h b/drivers/gpu/nvgpu/gv100/acr_gv100.h index 0693c6a1..e5e7c454 100644 --- a/drivers/gpu/nvgpu/acr_t19x.h +++ b/drivers/gpu/nvgpu/gv100/acr_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -20,10 +20,10 @@ | |||
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | 22 | ||
23 | #ifndef _NVGPU_ACR_T19X_H_ | 23 | #ifndef _NVGPU_ACR_GV100_H_ |
24 | #define _NVGPU_ACR_T19X_H_ | 24 | #define _NVGPU_ACR_GV100_H_ |
25 | 25 | ||
26 | #define BIGGPU_FECS_UCODE_SIG "gv100/fecs_sig.bin" | 26 | #define GV100_FECS_UCODE_SIG "gv100/fecs_sig.bin" |
27 | #define BIGGPU_GPCCS_UCODE_SIG "gv100/gpccs_sig.bin" | 27 | #define GV100_GPCCS_UCODE_SIG "gv100/gpccs_sig.bin" |
28 | 28 | ||
29 | #endif | 29 | #endif |
diff --git a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h index 2302d988..649a6b21 100644 --- a/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h +++ b/drivers/gpu/nvgpu/gv100/gr_ctx_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -23,7 +23,6 @@ | |||
23 | #define __GR_CTX_GV100_H__ | 23 | #define __GR_CTX_GV100_H__ |
24 | 24 | ||
25 | #include "gk20a/gr_ctx_gk20a.h" | 25 | #include "gk20a/gr_ctx_gk20a.h" |
26 | #include "nvgpu_gpuid_t19x.h" | ||
27 | 26 | ||
28 | /* production netlist, one and only one from below */ | 27 | /* production netlist, one and only one from below */ |
29 | #define GV100_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D | 28 | #define GV100_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D |
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c index f90fd075..0fa05714 100644 --- a/drivers/gpu/nvgpu/gv100/gr_gv100.c +++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c | |||
@@ -323,7 +323,7 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g) | |||
323 | /* | 323 | /* |
324 | * We need this for all subcontexts | 324 | * We need this for all subcontexts |
325 | */ | 325 | */ |
326 | size *= f->t19x.max_subctx_count; | 326 | size *= f->max_subctx_count; |
327 | 327 | ||
328 | /* | 328 | /* |
329 | * Add space for a partition mode change as well | 329 | * Add space for a partition mode change as well |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index ca41a90b..6103b923 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -79,6 +79,7 @@ | |||
79 | #include "gv11b/dbg_gpu_gv11b.h" | 79 | #include "gv11b/dbg_gpu_gv11b.h" |
80 | #include "gv11b/hal_gv11b.h" | 80 | #include "gv11b/hal_gv11b.h" |
81 | #include "gv100/gr_gv100.h" | 81 | #include "gv100/gr_gv100.h" |
82 | #include "gv11b/gr_gv11b.h" | ||
82 | #include "gv11b/mc_gv11b.h" | 83 | #include "gv11b/mc_gv11b.h" |
83 | #include "gv11b/ltc_gv11b.h" | 84 | #include "gv11b/ltc_gv11b.h" |
84 | #include "gv11b/gv11b.h" | 85 | #include "gv11b/gv11b.h" |
@@ -106,7 +107,6 @@ | |||
106 | #include <nvgpu/bus.h> | 107 | #include <nvgpu/bus.h> |
107 | #include <nvgpu/debug.h> | 108 | #include <nvgpu/debug.h> |
108 | #include <nvgpu/enabled.h> | 109 | #include <nvgpu/enabled.h> |
109 | #include <nvgpu/enabled_t19x.h> | ||
110 | #include <nvgpu/ctxsw_trace.h> | 110 | #include <nvgpu/ctxsw_trace.h> |
111 | 111 | ||
112 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> | 112 | #include <nvgpu/hw/gv100/hw_proj_gv100.h> |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.h b/drivers/gpu/nvgpu/gv100/hal_gv100.h index 7dcf1d77..7564947e 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.h +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 Tegra HAL interface | 2 | * GV100 Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,9 +22,11 @@ | |||
22 | * DEALINGS IN THE SOFTWARE. | 22 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef _NVGPU_HAL_GV11B_H | 25 | #ifndef _NVGPU_HAL_GV100_H |
26 | #define _NVGPU_HAL_GV11B_H | 26 | #define _NVGPU_HAL_GV100_H |
27 | |||
27 | struct gk20a; | 28 | struct gk20a; |
28 | 29 | ||
29 | int gv100_init_hal(struct gk20a *gops); | 30 | int gv100_init_hal(struct gk20a *gops); |
31 | |||
30 | #endif | 32 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h b/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h deleted file mode 100644 index ebce46ce..00000000 --- a/drivers/gpu/nvgpu/gv11b/ecc_gv11b.h +++ /dev/null | |||
@@ -1,66 +0,0 @@ | |||
1 | /* | ||
2 | * GV11B GPU ECC | ||
3 | * | ||
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_ECC_GV11B_H_ | ||
26 | #define _NVGPU_ECC_GV11B_H_ | ||
27 | |||
28 | struct ecc_gr_t19x { | ||
29 | struct gk20a_ecc_stat sm_l1_tag_corrected_err_count; | ||
30 | struct gk20a_ecc_stat sm_l1_tag_uncorrected_err_count; | ||
31 | struct gk20a_ecc_stat sm_cbu_corrected_err_count; | ||
32 | struct gk20a_ecc_stat sm_cbu_uncorrected_err_count; | ||
33 | struct gk20a_ecc_stat sm_l1_data_corrected_err_count; | ||
34 | struct gk20a_ecc_stat sm_l1_data_uncorrected_err_count; | ||
35 | struct gk20a_ecc_stat sm_icache_corrected_err_count; | ||
36 | struct gk20a_ecc_stat sm_icache_uncorrected_err_count; | ||
37 | struct gk20a_ecc_stat gcc_l15_corrected_err_count; | ||
38 | struct gk20a_ecc_stat gcc_l15_uncorrected_err_count; | ||
39 | struct gk20a_ecc_stat fecs_corrected_err_count; | ||
40 | struct gk20a_ecc_stat fecs_uncorrected_err_count; | ||
41 | struct gk20a_ecc_stat gpccs_corrected_err_count; | ||
42 | struct gk20a_ecc_stat gpccs_uncorrected_err_count; | ||
43 | struct gk20a_ecc_stat mmu_l1tlb_corrected_err_count; | ||
44 | struct gk20a_ecc_stat mmu_l1tlb_uncorrected_err_count; | ||
45 | }; | ||
46 | |||
47 | struct ecc_ltc_t19x { | ||
48 | struct gk20a_ecc_stat l2_cache_corrected_err_count; | ||
49 | struct gk20a_ecc_stat l2_cache_uncorrected_err_count; | ||
50 | }; | ||
51 | |||
52 | /* TODO: PMU and FB ECC features are still under embargo */ | ||
53 | struct ecc_eng_t19x { | ||
54 | /* FB */ | ||
55 | struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count; | ||
56 | struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count; | ||
57 | struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count; | ||
58 | struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count; | ||
59 | struct gk20a_ecc_stat mmu_fillunit_corrected_err_count; | ||
60 | struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count; | ||
61 | /* PMU */ | ||
62 | struct gk20a_ecc_stat pmu_corrected_err_count; | ||
63 | struct gk20a_ecc_stat pmu_uncorrected_err_count; | ||
64 | }; | ||
65 | |||
66 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index 8ac3cb7b..b7a0a3cf 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B FB | 2 | * GV11B FB |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -568,9 +568,9 @@ static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
568 | uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()); | 568 | uncorrected_delta += (0x1UL << fb_mmu_l2tlb_ecc_uncorrected_err_count_total_s()); |
569 | 569 | ||
570 | 570 | ||
571 | g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0] += | 571 | g->ecc.fb.mmu_l2tlb_corrected_err_count.counters[0] += |
572 | corrected_delta; | 572 | corrected_delta; |
573 | g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0] += | 573 | g->ecc.fb.mmu_l2tlb_uncorrected_err_count.counters[0] += |
574 | uncorrected_delta; | 574 | uncorrected_delta; |
575 | 575 | ||
576 | if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) | 576 | if (ecc_status & fb_mmu_l2tlb_ecc_status_corrected_err_l2tlb_sa_data_m()) |
@@ -584,8 +584,8 @@ static void gv11b_handle_l2tlb_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
584 | "ecc error address: 0x%x", ecc_addr); | 584 | "ecc error address: 0x%x", ecc_addr); |
585 | nvgpu_log(g, gpu_dbg_intr, | 585 | nvgpu_log(g, gpu_dbg_intr, |
586 | "ecc error count corrected: %d, uncorrected %d", | 586 | "ecc error count corrected: %d, uncorrected %d", |
587 | g->ecc.eng.t19x.mmu_l2tlb_corrected_err_count.counters[0], | 587 | g->ecc.fb.mmu_l2tlb_corrected_err_count.counters[0], |
588 | g->ecc.eng.t19x.mmu_l2tlb_uncorrected_err_count.counters[0]); | 588 | g->ecc.fb.mmu_l2tlb_uncorrected_err_count.counters[0]); |
589 | } | 589 | } |
590 | 590 | ||
591 | static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) | 591 | static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) |
@@ -626,9 +626,9 @@ static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
626 | uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()); | 626 | uncorrected_delta += (0x1UL << fb_mmu_hubtlb_ecc_uncorrected_err_count_total_s()); |
627 | 627 | ||
628 | 628 | ||
629 | g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0] += | 629 | g->ecc.fb.mmu_hubtlb_corrected_err_count.counters[0] += |
630 | corrected_delta; | 630 | corrected_delta; |
631 | g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0] += | 631 | g->ecc.fb.mmu_hubtlb_uncorrected_err_count.counters[0] += |
632 | uncorrected_delta; | 632 | uncorrected_delta; |
633 | 633 | ||
634 | if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) | 634 | if (ecc_status & fb_mmu_hubtlb_ecc_status_corrected_err_sa_data_m()) |
@@ -642,8 +642,8 @@ static void gv11b_handle_hubtlb_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
642 | "ecc error address: 0x%x", ecc_addr); | 642 | "ecc error address: 0x%x", ecc_addr); |
643 | nvgpu_log(g, gpu_dbg_intr, | 643 | nvgpu_log(g, gpu_dbg_intr, |
644 | "ecc error count corrected: %d, uncorrected %d", | 644 | "ecc error count corrected: %d, uncorrected %d", |
645 | g->ecc.eng.t19x.mmu_hubtlb_corrected_err_count.counters[0], | 645 | g->ecc.fb.mmu_hubtlb_corrected_err_count.counters[0], |
646 | g->ecc.eng.t19x.mmu_hubtlb_uncorrected_err_count.counters[0]); | 646 | g->ecc.fb.mmu_hubtlb_uncorrected_err_count.counters[0]); |
647 | } | 647 | } |
648 | 648 | ||
649 | static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) | 649 | static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) |
@@ -684,9 +684,9 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
684 | uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()); | 684 | uncorrected_delta += (0x1UL << fb_mmu_fillunit_ecc_uncorrected_err_count_total_s()); |
685 | 685 | ||
686 | 686 | ||
687 | g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0] += | 687 | g->ecc.fb.mmu_fillunit_corrected_err_count.counters[0] += |
688 | corrected_delta; | 688 | corrected_delta; |
689 | g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0] += | 689 | g->ecc.fb.mmu_fillunit_uncorrected_err_count.counters[0] += |
690 | uncorrected_delta; | 690 | uncorrected_delta; |
691 | 691 | ||
692 | if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) | 692 | if (ecc_status & fb_mmu_fillunit_ecc_status_corrected_err_pte_data_m()) |
@@ -705,8 +705,8 @@ static void gv11b_handle_fillunit_ecc_isr(struct gk20a *g, u32 ecc_status) | |||
705 | "ecc error address: 0x%x", ecc_addr); | 705 | "ecc error address: 0x%x", ecc_addr); |
706 | nvgpu_log(g, gpu_dbg_intr, | 706 | nvgpu_log(g, gpu_dbg_intr, |
707 | "ecc error count corrected: %d, uncorrected %d", | 707 | "ecc error count corrected: %d, uncorrected %d", |
708 | g->ecc.eng.t19x.mmu_fillunit_corrected_err_count.counters[0], | 708 | g->ecc.fb.mmu_fillunit_corrected_err_count.counters[0], |
709 | g->ecc.eng.t19x.mmu_fillunit_uncorrected_err_count.counters[0]); | 709 | g->ecc.fb.mmu_fillunit_uncorrected_err_count.counters[0]); |
710 | } | 710 | } |
711 | 711 | ||
712 | static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault) | 712 | static void gv11b_fb_parse_mmfault(struct mmu_fault_info *mmfault) |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 7d3c5c75..271dcc41 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -30,10 +30,11 @@ | |||
30 | #include <nvgpu/gmmu.h> | 30 | #include <nvgpu/gmmu.h> |
31 | #include <nvgpu/soc.h> | 31 | #include <nvgpu/soc.h> |
32 | #include <nvgpu/debug.h> | 32 | #include <nvgpu/debug.h> |
33 | #include <nvgpu/nvhost_t19x.h> | 33 | #include <nvgpu/nvhost.h> |
34 | #include <nvgpu/barrier.h> | 34 | #include <nvgpu/barrier.h> |
35 | #include <nvgpu/mm.h> | 35 | #include <nvgpu/mm.h> |
36 | #include <nvgpu/ctxsw_trace.h> | 36 | #include <nvgpu/ctxsw_trace.h> |
37 | #include <nvgpu/io_usermode.h> | ||
37 | 38 | ||
38 | #include "gk20a/gk20a.h" | 39 | #include "gk20a/gk20a.h" |
39 | #include "gk20a/fifo_gk20a.h" | 40 | #include "gk20a/fifo_gk20a.h" |
@@ -96,7 +97,7 @@ void gv11b_get_ch_runlist_entry(struct channel_gk20a *c, u32 *runlist) | |||
96 | /* Time being use 0 pbdma sequencer */ | 97 | /* Time being use 0 pbdma sequencer */ |
97 | runlist_entry = ram_rl_entry_type_channel_v() | | 98 | runlist_entry = ram_rl_entry_type_channel_v() | |
98 | ram_rl_entry_chan_runqueue_selector_f( | 99 | ram_rl_entry_chan_runqueue_selector_f( |
99 | c->t19x.runqueue_sel) | | 100 | c->runqueue_sel) | |
100 | ram_rl_entry_chan_userd_target_f( | 101 | ram_rl_entry_chan_userd_target_f( |
101 | nvgpu_aperture_mask(g, &g->fifo.userd, | 102 | nvgpu_aperture_mask(g, &g->fifo.userd, |
102 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), | 103 | ram_rl_entry_chan_userd_target_sys_mem_ncoh_v(), |
@@ -185,7 +186,7 @@ int channel_gv11b_setup_ramfc(struct channel_gk20a *c, | |||
185 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); | 186 | nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); |
186 | 187 | ||
187 | nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), | 188 | nvgpu_mem_wr32(g, mem, ram_fc_set_channel_info_w(), |
188 | pbdma_set_channel_info_veid_f(c->t19x.subctx_id)); | 189 | pbdma_set_channel_info_veid_f(c->subctx_id)); |
189 | 190 | ||
190 | gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); | 191 | gv11b_fifo_init_ramfc_eng_method_buffer(g, c, mem); |
191 | 192 | ||
@@ -215,7 +216,7 @@ static void gv11b_ring_channel_doorbell(struct channel_gk20a *c) | |||
215 | 216 | ||
216 | gk20a_dbg_info("channel ring door bell %d\n", c->chid); | 217 | gk20a_dbg_info("channel ring door bell %d\n", c->chid); |
217 | 218 | ||
218 | gv11b_usermode_writel(c->g, usermode_notify_channel_pending_r(), | 219 | nvgpu_usermode_writel(c->g, usermode_notify_channel_pending_r(), |
219 | usermode_notify_channel_pending_id_f(hw_chid)); | 220 | usermode_notify_channel_pending_id_f(hw_chid)); |
220 | } | 221 | } |
221 | 222 | ||
@@ -1782,8 +1783,7 @@ int gv11b_init_fifo_setup_hw(struct gk20a *g) | |||
1782 | { | 1783 | { |
1783 | struct fifo_gk20a *f = &g->fifo; | 1784 | struct fifo_gk20a *f = &g->fifo; |
1784 | 1785 | ||
1785 | f->t19x.max_subctx_count = | 1786 | f->max_subctx_count = gr_pri_fe_chip_def_info_max_veid_count_init_v(); |
1786 | gr_pri_fe_chip_def_info_max_veid_count_init_v(); | ||
1787 | return 0; | 1787 | return 0; |
1788 | } | 1788 | } |
1789 | 1789 | ||
@@ -1794,7 +1794,7 @@ static u32 gv11b_mmu_fault_id_to_gr_veid(struct gk20a *g, u32 gr_eng_fault_id, | |||
1794 | u32 num_subctx; | 1794 | u32 num_subctx; |
1795 | u32 veid = FIFO_INVAL_VEID; | 1795 | u32 veid = FIFO_INVAL_VEID; |
1796 | 1796 | ||
1797 | num_subctx = f->t19x.max_subctx_count; | 1797 | num_subctx = f->max_subctx_count; |
1798 | 1798 | ||
1799 | if (mmu_fault_id >= gr_eng_fault_id && | 1799 | if (mmu_fault_id >= gr_eng_fault_id && |
1800 | mmu_fault_id < (gr_eng_fault_id + num_subctx)) | 1800 | mmu_fault_id < (gr_eng_fault_id + num_subctx)) |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 9c79b29b..7288284e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -189,7 +189,7 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
189 | l1_tag_corrected_err_count_delta += | 189 | l1_tag_corrected_err_count_delta += |
190 | (is_l1_tag_ecc_corrected_total_err_overflow << | 190 | (is_l1_tag_ecc_corrected_total_err_overflow << |
191 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()); | 191 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_s()); |
192 | g->ecc.gr.t19x.sm_l1_tag_corrected_err_count.counters[tpc] += | 192 | g->ecc.gr.sm_l1_tag_corrected_err_count.counters[tpc] += |
193 | l1_tag_corrected_err_count_delta; | 193 | l1_tag_corrected_err_count_delta; |
194 | gk20a_writel(g, | 194 | gk20a_writel(g, |
195 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() + offset, | 195 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_r() + offset, |
@@ -204,7 +204,7 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
204 | l1_tag_uncorrected_err_count_delta += | 204 | l1_tag_uncorrected_err_count_delta += |
205 | (is_l1_tag_ecc_uncorrected_total_err_overflow << | 205 | (is_l1_tag_ecc_uncorrected_total_err_overflow << |
206 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()); | 206 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_s()); |
207 | g->ecc.gr.t19x.sm_l1_tag_uncorrected_err_count.counters[tpc] += | 207 | g->ecc.gr.sm_l1_tag_uncorrected_err_count.counters[tpc] += |
208 | l1_tag_uncorrected_err_count_delta; | 208 | l1_tag_uncorrected_err_count_delta; |
209 | gk20a_writel(g, | 209 | gk20a_writel(g, |
210 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() + offset, | 210 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_r() + offset, |
@@ -399,7 +399,7 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
399 | cbu_corrected_err_count_delta += | 399 | cbu_corrected_err_count_delta += |
400 | (is_cbu_ecc_corrected_total_err_overflow << | 400 | (is_cbu_ecc_corrected_total_err_overflow << |
401 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); | 401 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); |
402 | g->ecc.gr.t19x.sm_cbu_corrected_err_count.counters[tpc] += | 402 | g->ecc.gr.sm_cbu_corrected_err_count.counters[tpc] += |
403 | cbu_corrected_err_count_delta; | 403 | cbu_corrected_err_count_delta; |
404 | gk20a_writel(g, | 404 | gk20a_writel(g, |
405 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + offset, | 405 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + offset, |
@@ -414,7 +414,7 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
414 | cbu_uncorrected_err_count_delta += | 414 | cbu_uncorrected_err_count_delta += |
415 | (is_cbu_ecc_uncorrected_total_err_overflow << | 415 | (is_cbu_ecc_uncorrected_total_err_overflow << |
416 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); | 416 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); |
417 | g->ecc.gr.t19x.sm_cbu_uncorrected_err_count.counters[tpc] += | 417 | g->ecc.gr.sm_cbu_uncorrected_err_count.counters[tpc] += |
418 | cbu_uncorrected_err_count_delta; | 418 | cbu_uncorrected_err_count_delta; |
419 | gk20a_writel(g, | 419 | gk20a_writel(g, |
420 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + offset, | 420 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + offset, |
@@ -479,7 +479,7 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
479 | l1_data_corrected_err_count_delta += | 479 | l1_data_corrected_err_count_delta += |
480 | (is_l1_data_ecc_corrected_total_err_overflow << | 480 | (is_l1_data_ecc_corrected_total_err_overflow << |
481 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); | 481 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); |
482 | g->ecc.gr.t19x.sm_l1_data_corrected_err_count.counters[tpc] += | 482 | g->ecc.gr.sm_l1_data_corrected_err_count.counters[tpc] += |
483 | l1_data_corrected_err_count_delta; | 483 | l1_data_corrected_err_count_delta; |
484 | gk20a_writel(g, | 484 | gk20a_writel(g, |
485 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + offset, | 485 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + offset, |
@@ -494,7 +494,7 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
494 | l1_data_uncorrected_err_count_delta += | 494 | l1_data_uncorrected_err_count_delta += |
495 | (is_l1_data_ecc_uncorrected_total_err_overflow << | 495 | (is_l1_data_ecc_uncorrected_total_err_overflow << |
496 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); | 496 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); |
497 | g->ecc.gr.t19x.sm_l1_data_uncorrected_err_count.counters[tpc] += | 497 | g->ecc.gr.sm_l1_data_uncorrected_err_count.counters[tpc] += |
498 | l1_data_uncorrected_err_count_delta; | 498 | l1_data_uncorrected_err_count_delta; |
499 | gk20a_writel(g, | 499 | gk20a_writel(g, |
500 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + offset, | 500 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + offset, |
@@ -563,7 +563,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
563 | icache_corrected_err_count_delta += | 563 | icache_corrected_err_count_delta += |
564 | (is_icache_ecc_corrected_total_err_overflow << | 564 | (is_icache_ecc_corrected_total_err_overflow << |
565 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); | 565 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); |
566 | g->ecc.gr.t19x.sm_icache_corrected_err_count.counters[tpc] += | 566 | g->ecc.gr.sm_icache_corrected_err_count.counters[tpc] += |
567 | icache_corrected_err_count_delta; | 567 | icache_corrected_err_count_delta; |
568 | gk20a_writel(g, | 568 | gk20a_writel(g, |
569 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + offset, | 569 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + offset, |
@@ -578,7 +578,7 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
578 | icache_uncorrected_err_count_delta += | 578 | icache_uncorrected_err_count_delta += |
579 | (is_icache_ecc_uncorrected_total_err_overflow << | 579 | (is_icache_ecc_uncorrected_total_err_overflow << |
580 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); | 580 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); |
581 | g->ecc.gr.t19x.sm_icache_uncorrected_err_count.counters[tpc] += | 581 | g->ecc.gr.sm_icache_uncorrected_err_count.counters[tpc] += |
582 | icache_uncorrected_err_count_delta; | 582 | icache_uncorrected_err_count_delta; |
583 | gk20a_writel(g, | 583 | gk20a_writel(g, |
584 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + offset, | 584 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + offset, |
@@ -667,7 +667,7 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
667 | gcc_l15_corrected_err_count_delta += | 667 | gcc_l15_corrected_err_count_delta += |
668 | (is_gcc_l15_ecc_corrected_total_err_overflow << | 668 | (is_gcc_l15_ecc_corrected_total_err_overflow << |
669 | gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s()); | 669 | gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_s()); |
670 | g->ecc.gr.t19x.gcc_l15_corrected_err_count.counters[gpc] += | 670 | g->ecc.gr.gcc_l15_corrected_err_count.counters[gpc] += |
671 | gcc_l15_corrected_err_count_delta; | 671 | gcc_l15_corrected_err_count_delta; |
672 | gk20a_writel(g, | 672 | gk20a_writel(g, |
673 | gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() + offset, | 673 | gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_r() + offset, |
@@ -682,7 +682,7 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
682 | gcc_l15_uncorrected_err_count_delta += | 682 | gcc_l15_uncorrected_err_count_delta += |
683 | (is_gcc_l15_ecc_uncorrected_total_err_overflow << | 683 | (is_gcc_l15_ecc_uncorrected_total_err_overflow << |
684 | gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()); | 684 | gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_total_s()); |
685 | g->ecc.gr.t19x.gcc_l15_uncorrected_err_count.counters[gpc] += | 685 | g->ecc.gr.gcc_l15_uncorrected_err_count.counters[gpc] += |
686 | gcc_l15_uncorrected_err_count_delta; | 686 | gcc_l15_uncorrected_err_count_delta; |
687 | gk20a_writel(g, | 687 | gk20a_writel(g, |
688 | gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() + offset, | 688 | gr_pri_gpc0_gcc_l15_ecc_uncorrected_err_count_r() + offset, |
@@ -752,9 +752,9 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc, | |||
752 | uncorrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s()); | 752 | uncorrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s()); |
753 | 753 | ||
754 | 754 | ||
755 | g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count.counters[gpc] += | 755 | g->ecc.gr.mmu_l1tlb_corrected_err_count.counters[gpc] += |
756 | corrected_delta; | 756 | corrected_delta; |
757 | g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count.counters[gpc] += | 757 | g->ecc.gr.mmu_l1tlb_uncorrected_err_count.counters[gpc] += |
758 | uncorrected_delta; | 758 | uncorrected_delta; |
759 | nvgpu_log(g, gpu_dbg_intr, | 759 | nvgpu_log(g, gpu_dbg_intr, |
760 | "mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); | 760 | "mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); |
@@ -774,8 +774,8 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc, | |||
774 | "ecc error address: 0x%x", ecc_addr); | 774 | "ecc error address: 0x%x", ecc_addr); |
775 | nvgpu_log(g, gpu_dbg_intr, | 775 | nvgpu_log(g, gpu_dbg_intr, |
776 | "ecc error count corrected: %d, uncorrected %d", | 776 | "ecc error count corrected: %d, uncorrected %d", |
777 | g->ecc.gr.t19x.mmu_l1tlb_corrected_err_count.counters[gpc], | 777 | g->ecc.gr.mmu_l1tlb_corrected_err_count.counters[gpc], |
778 | g->ecc.gr.t19x.mmu_l1tlb_uncorrected_err_count.counters[gpc]); | 778 | g->ecc.gr.mmu_l1tlb_uncorrected_err_count.counters[gpc]); |
779 | 779 | ||
780 | return ret; | 780 | return ret; |
781 | } | 781 | } |
@@ -830,9 +830,9 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, | |||
830 | gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, | 830 | gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, |
831 | gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); | 831 | gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); |
832 | 832 | ||
833 | g->ecc.gr.t19x.gpccs_corrected_err_count.counters[gpc] += | 833 | g->ecc.gr.gpccs_corrected_err_count.counters[gpc] += |
834 | corrected_delta; | 834 | corrected_delta; |
835 | g->ecc.gr.t19x.gpccs_uncorrected_err_count.counters[gpc] += | 835 | g->ecc.gr.gpccs_uncorrected_err_count.counters[gpc] += |
836 | uncorrected_delta; | 836 | uncorrected_delta; |
837 | nvgpu_log(g, gpu_dbg_intr, | 837 | nvgpu_log(g, gpu_dbg_intr, |
838 | "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); | 838 | "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); |
@@ -857,8 +857,8 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, | |||
857 | 857 | ||
858 | nvgpu_log(g, gpu_dbg_intr, | 858 | nvgpu_log(g, gpu_dbg_intr, |
859 | "ecc error count corrected: %d, uncorrected %d", | 859 | "ecc error count corrected: %d, uncorrected %d", |
860 | g->ecc.gr.t19x.gpccs_corrected_err_count.counters[gpc], | 860 | g->ecc.gr.gpccs_corrected_err_count.counters[gpc], |
861 | g->ecc.gr.t19x.gpccs_uncorrected_err_count.counters[gpc]); | 861 | g->ecc.gr.gpccs_uncorrected_err_count.counters[gpc]); |
862 | 862 | ||
863 | return ret; | 863 | return ret; |
864 | } | 864 | } |
@@ -2206,9 +2206,9 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) | |||
2206 | gk20a_writel(g, gr_fecs_falcon_ecc_status_r(), | 2206 | gk20a_writel(g, gr_fecs_falcon_ecc_status_r(), |
2207 | gr_fecs_falcon_ecc_status_reset_task_f()); | 2207 | gr_fecs_falcon_ecc_status_reset_task_f()); |
2208 | 2208 | ||
2209 | g->ecc.gr.t19x.fecs_corrected_err_count.counters[0] += | 2209 | g->ecc.gr.fecs_corrected_err_count.counters[0] += |
2210 | corrected_delta; | 2210 | corrected_delta; |
2211 | g->ecc.gr.t19x.fecs_uncorrected_err_count.counters[0] += | 2211 | g->ecc.gr.fecs_uncorrected_err_count.counters[0] += |
2212 | uncorrected_delta; | 2212 | uncorrected_delta; |
2213 | 2213 | ||
2214 | nvgpu_log(g, gpu_dbg_intr, | 2214 | nvgpu_log(g, gpu_dbg_intr, |
@@ -2237,8 +2237,8 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) | |||
2237 | 2237 | ||
2238 | nvgpu_log(g, gpu_dbg_intr, | 2238 | nvgpu_log(g, gpu_dbg_intr, |
2239 | "ecc error count corrected: %d, uncorrected %d", | 2239 | "ecc error count corrected: %d, uncorrected %d", |
2240 | g->ecc.gr.t19x.fecs_corrected_err_count.counters[0], | 2240 | g->ecc.gr.fecs_corrected_err_count.counters[0], |
2241 | g->ecc.gr.t19x.fecs_uncorrected_err_count.counters[0]); | 2241 | g->ecc.gr.fecs_uncorrected_err_count.counters[0]); |
2242 | } | 2242 | } |
2243 | } | 2243 | } |
2244 | 2244 | ||
@@ -2323,7 +2323,7 @@ static int gv11b_write_bundle_veid_state(struct gk20a *g, u32 index) | |||
2323 | u32 j; | 2323 | u32 j; |
2324 | u32 num_subctx, err = 0; | 2324 | u32 num_subctx, err = 0; |
2325 | 2325 | ||
2326 | num_subctx = g->fifo.t19x.max_subctx_count; | 2326 | num_subctx = g->fifo.max_subctx_count; |
2327 | 2327 | ||
2328 | for (j = 0; j < num_subctx; j++) { | 2328 | for (j = 0; j < num_subctx; j++) { |
2329 | nvgpu_log_fn(g, "write bundle_address_r for subctx: %d", j); | 2329 | nvgpu_log_fn(g, "write bundle_address_r for subctx: %d", j); |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index f8f80df3..774afe56 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -34,12 +34,6 @@ | |||
34 | #define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 | 34 | #define ZBC_STENCIL_CLEAR_FMT_INVAILD 0 |
35 | #define ZBC_STENCIL_CLEAR_FMT_U8 1 | 35 | #define ZBC_STENCIL_CLEAR_FMT_U8 1 |
36 | 36 | ||
37 | struct zbc_s_table { | ||
38 | u32 stencil; | ||
39 | u32 format; | ||
40 | u32 ref_cnt; | ||
41 | }; | ||
42 | |||
43 | struct gk20a; | 37 | struct gk20a; |
44 | struct gr_gk20a; | 38 | struct gr_gk20a; |
45 | struct zbc_entry; | 39 | struct zbc_entry; |
diff --git a/drivers/gpu/nvgpu/gv11b/gv11b.c b/drivers/gpu/nvgpu/gv11b/gv11b.c index a62e49fb..709f18df 100644 --- a/drivers/gpu/nvgpu/gv11b/gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B Graphics | 2 | * GV11B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -23,7 +23,6 @@ | |||
23 | */ | 23 | */ |
24 | 24 | ||
25 | #include <nvgpu/enabled.h> | 25 | #include <nvgpu/enabled.h> |
26 | #include <nvgpu/enabled_t19x.h> | ||
27 | 26 | ||
28 | #include "gk20a/gk20a.h" | 27 | #include "gk20a/gk20a.h" |
29 | #include "gp10b/gp10b.h" | 28 | #include "gp10b/gp10b.h" |
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c index 8661b420..a596c3b2 100644 --- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B LTC | 2 | * GV11B LTC |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -177,9 +177,9 @@ void gv11b_ltc_isr(struct gk20a *g) | |||
177 | } | 177 | } |
178 | 178 | ||
179 | } | 179 | } |
180 | g->ecc.ltc.t19x.l2_cache_corrected_err_count.counters[ltc] += | 180 | g->ecc.ltc.l2_cache_corrected_err_count.counters[ltc] += |
181 | ltc_corrected; | 181 | ltc_corrected; |
182 | g->ecc.ltc.t19x.l2_cache_uncorrected_err_count.counters[ltc] += | 182 | g->ecc.ltc.l2_cache_uncorrected_err_count.counters[ltc] += |
183 | ltc_uncorrected; | 183 | ltc_uncorrected; |
184 | 184 | ||
185 | } | 185 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c index fdc506ac..943ae22a 100644 --- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B MMU | 2 | * GV11B MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -273,7 +273,7 @@ void gv11b_mm_l2_flush(struct gk20a *g, bool invalidate) | |||
273 | u64 gv11b_gpu_phys_addr(struct gk20a *g, | 273 | u64 gv11b_gpu_phys_addr(struct gk20a *g, |
274 | struct nvgpu_gmmu_attrs *attrs, u64 phys) | 274 | struct nvgpu_gmmu_attrs *attrs, u64 phys) |
275 | { | 275 | { |
276 | if (attrs && attrs->t19x_attrs.l3_alloc) | 276 | if (attrs && attrs->l3_alloc) |
277 | return phys | NVGPU_L3_ALLOC_BIT; | 277 | return phys | NVGPU_L3_ALLOC_BIT; |
278 | 278 | ||
279 | return phys; | 279 | return phys; |
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index a972510f..e4cfe925 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV11B PMU | 2 | * GV11B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -343,8 +343,8 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0) | |||
343 | if (uncorrected_overflow) | 343 | if (uncorrected_overflow) |
344 | uncorrected_delta += (0x1UL << pwr_pmu_falcon_ecc_uncorrected_err_count_total_s()); | 344 | uncorrected_delta += (0x1UL << pwr_pmu_falcon_ecc_uncorrected_err_count_total_s()); |
345 | 345 | ||
346 | g->ecc.eng.t19x.pmu_corrected_err_count.counters[0] += corrected_delta; | 346 | g->ecc.pmu.pmu_corrected_err_count.counters[0] += corrected_delta; |
347 | g->ecc.eng.t19x.pmu_uncorrected_err_count.counters[0] += uncorrected_delta; | 347 | g->ecc.pmu.pmu_uncorrected_err_count.counters[0] += uncorrected_delta; |
348 | 348 | ||
349 | nvgpu_log(g, gpu_dbg_intr, | 349 | nvgpu_log(g, gpu_dbg_intr, |
350 | "pmu ecc interrupt intr1: 0x%x", intr1); | 350 | "pmu ecc interrupt intr1: 0x%x", intr1); |
@@ -371,8 +371,8 @@ void gv11b_pmu_handle_ext_irq(struct gk20a *g, u32 intr0) | |||
371 | 371 | ||
372 | nvgpu_log(g, gpu_dbg_intr, | 372 | nvgpu_log(g, gpu_dbg_intr, |
373 | "ecc error count corrected: %d, uncorrected %d", | 373 | "ecc error count corrected: %d, uncorrected %d", |
374 | g->ecc.eng.t19x.pmu_corrected_err_count.counters[0], | 374 | g->ecc.pmu.pmu_corrected_err_count.counters[0], |
375 | g->ecc.eng.t19x.pmu_uncorrected_err_count.counters[0]); | 375 | g->ecc.pmu.pmu_uncorrected_err_count.counters[0]); |
376 | } | 376 | } |
377 | } | 377 | } |
378 | } | 378 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index 607fff91..4f98d82a 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Volta GPU series Subcontext | 2 | * Volta GPU series Subcontext |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -103,9 +103,9 @@ static void gv11b_init_subcontext_pdb(struct channel_gk20a *c, | |||
103 | gv11b_subctx_commit_pdb(c, inst_block); | 103 | gv11b_subctx_commit_pdb(c, inst_block); |
104 | gv11b_subctx_commit_valid_mask(c, inst_block); | 104 | gv11b_subctx_commit_valid_mask(c, inst_block); |
105 | 105 | ||
106 | nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->t19x.subctx_id); | 106 | nvgpu_log(g, gpu_dbg_info, " subctx %d instblk set", c->subctx_id); |
107 | nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), | 107 | nvgpu_mem_wr32(g, inst_block, ram_in_engine_wfi_veid_w(), |
108 | ram_in_engine_wfi_veid_f(c->t19x.subctx_id)); | 108 | ram_in_engine_wfi_veid_f(c->subctx_id)); |
109 | 109 | ||
110 | } | 110 | } |
111 | 111 | ||
@@ -206,7 +206,7 @@ void gv11b_subctx_commit_pdb(struct channel_gk20a *c, | |||
206 | ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); | 206 | ram_in_sc_page_dir_base_lo_0_f(pdb_addr_lo); |
207 | nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", | 207 | nvgpu_log(g, gpu_dbg_info, " pdb info lo %x hi %x", |
208 | format_word, pdb_addr_hi); | 208 | format_word, pdb_addr_hi); |
209 | for (subctx_id = 0; subctx_id < f->t19x.max_subctx_count; subctx_id++) { | 209 | for (subctx_id = 0; subctx_id < f->max_subctx_count; subctx_id++) { |
210 | lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); | 210 | lo = ram_in_sc_page_dir_base_vol_0_w() + (4 * subctx_id); |
211 | hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); | 211 | hi = ram_in_sc_page_dir_base_hi_0_w() + (4 * subctx_id); |
212 | nvgpu_mem_wr32(g, inst_block, lo, format_word); | 212 | nvgpu_mem_wr32(g, inst_block, lo, format_word); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 001cafb0..c614ce4d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -142,6 +142,8 @@ struct gk20a; | |||
142 | 142 | ||
143 | /* set if ASPM is enabled; only makes sense for PCI */ | 143 | /* set if ASPM is enabled; only makes sense for PCI */ |
144 | #define NVGPU_SUPPORT_ASPM 62 | 144 | #define NVGPU_SUPPORT_ASPM 62 |
145 | /* subcontexts are available */ | ||
146 | #define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63 | ||
145 | /* | 147 | /* |
146 | * Must be greater than the largest bit offset in the above list. | 148 | * Must be greater than the largest bit offset in the above list. |
147 | */ | 149 | */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h deleted file mode 100644 index 9ef1dc30..00000000 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled_t19x.h +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __NVGPU_ENABLED_T19X_H__ | ||
24 | #define __NVGPU_ENABLED_T19X_H__ | ||
25 | |||
26 | /* subcontexts are available */ | ||
27 | #define NVGPU_SUPPORT_TSG_SUBCONTEXTS 63 | ||
28 | |||
29 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h index ade94df9..02b211d6 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gmmu.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -29,10 +29,6 @@ | |||
29 | #include <nvgpu/rbtree.h> | 29 | #include <nvgpu/rbtree.h> |
30 | #include <nvgpu/lock.h> | 30 | #include <nvgpu/lock.h> |
31 | 31 | ||
32 | #ifdef CONFIG_TEGRA_19x_GPU | ||
33 | #include <nvgpu/gmmu_t19x.h> | ||
34 | #endif | ||
35 | |||
36 | /* | 32 | /* |
37 | * This is the GMMU API visible to blocks outside of the GMMU. Basically this | 33 | * This is the GMMU API visible to blocks outside of the GMMU. Basically this |
38 | * API supports all the different types of mappings that might be done in the | 34 | * API supports all the different types of mappings that might be done in the |
@@ -180,9 +176,7 @@ struct nvgpu_gmmu_attrs { | |||
180 | enum nvgpu_aperture aperture; | 176 | enum nvgpu_aperture aperture; |
181 | bool debug; | 177 | bool debug; |
182 | 178 | ||
183 | #ifdef CONFIG_TEGRA_19x_GPU | 179 | bool l3_alloc; |
184 | struct nvgpu_gmmu_attrs_t19x t19x_attrs; | ||
185 | #endif | ||
186 | }; | 180 | }; |
187 | 181 | ||
188 | struct gk20a_mmu_level { | 182 | struct gk20a_mmu_level { |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h deleted file mode 100644 index eea51fbb..00000000 --- a/drivers/gpu/nvgpu/include/nvgpu/gmmu_t19x.h +++ /dev/null | |||
@@ -1,34 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __NVGPU_GMMU_T19X_H__ | ||
24 | #define __NVGPU_GMMU_T19X_H__ | ||
25 | |||
26 | struct nvgpu_gmmu_attrs; | ||
27 | |||
28 | struct nvgpu_gmmu_attrs_t19x { | ||
29 | bool l3_alloc; | ||
30 | }; | ||
31 | |||
32 | void nvgpu_gmmu_add_t19x_attrs(struct nvgpu_gmmu_attrs *attrs, u32 flags); | ||
33 | |||
34 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/io.h b/drivers/gpu/nvgpu/include/nvgpu/io.h index b7281b41..28011e04 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/io.h +++ b/drivers/gpu/nvgpu/include/nvgpu/io.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -23,9 +23,6 @@ | |||
23 | #define __NVGPU_IO_H__ | 23 | #define __NVGPU_IO_H__ |
24 | 24 | ||
25 | #include <nvgpu/types.h> | 25 | #include <nvgpu/types.h> |
26 | #ifdef CONFIG_TEGRA_19x_GPU | ||
27 | #include <nvgpu/io_t19x.h> | ||
28 | #endif | ||
29 | 26 | ||
30 | /* Legacy defines - should be removed once everybody uses nvgpu_* */ | 27 | /* Legacy defines - should be removed once everybody uses nvgpu_* */ |
31 | #define gk20a_writel nvgpu_writel | 28 | #define gk20a_writel nvgpu_writel |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h deleted file mode 100644 index f8c7dbbd..00000000 --- a/drivers/gpu/nvgpu/include/nvgpu/io_t19x.h +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | #ifndef __NVGPU_IO_T19X_H__ | ||
23 | #define __NVGPU_IO_T19X_H__ | ||
24 | |||
25 | #ifdef __KERNEL__ | ||
26 | #include "linux/io_t19x.h" | ||
27 | #endif | ||
28 | |||
29 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gr_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/io_usermode.h index 954472fa..a756ef44 100644 --- a/drivers/gpu/nvgpu/gr_t19x.h +++ b/drivers/gpu/nvgpu/include/nvgpu/io_usermode.h | |||
@@ -1,7 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * NVIDIA T19x GR | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | 3 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -21,9 +19,9 @@ | |||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
22 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
23 | */ | 21 | */ |
24 | #ifndef _NVGPU_GR_T19X_H_ | 22 | #ifndef __NVGPU_IO_USERMODE_H__ |
25 | #define _NVGPU_GR_T19X_H_ | 23 | #define __NVGPU_IO_USERMODE_H__ |
26 | 24 | ||
27 | #include "gv11b/gr_gv11b.h" | 25 | void nvgpu_usermode_writel(struct gk20a *g, u32 r, u32 v); |
28 | 26 | ||
29 | #endif | 27 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h deleted file mode 100644 index f71a6ecf..00000000 --- a/drivers/gpu/nvgpu/include/nvgpu/linux/io_t19x.h +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #ifndef __NVGPU_IO_T19X_LINUX_H__ | ||
18 | #define __NVGPU_IO_T19X_LINUX_H__ | ||
19 | |||
20 | #include <nvgpu/types.h> | ||
21 | |||
22 | struct gk20a; | ||
23 | |||
24 | void gv11b_usermode_writel(struct gk20a *g, u32 r, u32 v); | ||
25 | |||
26 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h deleted file mode 100644 index a306bfb8..00000000 --- a/drivers/gpu/nvgpu/include/nvgpu/linux/os_linux_t19x.h +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | #ifndef NVGPU_OS_LINUX_T19X_H | ||
17 | #define NVGPU_OS_LINUX_T19X_H | ||
18 | |||
19 | #include <linux/compiler.h> | ||
20 | |||
21 | struct nvgpu_os_linux_t19x { | ||
22 | void __iomem *usermode_regs; | ||
23 | void __iomem *usermode_regs_saved; | ||
24 | }; | ||
25 | |||
26 | #endif | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mm.h b/drivers/gpu/nvgpu/include/nvgpu/mm.h index f2d3ba26..e7b3e52c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mm.h +++ b/drivers/gpu/nvgpu/include/nvgpu/mm.h | |||
@@ -1,4 +1,6 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
2 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
3 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
4 | * to deal in the Software without restriction, including without limitation | 6 | * to deal in the Software without restriction, including without limitation |
@@ -126,13 +128,12 @@ struct mm_gk20a { | |||
126 | 128 | ||
127 | struct nvgpu_mem bar2_desc; | 129 | struct nvgpu_mem bar2_desc; |
128 | 130 | ||
129 | #ifdef CONFIG_TEGRA_19x_GPU | ||
130 | struct nvgpu_mem hw_fault_buf[FAULT_TYPE_NUM]; | 131 | struct nvgpu_mem hw_fault_buf[FAULT_TYPE_NUM]; |
131 | unsigned int hw_fault_buf_status[FAULT_TYPE_NUM]; | 132 | unsigned int hw_fault_buf_status[FAULT_TYPE_NUM]; |
132 | struct mmu_fault_info *fault_info[FAULT_TYPE_NUM]; | 133 | struct mmu_fault_info *fault_info[FAULT_TYPE_NUM]; |
133 | struct nvgpu_mutex hub_isr_mutex; | 134 | struct nvgpu_mutex hub_isr_mutex; |
134 | u32 hub_intr_types; | 135 | u32 hub_intr_types; |
135 | #endif | 136 | |
136 | /* | 137 | /* |
137 | * Separate function to cleanup the CE since it requires a channel to | 138 | * Separate function to cleanup the CE since it requires a channel to |
138 | * be closed which must happen before fifo cleanup. | 139 | * be closed which must happen before fifo cleanup. |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost.h index d852c77c..6e92637a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/nvhost.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvhost.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -77,5 +77,19 @@ struct sync_fence *nvgpu_nvhost_sync_create_fence( | |||
77 | struct nvgpu_nvhost_dev *nvhost_dev, | 77 | struct nvgpu_nvhost_dev *nvhost_dev, |
78 | u32 id, u32 thresh, const char *name); | 78 | u32 id, u32 thresh, const char *name); |
79 | #endif /* CONFIG_SYNC */ | 79 | #endif /* CONFIG_SYNC */ |
80 | |||
81 | #ifdef CONFIG_TEGRA_T19X_GRHOST | ||
82 | int nvgpu_nvhost_syncpt_unit_interface_get_aperture( | ||
83 | struct nvgpu_nvhost_dev *nvhost_dev, | ||
84 | u64 *base, size_t *size); | ||
85 | u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); | ||
86 | #else | ||
87 | static inline int nvgpu_nvhost_syncpt_unit_interface_get_aperture( | ||
88 | struct nvgpu_nvhost_dev *nvhost_dev, | ||
89 | u64 *base, size_t *size) { return -EINVAL; } | ||
90 | static inline u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id) { | ||
91 | return 0; | ||
92 | } | ||
93 | #endif | ||
80 | #endif /* CONFIG_TEGRA_GK20A_NVHOST */ | 94 | #endif /* CONFIG_TEGRA_GK20A_NVHOST */ |
81 | #endif /* __NVGPU_NVHOST_H__ */ | 95 | #endif /* __NVGPU_NVHOST_H__ */ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h b/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h deleted file mode 100644 index 4b499882..00000000 --- a/drivers/gpu/nvgpu/include/nvgpu/nvhost_t19x.h +++ /dev/null | |||
@@ -1,37 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef __NVGPU_NVHOST_T19X_H__ | ||
24 | #define __NVGPU_NVHOST_T19X_H__ | ||
25 | |||
26 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
27 | #include <nvgpu/types.h> | ||
28 | |||
29 | struct nvgpu_nvhost_dev; | ||
30 | |||
31 | int nvgpu_nvhost_syncpt_unit_interface_get_aperture( | ||
32 | struct nvgpu_nvhost_dev *nvhost_dev, | ||
33 | u64 *base, size_t *size); | ||
34 | u32 nvgpu_nvhost_syncpt_unit_interface_get_byte_offset(u32 syncpt_id); | ||
35 | |||
36 | #endif | ||
37 | #endif /* __NVGPU_NVHOST_T19X_H__ */ | ||
diff --git a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h b/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h deleted file mode 100644 index 8689a535..00000000 --- a/drivers/gpu/nvgpu/nvgpu_gpuid_t19x.h +++ /dev/null | |||
@@ -1,47 +0,0 @@ | |||
1 | /* | ||
2 | * NVIDIA GPU ID functions, definitions. | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | #ifndef _NVGPU_GPUID_T19X_H_ | ||
25 | #define _NVGPU_GPUID_T19X_H_ | ||
26 | |||
27 | #define NVGPU_GPUID_GV11B 0x0000015B | ||
28 | #define NVGPU_GPUID_GV100 0x00000140 | ||
29 | |||
30 | #define NVGPU_COMPAT_TEGRA_GV11B "nvidia,gv11b" | ||
31 | #define NVGPU_COMPAT_GENERIC_GV11B "nvidia,generic-gv11b" | ||
32 | |||
33 | |||
34 | #define TEGRA_19x_GPUID NVGPU_GPUID_GV11B | ||
35 | #define TEGRA_19x_GPUID_HAL gv11b_init_hal | ||
36 | #define TEGRA_19x_GPU_COMPAT_TEGRA NVGPU_COMPAT_TEGRA_GV11B | ||
37 | #define TEGRA_19x_GPU_COMPAT_GENERIC NVGPU_COMPAT_GENERIC_GV11B | ||
38 | |||
39 | #define BIGGPU_19x_GPUID NVGPU_GPUID_GV100 | ||
40 | #define BIGGPU_19x_GPUID_HAL gv100_init_hal | ||
41 | |||
42 | struct gpu_ops; | ||
43 | extern int gv11b_init_hal(struct gk20a *); | ||
44 | extern int gv100_init_hal(struct gk20a *); | ||
45 | extern struct gk20a_platform t19x_gpu_tegra_platform; | ||
46 | |||
47 | #endif | ||
diff --git a/drivers/gpu/nvgpu/tsg_t19x.h b/drivers/gpu/nvgpu/tsg_t19x.h deleted file mode 100644 index d1f47cc3..00000000 --- a/drivers/gpu/nvgpu/tsg_t19x.h +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | /* | ||
2 | * NVIDIA T19x TSG | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef __NVGPU_TSG_T19X_H__ | ||
26 | #define __NVGPU_TSG_T19X_H__ | ||
27 | |||
28 | #include <nvgpu/types.h> | ||
29 | |||
30 | struct tsg_t19x { | ||
31 | u32 num_active_tpcs; | ||
32 | u8 tpc_pg_enabled; | ||
33 | bool tpc_num_initialized; | ||
34 | }; | ||
35 | |||
36 | #endif | ||