diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 100 |
1 files changed, 47 insertions, 53 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index be567c26..ec487bdf 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |||
@@ -29,6 +29,7 @@ | |||
29 | #include <nvgpu/enabled.h> | 29 | #include <nvgpu/enabled.h> |
30 | #include <nvgpu/gmmu.h> | 30 | #include <nvgpu/gmmu.h> |
31 | #include <nvgpu/barrier.h> | 31 | #include <nvgpu/barrier.h> |
32 | #include <nvgpu/soc.h> | ||
32 | 33 | ||
33 | #include "gk20a/gk20a.h" | 34 | #include "gk20a/gk20a.h" |
34 | #include "gk20a/mm_gk20a.h" | 35 | #include "gk20a/mm_gk20a.h" |
@@ -41,7 +42,6 @@ | |||
41 | 42 | ||
42 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> | 43 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> |
43 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | 44 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> |
44 | #include <nvgpu/hw/gv11b/hw_fifo_gv11b.h> | ||
45 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | 45 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> |
46 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> | 46 | #include <nvgpu/hw/gv11b/hw_gmmu_gv11b.h> |
47 | 47 | ||
@@ -53,35 +53,41 @@ static int gv11b_fb_mmu_invalidate_replay(struct gk20a *g, | |||
53 | 53 | ||
54 | static void gv11b_init_nvlink_soc_credits(struct gk20a *g) | 54 | static void gv11b_init_nvlink_soc_credits(struct gk20a *g) |
55 | { | 55 | { |
56 | void __iomem *soc1 = ioremap(0x01f20010, 4096); //MSS_NVLINK_1_BASE | 56 | if (nvgpu_is_bpmp_running(g) && (!nvgpu_platform_is_simulation(g))) { |
57 | void __iomem *soc2 = ioremap(0x01f40010, 4096); //MSS_NVLINK_2_BASE | 57 | nvgpu_info(g, "nvlink soc credits init done by bpmp"); |
58 | void __iomem *soc3 = ioremap(0x01f60010, 4096); //MSS_NVLINK_3_BASE | 58 | } else { |
59 | void __iomem *soc4 = ioremap(0x01f80010, 4096); //MSS_NVLINK_4_BASE | 59 | /* MSS_NVLINK_1_BASE */ |
60 | u32 val; | 60 | void __iomem *soc1 = ioremap(0x01f20010, 4096); |
61 | 61 | /* MSS_NVLINK_2_BASE */ | |
62 | /* TODO : replace this code with proper nvlink API */ | 62 | void __iomem *soc2 = ioremap(0x01f40010, 4096); |
63 | nvgpu_info(g, "init nvlink soc credits"); | 63 | /* MSS_NVLINK_3_BASE */ |
64 | 64 | void __iomem *soc3 = ioremap(0x01f60010, 4096); | |
65 | val = readl_relaxed(soc1); | 65 | /* MSS_NVLINK_4_BASE */ |
66 | writel_relaxed(val, soc1); | 66 | void __iomem *soc4 = ioremap(0x01f80010, 4096); |
67 | val = readl_relaxed(soc1 + 4); | 67 | u32 val; |
68 | writel_relaxed(val, soc1 + 4); | 68 | |
69 | 69 | nvgpu_info(g, "init nvlink soc credits"); | |
70 | val = readl_relaxed(soc2); | 70 | |
71 | writel_relaxed(val, soc2); | 71 | val = readl_relaxed(soc1); |
72 | val = readl_relaxed(soc2 + 4); | 72 | writel_relaxed(val, soc1); |
73 | writel_relaxed(val, soc2 + 4); | 73 | val = readl_relaxed(soc1 + 4); |
74 | 74 | writel_relaxed(val, soc1 + 4); | |
75 | val = readl_relaxed(soc3); | 75 | |
76 | writel_relaxed(val, soc3); | 76 | val = readl_relaxed(soc2); |
77 | val = readl_relaxed(soc3 + 4); | 77 | writel_relaxed(val, soc2); |
78 | writel_relaxed(val, soc3 + 4); | 78 | val = readl_relaxed(soc2 + 4); |
79 | 79 | writel_relaxed(val, soc2 + 4); | |
80 | val = readl_relaxed(soc4); | 80 | |
81 | writel_relaxed(val, soc4); | 81 | val = readl_relaxed(soc3); |
82 | val = readl_relaxed(soc4 + 4); | 82 | writel_relaxed(val, soc3); |
83 | writel_relaxed(val, soc4 + 4); | 83 | val = readl_relaxed(soc3 + 4); |
84 | 84 | writel_relaxed(val, soc3 + 4); | |
85 | |||
86 | val = readl_relaxed(soc4); | ||
87 | writel_relaxed(val, soc4); | ||
88 | val = readl_relaxed(soc4 + 4); | ||
89 | writel_relaxed(val, soc4 + 4); | ||
90 | } | ||
85 | } | 91 | } |
86 | 92 | ||
87 | void gv11b_fb_init_fs_state(struct gk20a *g) | 93 | void gv11b_fb_init_fs_state(struct gk20a *g) |
@@ -149,33 +155,21 @@ void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | |||
149 | 155 | ||
150 | void gv11b_fb_reset(struct gk20a *g) | 156 | void gv11b_fb_reset(struct gk20a *g) |
151 | { | 157 | { |
152 | u32 val; | 158 | if (nvgpu_is_bpmp_running(g) && (!nvgpu_platform_is_simulation(g))) { |
153 | 159 | nvgpu_log(g, gpu_dbg_info, "mc_elpg_enable set by bpmp"); | |
154 | nvgpu_info(g, "reset gv11b fb"); | 160 | } else { |
155 | 161 | u32 mc_elpg_enable_val; | |
156 | g->ops.mc.reset(g, mc_enable_pfb_enabled_f() | | ||
157 | mc_enable_xbar_enabled_f() | | ||
158 | mc_enable_hub_enabled_f()); | ||
159 | 162 | ||
160 | val = gk20a_readl(g, mc_elpg_enable_r()); | 163 | nvgpu_log(g, gpu_dbg_info, "enable xbar, pfb and hub"); |
161 | val |= mc_elpg_enable_xbar_enabled_f() | | 164 | mc_elpg_enable_val = mc_elpg_enable_xbar_enabled_f() | |
162 | mc_elpg_enable_pfb_enabled_f() | | 165 | mc_elpg_enable_pfb_enabled_f() | |
163 | mc_elpg_enable_hub_enabled_f(); | 166 | mc_elpg_enable_hub_enabled_f(); |
164 | gk20a_writel(g, mc_elpg_enable_r(), val); | 167 | mc_elpg_enable_val |= gk20a_readl(g, mc_elpg_enable_r()); |
168 | gk20a_writel(g, mc_elpg_enable_r(), mc_elpg_enable_val); | ||
165 | 169 | ||
170 | } | ||
166 | /* fs hub should be out of reset by now */ | 171 | /* fs hub should be out of reset by now */ |
167 | gv11b_init_nvlink_soc_credits(g); | 172 | gv11b_init_nvlink_soc_credits(g); |
168 | |||
169 | val = gk20a_readl(g, fifo_fb_iface_r()); | ||
170 | nvgpu_info(g, "fifo_fb_iface val = 0x%x", val); | ||
171 | if (!(val & fifo_fb_iface_control_enable_f() && | ||
172 | val & fifo_fb_iface_status_enabled_f())) { | ||
173 | nvgpu_info(g, "fifo_fb_iface set control enable"); | ||
174 | gk20a_writel(g, fifo_fb_iface_r(), | ||
175 | fifo_fb_iface_control_enable_f()); | ||
176 | val = gk20a_readl(g, fifo_fb_iface_r()); | ||
177 | nvgpu_info(g, "fifo_fb_iface val = 0x%x", val); | ||
178 | } | ||
179 | } | 173 | } |
180 | 174 | ||
181 | static const char * const invalid_str = "invalid"; | 175 | static const char * const invalid_str = "invalid"; |