diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 39 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/fifo_gv100.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 |
11 files changed, 90 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index a1844a28..d6f1cb3a 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1980,6 +1980,27 @@ void gk20a_fifo_recover_tsg(struct gk20a *g, struct tsg_gk20a *tsg, | |||
1980 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 1980 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1981 | } | 1981 | } |
1982 | 1982 | ||
1983 | void gk20a_fifo_teardown_mask_intr(struct gk20a *g) | ||
1984 | { | ||
1985 | u32 val; | ||
1986 | |||
1987 | val = gk20a_readl(g, fifo_intr_en_0_r()); | ||
1988 | val &= ~(fifo_intr_en_0_sched_error_m() | | ||
1989 | fifo_intr_en_0_mmu_fault_m()); | ||
1990 | gk20a_writel(g, fifo_intr_en_0_r(), val); | ||
1991 | gk20a_writel(g, fifo_intr_0_r(), fifo_intr_0_sched_error_reset_f()); | ||
1992 | } | ||
1993 | |||
1994 | void gk20a_fifo_teardown_unmask_intr(struct gk20a *g) | ||
1995 | { | ||
1996 | u32 val; | ||
1997 | |||
1998 | val = gk20a_readl(g, fifo_intr_en_0_r()); | ||
1999 | val |= fifo_intr_en_0_mmu_fault_f(1) | fifo_intr_en_0_sched_error_f(1); | ||
2000 | gk20a_writel(g, fifo_intr_en_0_r(), val); | ||
2001 | |||
2002 | } | ||
2003 | |||
1983 | void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, | 2004 | void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, |
1984 | u32 hw_id, unsigned int id_type, unsigned int rc_type, | 2005 | u32 hw_id, unsigned int id_type, unsigned int rc_type, |
1985 | struct mmu_fault_info *mmfault) | 2006 | struct mmu_fault_info *mmfault) |
@@ -1987,7 +2008,6 @@ void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, | |||
1987 | unsigned long engine_id, i; | 2008 | unsigned long engine_id, i; |
1988 | unsigned long _engine_ids = __engine_ids; | 2009 | unsigned long _engine_ids = __engine_ids; |
1989 | unsigned long engine_ids = 0; | 2010 | unsigned long engine_ids = 0; |
1990 | u32 val; | ||
1991 | u32 mmu_fault_engines = 0; | 2011 | u32 mmu_fault_engines = 0; |
1992 | u32 ref_type; | 2012 | u32 ref_type; |
1993 | u32 ref_id; | 2013 | u32 ref_id; |
@@ -2048,25 +2068,12 @@ void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids, | |||
2048 | } | 2068 | } |
2049 | 2069 | ||
2050 | if (mmu_fault_engines) { | 2070 | if (mmu_fault_engines) { |
2051 | /* | 2071 | g->ops.fifo.teardown_mask_intr(g); |
2052 | * sched error prevents recovery, and ctxsw error will retrigger | ||
2053 | * every 100ms. Disable the sched error to allow recovery. | ||
2054 | */ | ||
2055 | val = gk20a_readl(g, fifo_intr_en_0_r()); | ||
2056 | val &= ~(fifo_intr_en_0_sched_error_m() | | ||
2057 | fifo_intr_en_0_mmu_fault_m()); | ||
2058 | gk20a_writel(g, fifo_intr_en_0_r(), val); | ||
2059 | gk20a_writel(g, fifo_intr_0_r(), | ||
2060 | fifo_intr_0_sched_error_reset_f()); | ||
2061 | |||
2062 | g->ops.fifo.trigger_mmu_fault(g, engine_ids); | 2072 | g->ops.fifo.trigger_mmu_fault(g, engine_ids); |
2063 | gk20a_fifo_handle_mmu_fault_locked(g, mmu_fault_engines, ref_id, | 2073 | gk20a_fifo_handle_mmu_fault_locked(g, mmu_fault_engines, ref_id, |
2064 | ref_id_is_tsg); | 2074 | ref_id_is_tsg); |
2065 | 2075 | ||
2066 | val = gk20a_readl(g, fifo_intr_en_0_r()); | 2076 | g->ops.fifo.teardown_unmask_intr(g); |
2067 | val |= fifo_intr_en_0_mmu_fault_f(1) | ||
2068 | | fifo_intr_en_0_sched_error_f(1); | ||
2069 | gk20a_writel(g, fifo_intr_en_0_r(), val); | ||
2070 | } | 2077 | } |
2071 | 2078 | ||
2072 | nvgpu_log_info(g, "release runlist_lock for all runlists"); | 2079 | nvgpu_log_info(g, "release runlist_lock for all runlists"); |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 29c2f889..0c9d9101 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -426,6 +426,8 @@ bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch, | |||
426 | bool *verbose, u32 *ms); | 426 | bool *verbose, u32 *ms); |
427 | bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, | 427 | bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg, |
428 | bool *verbose, u32 *ms); | 428 | bool *verbose, u32 *ms); |
429 | void gk20a_fifo_teardown_mask_intr(struct gk20a *g); | ||
430 | void gk20a_fifo_teardown_unmask_intr(struct gk20a *g); | ||
429 | bool gk20a_fifo_handle_sched_error(struct gk20a *g); | 431 | bool gk20a_fifo_handle_sched_error(struct gk20a *g); |
430 | 432 | ||
431 | void gk20a_fifo_reset_pbdma_method(struct gk20a *g, int pbdma_id, | 433 | void gk20a_fifo_reset_pbdma_method(struct gk20a *g, int pbdma_id, |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index dbfbc3d7..c5bf4ff5 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -448,6 +448,8 @@ static const struct gpu_ops gm20b_ops = { | |||
448 | .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs, | 448 | .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs, |
449 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | 449 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, |
450 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | 450 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, |
451 | .teardown_mask_intr = gk20a_fifo_teardown_mask_intr, | ||
452 | .teardown_unmask_intr = gk20a_fifo_teardown_unmask_intr, | ||
451 | .handle_sched_error = gk20a_fifo_handle_sched_error, | 453 | .handle_sched_error = gk20a_fifo_handle_sched_error, |
452 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | 454 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, |
453 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | 455 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index b3379253..5fcfb32f 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -488,6 +488,8 @@ static const struct gpu_ops gp10b_ops = { | |||
488 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, | 488 | .init_pbdma_intr_descs = gp10b_fifo_init_pbdma_intr_descs, |
489 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | 489 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, |
490 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | 490 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, |
491 | .teardown_mask_intr = gk20a_fifo_teardown_mask_intr, | ||
492 | .teardown_unmask_intr = gk20a_fifo_teardown_unmask_intr, | ||
491 | .handle_sched_error = gk20a_fifo_handle_sched_error, | 493 | .handle_sched_error = gk20a_fifo_handle_sched_error, |
492 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | 494 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, |
493 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | 495 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, |
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.c b/drivers/gpu/nvgpu/gv100/fifo_gv100.c index 0b5515f2..e23bc77b 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.c +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 fifo | 2 | * GV100 fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -55,3 +55,21 @@ void gv100_apply_ctxsw_timeout_intr(struct gk20a *g) | |||
55 | gk20a_writel(g, fifo_eng_timeout_r(), timeout); | 55 | gk20a_writel(g, fifo_eng_timeout_r(), timeout); |
56 | } | 56 | } |
57 | 57 | ||
58 | void gv100_fifo_teardown_mask_intr(struct gk20a *g) | ||
59 | { | ||
60 | u32 val; | ||
61 | |||
62 | val = gk20a_readl(g, fifo_intr_en_0_r()); | ||
63 | val &= ~(fifo_intr_en_0_sched_error_m()); | ||
64 | gk20a_writel(g, fifo_intr_en_0_r(), val); | ||
65 | gk20a_writel(g, fifo_intr_0_r(), fifo_intr_0_sched_error_reset_f()); | ||
66 | } | ||
67 | |||
68 | void gv100_fifo_teardown_unmask_intr(struct gk20a *g) | ||
69 | { | ||
70 | u32 val; | ||
71 | |||
72 | val = gk20a_readl(g, fifo_intr_en_0_r()); | ||
73 | val |= fifo_intr_en_0_sched_error_f(1); | ||
74 | gk20a_writel(g, fifo_intr_en_0_r(), val); | ||
75 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/fifo_gv100.h b/drivers/gpu/nvgpu/gv100/fifo_gv100.h index 0af3fcce..e9a89766 100644 --- a/drivers/gpu/nvgpu/gv100/fifo_gv100.h +++ b/drivers/gpu/nvgpu/gv100/fifo_gv100.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 Fifo | 2 | * GV100 Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -31,4 +31,6 @@ struct gk20a; | |||
31 | u32 gv100_fifo_get_num_fifos(struct gk20a *g); | 31 | u32 gv100_fifo_get_num_fifos(struct gk20a *g); |
32 | u32 gv100_fifo_get_preempt_timeout(struct gk20a *g); | 32 | u32 gv100_fifo_get_preempt_timeout(struct gk20a *g); |
33 | void gv100_apply_ctxsw_timeout_intr(struct gk20a *g); | 33 | void gv100_apply_ctxsw_timeout_intr(struct gk20a *g); |
34 | void gv100_fifo_teardown_mask_intr(struct gk20a *g); | ||
35 | void gv100_fifo_teardown_unmask_intr(struct gk20a *g); | ||
34 | #endif | 36 | #endif |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9621aaa4..c8849631 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -639,6 +639,8 @@ static const struct gpu_ops gv100_ops = { | |||
639 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, | 639 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, |
640 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | 640 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, |
641 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, | 641 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, |
642 | .teardown_mask_intr = gv100_fifo_teardown_mask_intr, | ||
643 | .teardown_unmask_intr = gv100_fifo_teardown_unmask_intr, | ||
642 | .handle_sched_error = gk20a_fifo_handle_sched_error, | 644 | .handle_sched_error = gk20a_fifo_handle_sched_error, |
643 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, | 645 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, |
644 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, | 646 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index b5af2972..5b84df47 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -982,6 +982,33 @@ static void gv11b_fifo_locked_abort_runlist_active_tsgs(struct gk20a *g, | |||
982 | } | 982 | } |
983 | } | 983 | } |
984 | 984 | ||
985 | void gv11b_fifo_teardown_mask_intr(struct gk20a *g) | ||
986 | { | ||
987 | u32 val; | ||
988 | |||
989 | /* | ||
990 | * ctxsw timeout error prevents recovery, and ctxsw error will retrigger | ||
991 | * every 100ms. Disable ctxsw timeout error to allow recovery. | ||
992 | */ | ||
993 | val = gk20a_readl(g, fifo_intr_en_0_r()); | ||
994 | val &= ~ fifo_intr_0_ctxsw_timeout_pending_f(); | ||
995 | gk20a_writel(g, fifo_intr_en_0_r(), val); | ||
996 | gk20a_writel(g, fifo_intr_ctxsw_timeout_r(), | ||
997 | gk20a_readl(g, fifo_intr_ctxsw_timeout_r())); | ||
998 | |||
999 | } | ||
1000 | |||
1001 | void gv11b_fifo_teardown_unmask_intr(struct gk20a *g) | ||
1002 | { | ||
1003 | u32 val; | ||
1004 | |||
1005 | /* enable ctxsw timeout interrupt */ | ||
1006 | val = gk20a_readl(g, fifo_intr_en_0_r()); | ||
1007 | val |= fifo_intr_0_ctxsw_timeout_pending_f(); | ||
1008 | gk20a_writel(g, fifo_intr_en_0_r(), val); | ||
1009 | } | ||
1010 | |||
1011 | |||
985 | void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, | 1012 | void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, |
986 | u32 id, unsigned int id_type, unsigned int rc_type, | 1013 | u32 id, unsigned int id_type, unsigned int rc_type, |
987 | struct mmu_fault_info *mmfault) | 1014 | struct mmu_fault_info *mmfault) |
@@ -1001,6 +1028,8 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, | |||
1001 | runlist_lock); | 1028 | runlist_lock); |
1002 | } | 1029 | } |
1003 | 1030 | ||
1031 | g->ops.fifo.teardown_mask_intr(g); | ||
1032 | |||
1004 | /* get runlist id and tsg */ | 1033 | /* get runlist id and tsg */ |
1005 | if (id_type == ID_TYPE_TSG) { | 1034 | if (id_type == ID_TYPE_TSG) { |
1006 | if (id != FIFO_INVAL_TSG_ID) { | 1035 | if (id != FIFO_INVAL_TSG_ID) { |
@@ -1195,6 +1224,8 @@ void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, | |||
1195 | nvgpu_pmu_enable_elpg(g); | 1224 | nvgpu_pmu_enable_elpg(g); |
1196 | } | 1225 | } |
1197 | 1226 | ||
1227 | g->ops.fifo.teardown_unmask_intr(g); | ||
1228 | |||
1198 | /* release runlist_lock */ | 1229 | /* release runlist_lock */ |
1199 | if (runlist_id != FIFO_INVAL_RUNLIST_ID) { | 1230 | if (runlist_id != FIFO_INVAL_RUNLIST_ID) { |
1200 | nvgpu_log_fn(g, "release runlist_lock runlist_id = %d", | 1231 | nvgpu_log_fn(g, "release runlist_lock runlist_id = %d", |
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h index 3d491bad..bc6b0f1c 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.h | |||
@@ -87,6 +87,8 @@ int gv11b_fifo_enable_tsg(struct tsg_gk20a *tsg); | |||
87 | void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, | 87 | void gv11b_fifo_teardown_ch_tsg(struct gk20a *g, u32 act_eng_bitmask, |
88 | u32 id, unsigned int id_type, unsigned int rc_type, | 88 | u32 id, unsigned int id_type, unsigned int rc_type, |
89 | struct mmu_fault_info *mmfault); | 89 | struct mmu_fault_info *mmfault); |
90 | void gv11b_fifo_teardown_mask_intr(struct gk20a *g); | ||
91 | void gv11b_fifo_teardown_unmask_intr(struct gk20a *g); | ||
90 | void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); | 92 | void gv11b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); |
91 | int gv11b_init_fifo_reset_enable_hw(struct gk20a *g); | 93 | int gv11b_init_fifo_reset_enable_hw(struct gk20a *g); |
92 | bool gv11b_fifo_handle_sched_error(struct gk20a *g); | 94 | bool gv11b_fifo_handle_sched_error(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index d52d1c7e..718b6f93 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -601,6 +601,8 @@ static const struct gpu_ops gv11b_ops = { | |||
601 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, | 601 | .init_pbdma_intr_descs = gv11b_fifo_init_pbdma_intr_descs, |
602 | .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, | 602 | .reset_enable_hw = gv11b_init_fifo_reset_enable_hw, |
603 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, | 603 | .teardown_ch_tsg = gv11b_fifo_teardown_ch_tsg, |
604 | .teardown_mask_intr = gv11b_fifo_teardown_mask_intr, | ||
605 | .teardown_unmask_intr = gv11b_fifo_teardown_unmask_intr, | ||
604 | .handle_sched_error = gv11b_fifo_handle_sched_error, | 606 | .handle_sched_error = gv11b_fifo_handle_sched_error, |
605 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, | 607 | .handle_pbdma_intr_0 = gv11b_fifo_handle_pbdma_intr_0, |
606 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, | 608 | .handle_pbdma_intr_1 = gv11b_fifo_handle_pbdma_intr_1, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index aa435638..81a4e7b8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -718,6 +718,8 @@ struct gpu_ops { | |||
718 | void (*teardown_ch_tsg)(struct gk20a *g, u32 act_eng_bitmask, | 718 | void (*teardown_ch_tsg)(struct gk20a *g, u32 act_eng_bitmask, |
719 | u32 id, unsigned int id_type, unsigned int rc_type, | 719 | u32 id, unsigned int id_type, unsigned int rc_type, |
720 | struct mmu_fault_info *mmfault); | 720 | struct mmu_fault_info *mmfault); |
721 | void (*teardown_mask_intr)(struct gk20a *g); | ||
722 | void (*teardown_unmask_intr)(struct gk20a *g); | ||
721 | bool (*handle_sched_error)(struct gk20a *g); | 723 | bool (*handle_sched_error)(struct gk20a *g); |
722 | bool (*handle_ctxsw_timeout)(struct gk20a *g, u32 fifo_intr); | 724 | bool (*handle_ctxsw_timeout)(struct gk20a *g, u32 fifo_intr); |
723 | unsigned int (*handle_pbdma_intr_0)(struct gk20a *g, | 725 | unsigned int (*handle_pbdma_intr_0)(struct gk20a *g, |