diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 87 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.h | 24 |
3 files changed, 87 insertions, 27 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 8f328696..e44ee631 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -91,6 +91,9 @@ struct gr_ctx_desc { | |||
91 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 91 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC |
92 | struct gr_ctx_desc_t18x t18x; | 92 | struct gr_ctx_desc_t18x t18x; |
93 | #endif | 93 | #endif |
94 | #ifdef CONFIG_TEGRA_GR_VIRTUALIZATION | ||
95 | u64 virt_ctx; | ||
96 | #endif | ||
94 | }; | 97 | }; |
95 | 98 | ||
96 | #define NVGPU_GR_PREEMPTION_MODE_WFI 0 | 99 | #define NVGPU_GR_PREEMPTION_MODE_WFI 0 |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 2b4b3c26..7dfc970e 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -70,9 +70,10 @@ static int vgpu_gr_load_golden_ctx_image(struct gk20a *g, | |||
70 | return (err || msg.ret) ? -1 : 0; | 70 | return (err || msg.ret) ? -1 : 0; |
71 | } | 71 | } |
72 | 72 | ||
73 | static int vgpu_gr_init_ctx_state(struct gk20a *g, struct gr_gk20a *gr) | 73 | int vgpu_gr_init_ctx_state(struct gk20a *g) |
74 | { | 74 | { |
75 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | 75 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); |
76 | struct gr_gk20a *gr = &g->gr; | ||
76 | 77 | ||
77 | gk20a_dbg_fn(""); | 78 | gk20a_dbg_fn(""); |
78 | 79 | ||
@@ -233,15 +234,17 @@ static void vgpu_gr_unmap_global_ctx_buffers(struct channel_gk20a *c) | |||
233 | c->ch_ctx.global_ctx_buffer_mapped = false; | 234 | c->ch_ctx.global_ctx_buffer_mapped = false; |
234 | } | 235 | } |
235 | 236 | ||
236 | static int vgpu_gr_alloc_channel_gr_ctx(struct gk20a *g, | 237 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, |
237 | struct channel_gk20a *c) | 238 | struct gr_ctx_desc **__gr_ctx, |
239 | struct vm_gk20a *vm, | ||
240 | u32 class, | ||
241 | u32 flags) | ||
238 | { | 242 | { |
239 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | 243 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); |
240 | struct tegra_vgpu_cmd_msg msg; | 244 | struct tegra_vgpu_cmd_msg msg; |
241 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; | 245 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; |
242 | struct gr_gk20a *gr = &g->gr; | 246 | struct gr_gk20a *gr = &g->gr; |
243 | struct gr_ctx_desc *gr_ctx; | 247 | struct gr_ctx_desc *gr_ctx = *__gr_ctx; |
244 | struct vm_gk20a *ch_vm = c->vm; | ||
245 | int err; | 248 | int err; |
246 | 249 | ||
247 | gk20a_dbg_fn(""); | 250 | gk20a_dbg_fn(""); |
@@ -253,12 +256,8 @@ static int vgpu_gr_alloc_channel_gr_ctx(struct gk20a *g, | |||
253 | gr->ctx_vars.buffer_size = gr->ctx_vars.golden_image_size; | 256 | gr->ctx_vars.buffer_size = gr->ctx_vars.golden_image_size; |
254 | gr->ctx_vars.buffer_total_size = gr->ctx_vars.golden_image_size; | 257 | gr->ctx_vars.buffer_total_size = gr->ctx_vars.golden_image_size; |
255 | 258 | ||
256 | gr_ctx = kzalloc(sizeof(*gr_ctx), GFP_KERNEL); | ||
257 | if (!gr_ctx) | ||
258 | return -ENOMEM; | ||
259 | |||
260 | gr_ctx->mem.size = gr->ctx_vars.buffer_total_size; | 259 | gr_ctx->mem.size = gr->ctx_vars.buffer_total_size; |
261 | gr_ctx->mem.gpu_va = gk20a_vm_alloc_va(ch_vm, gr_ctx->mem.size, 0); | 260 | gr_ctx->mem.gpu_va = gk20a_vm_alloc_va(vm, gr_ctx->mem.size, 0); |
262 | 261 | ||
263 | if (!gr_ctx->mem.gpu_va) { | 262 | if (!gr_ctx->mem.gpu_va) { |
264 | kfree(gr_ctx); | 263 | kfree(gr_ctx); |
@@ -267,48 +266,77 @@ static int vgpu_gr_alloc_channel_gr_ctx(struct gk20a *g, | |||
267 | 266 | ||
268 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX; | 267 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_CTX; |
269 | msg.handle = platform->virt_handle; | 268 | msg.handle = platform->virt_handle; |
270 | p->handle = c->virt_ctx; | 269 | p->handle = gr_ctx->virt_ctx; |
271 | p->gr_ctx_va = gr_ctx->mem.gpu_va; | 270 | p->gr_ctx_va = gr_ctx->mem.gpu_va; |
272 | p->class_num = c->obj_class; | 271 | p->class_num = class; |
273 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 272 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
274 | 273 | ||
275 | if (err || msg.ret) { | 274 | if (err || msg.ret) { |
276 | kfree(gr_ctx); | 275 | kfree(gr_ctx); |
277 | gk20a_vm_free_va(ch_vm, gr_ctx->mem.gpu_va, | 276 | gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, |
278 | gr_ctx->mem.size, 0); | 277 | gr_ctx->mem.size, 0); |
279 | err = -ENOMEM; | 278 | err = -ENOMEM; |
280 | } else | 279 | } |
281 | c->ch_ctx.gr_ctx = gr_ctx; | ||
282 | 280 | ||
283 | return err; | 281 | return err; |
284 | } | 282 | } |
285 | 283 | ||
286 | static void vgpu_gr_free_channel_gr_ctx(struct channel_gk20a *c) | 284 | static int vgpu_gr_alloc_channel_gr_ctx(struct gk20a *g, |
285 | struct channel_gk20a *c, | ||
286 | u32 class, | ||
287 | u32 flags) | ||
287 | { | 288 | { |
288 | struct gk20a_platform *platform = gk20a_get_platform(c->g->dev); | 289 | struct gr_ctx_desc **gr_ctx = &c->ch_ctx.gr_ctx; |
289 | struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; | 290 | struct gr_ctx_desc *__gr_ctx = kzalloc(sizeof(*__gr_ctx), GFP_KERNEL); |
290 | struct vm_gk20a *ch_vm = c->vm; | 291 | int err; |
291 | 292 | ||
292 | gk20a_dbg_fn(""); | 293 | gk20a_dbg_fn(""); |
293 | 294 | ||
294 | if (ch_ctx->gr_ctx && ch_ctx->gr_ctx->mem.gpu_va) { | 295 | if (!__gr_ctx) |
296 | return -ENOMEM; | ||
297 | |||
298 | __gr_ctx->virt_ctx = c->virt_ctx; | ||
299 | *gr_ctx = __gr_ctx; | ||
300 | err = g->ops.gr.alloc_gr_ctx(g, gr_ctx, c->vm, class, flags); | ||
301 | if (err) { | ||
302 | kfree(__gr_ctx); | ||
303 | return err; | ||
304 | } | ||
305 | |||
306 | c->ch_ctx.gr_ctx = __gr_ctx; | ||
307 | return 0; | ||
308 | } | ||
309 | |||
310 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
311 | struct gr_ctx_desc *gr_ctx) | ||
312 | { | ||
313 | gk20a_dbg_fn(""); | ||
314 | |||
315 | if (gr_ctx && gr_ctx->mem.gpu_va) { | ||
316 | struct gk20a_platform *platform = gk20a_get_platform(g->dev); | ||
295 | struct tegra_vgpu_cmd_msg msg; | 317 | struct tegra_vgpu_cmd_msg msg; |
296 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; | 318 | struct tegra_vgpu_gr_ctx_params *p = &msg.params.gr_ctx; |
297 | int err; | 319 | int err; |
298 | 320 | ||
299 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX; | 321 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FREE_GR_CTX; |
300 | msg.handle = platform->virt_handle; | 322 | msg.handle = platform->virt_handle; |
301 | p->handle = c->virt_ctx; | 323 | p->handle = gr_ctx->virt_ctx; |
302 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 324 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
303 | WARN_ON(err || msg.ret); | 325 | WARN_ON(err || msg.ret); |
304 | 326 | ||
305 | gk20a_vm_free_va(ch_vm, ch_ctx->gr_ctx->mem.gpu_va, | 327 | gk20a_vm_free_va(vm, gr_ctx->mem.gpu_va, gr_ctx->mem.size, 0); |
306 | ch_ctx->gr_ctx->mem.size, 0); | 328 | kfree(gr_ctx); |
307 | ch_ctx->gr_ctx->mem.gpu_va = 0; | ||
308 | kfree(ch_ctx->gr_ctx); | ||
309 | } | 329 | } |
310 | } | 330 | } |
311 | 331 | ||
332 | static void vgpu_gr_free_channel_gr_ctx(struct channel_gk20a *c) | ||
333 | { | ||
334 | gk20a_dbg_fn(""); | ||
335 | |||
336 | c->g->ops.gr.free_gr_ctx(c->g, c->vm, c->ch_ctx.gr_ctx); | ||
337 | c->ch_ctx.gr_ctx = NULL; | ||
338 | } | ||
339 | |||
312 | static int vgpu_gr_alloc_channel_patch_ctx(struct gk20a *g, | 340 | static int vgpu_gr_alloc_channel_patch_ctx(struct gk20a *g, |
313 | struct channel_gk20a *c) | 341 | struct channel_gk20a *c) |
314 | { | 342 | { |
@@ -416,7 +444,9 @@ static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, | |||
416 | 444 | ||
417 | /* allocate gr ctx buffer */ | 445 | /* allocate gr ctx buffer */ |
418 | if (!ch_ctx->gr_ctx) { | 446 | if (!ch_ctx->gr_ctx) { |
419 | err = vgpu_gr_alloc_channel_gr_ctx(g, c); | 447 | err = vgpu_gr_alloc_channel_gr_ctx(g, c, |
448 | args->class_num, | ||
449 | args->flags); | ||
420 | if (err) { | 450 | if (err) { |
421 | gk20a_err(dev_from_gk20a(g), | 451 | gk20a_err(dev_from_gk20a(g), |
422 | "fail to allocate gr ctx buffer"); | 452 | "fail to allocate gr ctx buffer"); |
@@ -785,7 +815,7 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g) | |||
785 | if (err) | 815 | if (err) |
786 | goto clean_up; | 816 | goto clean_up; |
787 | 817 | ||
788 | err = vgpu_gr_init_ctx_state(g, gr); | 818 | err = g->ops.gr.init_ctx_state(g); |
789 | if (err) | 819 | if (err) |
790 | goto clean_up; | 820 | goto clean_up; |
791 | 821 | ||
@@ -894,6 +924,8 @@ void vgpu_init_gr_ops(struct gpu_ops *gops) | |||
894 | gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx; | 924 | gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx; |
895 | gops->gr.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx; | 925 | gops->gr.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx; |
896 | gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx; | 926 | gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx; |
927 | gops->gr.alloc_gr_ctx = vgpu_gr_alloc_gr_ctx; | ||
928 | gops->gr.free_gr_ctx = vgpu_gr_free_gr_ctx; | ||
897 | gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull; | 929 | gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull; |
898 | gops->gr.get_zcull_info = vgpu_gr_get_zcull_info; | 930 | gops->gr.get_zcull_info = vgpu_gr_get_zcull_info; |
899 | gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask; | 931 | gops->gr.get_gpc_tpc_mask = vgpu_gr_get_gpc_tpc_mask; |
@@ -904,4 +936,5 @@ void vgpu_init_gr_ops(struct gpu_ops *gops) | |||
904 | gops->gr.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask; | 936 | gops->gr.get_rop_l2_en_mask = vgpu_gr_rop_l2_en_mask; |
905 | gops->gr.zbc_set_table = vgpu_gr_add_zbc; | 937 | gops->gr.zbc_set_table = vgpu_gr_add_zbc; |
906 | gops->gr.zbc_query_table = vgpu_gr_query_zbc; | 938 | gops->gr.zbc_query_table = vgpu_gr_query_zbc; |
939 | gops->gr.init_ctx_state = vgpu_gr_init_ctx_state; | ||
907 | } | 940 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h index f1590593..ffb863cd 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/vgpu.h | |||
@@ -29,6 +29,14 @@ u64 vgpu_bar1_map(struct gk20a *g, struct sg_table **sgt, u64 size); | |||
29 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); | 29 | int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info); |
30 | int vgpu_gr_nonstall_isr(struct gk20a *g, | 30 | int vgpu_gr_nonstall_isr(struct gk20a *g, |
31 | struct tegra_vgpu_gr_nonstall_intr_info *info); | 31 | struct tegra_vgpu_gr_nonstall_intr_info *info); |
32 | int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
33 | struct gr_ctx_desc **__gr_ctx, | ||
34 | struct vm_gk20a *vm, | ||
35 | u32 class, | ||
36 | u32 flags); | ||
37 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
38 | struct gr_ctx_desc *gr_ctx); | ||
39 | int vgpu_gr_init_ctx_state(struct gk20a *g); | ||
32 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); | 40 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); |
33 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | 41 | int vgpu_fifo_nonstall_isr(struct gk20a *g, |
34 | struct tegra_vgpu_fifo_nonstall_intr_info *info); | 42 | struct tegra_vgpu_fifo_nonstall_intr_info *info); |
@@ -77,6 +85,22 @@ static inline int vgpu_gr_isr(struct gk20a *g, | |||
77 | { | 85 | { |
78 | return 0; | 86 | return 0; |
79 | } | 87 | } |
88 | static inline int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | ||
89 | struct gr_ctx_desc **__gr_ctx, | ||
90 | struct vm_gk20a *vm, | ||
91 | u32 class, | ||
92 | u32 flags) | ||
93 | { | ||
94 | return -ENOSYS; | ||
95 | } | ||
96 | static inline void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | ||
97 | struct gr_ctx_desc *gr_ctx) | ||
98 | { | ||
99 | } | ||
100 | static inline int vgpu_gr_init_ctx_state(struct gk20a *g) | ||
101 | { | ||
102 | return -ENOSYS; | ||
103 | } | ||
80 | static inline int vgpu_fifo_isr(struct gk20a *g, | 104 | static inline int vgpu_fifo_isr(struct gk20a *g, |
81 | struct tegra_vgpu_fifo_intr_info *info) | 105 | struct tegra_vgpu_fifo_intr_info *info) |
82 | { | 106 | { |