diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/bus_gk20a.c | 54 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h | 12 |
2 files changed, 43 insertions, 23 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c index 9b031bbf..ba4cfcbe 100644 --- a/drivers/gpu/nvgpu/gk20a/bus_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/bus_gk20a.c | |||
@@ -62,37 +62,45 @@ void gk20a_bus_init_hw(struct gk20a *g) | |||
62 | 62 | ||
63 | void gk20a_bus_isr(struct gk20a *g) | 63 | void gk20a_bus_isr(struct gk20a *g) |
64 | { | 64 | { |
65 | u32 val, err_code; | 65 | u32 val, save0, save1, err_code; |
66 | |||
66 | val = gk20a_readl(g, bus_intr_0_r()); | 67 | val = gk20a_readl(g, bus_intr_0_r()); |
68 | |||
67 | if (val & (bus_intr_0_pri_squash_m() | | 69 | if (val & (bus_intr_0_pri_squash_m() | |
68 | bus_intr_0_pri_fecserr_m() | | 70 | bus_intr_0_pri_fecserr_m() | |
69 | bus_intr_0_pri_timeout_m())) { | 71 | bus_intr_0_pri_timeout_m())) { |
70 | gk20a_dbg(gpu_dbg_intr, "pmc_enable : 0x%x", | 72 | |
73 | nvgpu_log(g, gpu_dbg_intr, "pmc_enable : 0x%x", | ||
71 | gk20a_readl(g, mc_enable_r())); | 74 | gk20a_readl(g, mc_enable_r())); |
72 | gk20a_dbg(gpu_dbg_intr, "NV_PBUS_INTR_0 : 0x%x", val); | 75 | |
73 | gk20a_dbg(gpu_dbg_intr, | 76 | save0 = gk20a_readl(g, timer_pri_timeout_save_0_r()); |
74 | "NV_PTIMER_PRI_TIMEOUT_SAVE_0: 0x%x\n", | 77 | if (timer_pri_timeout_save_0_fecs_tgt_v(save0)) { |
75 | gk20a_readl(g, timer_pri_timeout_save_0_r())); | 78 | |
76 | gk20a_dbg(gpu_dbg_intr, | 79 | err_code = gk20a_readl(g, |
77 | "NV_PTIMER_PRI_TIMEOUT_SAVE_1: 0x%x\n", | 80 | timer_pri_timeout_fecs_errcode_r()); |
78 | gk20a_readl(g, timer_pri_timeout_save_1_r())); | 81 | /* write and addr fields are not reliable */ |
79 | err_code = gk20a_readl(g, timer_pri_timeout_fecs_errcode_r()); | 82 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x " |
80 | gk20a_dbg(gpu_dbg_intr, | 83 | "FECS_ERRCODE 0x%08x", val, err_code); |
81 | "NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE: 0x%x\n", | 84 | |
82 | err_code); | 85 | if ((err_code & 0xffffff00) == 0xbadf1300) |
83 | if (err_code == 0xbadf13) | 86 | nvgpu_err(g, "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: " |
84 | gk20a_dbg(gpu_dbg_intr, | 87 | "0x%08x", |
85 | "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: 0x%x\n", | 88 | gk20a_readl(g, gr_gpc0_fs_gpc_r())); |
86 | gk20a_readl(g, gr_gpc0_fs_gpc_r())); | 89 | } else { |
90 | save1 = gk20a_readl(g, timer_pri_timeout_save_1_r()); | ||
91 | nvgpu_err(g, "NV_PBUS_INTR_0: 0x%08x ADR 0x%08x " | ||
92 | "R/W %s DATA 0x%08x", | ||
93 | val, | ||
94 | timer_pri_timeout_save_0_addr_v(save0) << 2, | ||
95 | timer_pri_timeout_save_0_write_v(save0) ? | ||
96 | "WRITE" : "READ", save1); | ||
97 | } | ||
87 | 98 | ||
88 | gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); | 99 | gk20a_writel(g, timer_pri_timeout_save_0_r(), 0); |
89 | gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); | 100 | gk20a_writel(g, timer_pri_timeout_save_1_r(), 0); |
101 | } else { | ||
102 | nvgpu_err(g, "Unhandled NV_PBUS_INTR_0: 0x%08x", val); | ||
90 | } | 103 | } |
91 | |||
92 | if (val) | ||
93 | gk20a_dbg(gpu_dbg_intr, | ||
94 | "Unhandled pending pbus interrupt\n"); | ||
95 | |||
96 | gk20a_writel(g, bus_intr_0_r(), val); | 104 | gk20a_writel(g, bus_intr_0_r(), val); |
97 | } | 105 | } |
98 | 106 | ||
@@ -141,7 +149,7 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) | |||
141 | u64 iova = nvgpu_inst_block_addr(g, bar1_inst); | 149 | u64 iova = nvgpu_inst_block_addr(g, bar1_inst); |
142 | u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v()); | 150 | u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v()); |
143 | 151 | ||
144 | gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v); | 152 | nvgpu_log(g, gpu_dbg_info, "bar1 inst block ptr: 0x%08x", ptr_v); |
145 | 153 | ||
146 | gk20a_writel(g, bus_bar1_block_r(), | 154 | gk20a_writel(g, bus_bar1_block_r(), |
147 | nvgpu_aperture_mask(g, bar1_inst, | 155 | nvgpu_aperture_mask(g, bar1_inst, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h index 853227fe..f0dbfc30 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h | |||
@@ -96,6 +96,18 @@ static inline u32 timer_pri_timeout_save_0_r(void) | |||
96 | { | 96 | { |
97 | return 0x00009084U; | 97 | return 0x00009084U; |
98 | } | 98 | } |
99 | static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r) | ||
100 | { | ||
101 | return (r >> 31) & 0x1; | ||
102 | } | ||
103 | static inline u32 timer_pri_timeout_save_0_addr_v(u32 r) | ||
104 | { | ||
105 | return (r >> 2) & 0x3fffff; | ||
106 | } | ||
107 | static inline u32 timer_pri_timeout_save_0_write_v(u32 r) | ||
108 | { | ||
109 | return (r >> 1) & 0x1; | ||
110 | } | ||
99 | static inline u32 timer_pri_timeout_save_1_r(void) | 111 | static inline u32 timer_pri_timeout_save_1_r(void) |
100 | { | 112 | { |
101 | return 0x00009088U; | 113 | return 0x00009088U; |