diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 52 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.h | 4 |
3 files changed, 59 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index f1b498ca..02a5e87e 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU Graphics | 2 | * Virtualized GPU Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -837,6 +837,9 @@ static void vgpu_remove_gr_support(struct gr_gk20a *gr) | |||
837 | 837 | ||
838 | gk20a_comptag_allocator_destroy(&gr->comp_tags); | 838 | gk20a_comptag_allocator_destroy(&gr->comp_tags); |
839 | 839 | ||
840 | kfree(gr->sm_error_states); | ||
841 | gr->sm_error_states = NULL; | ||
842 | |||
840 | kfree(gr->gpc_tpc_mask); | 843 | kfree(gr->gpc_tpc_mask); |
841 | gr->gpc_tpc_mask = NULL; | 844 | gr->gpc_tpc_mask = NULL; |
842 | 845 | ||
@@ -883,6 +886,14 @@ static int vgpu_gr_init_gr_setup_sw(struct gk20a *g) | |||
883 | 886 | ||
884 | mutex_init(&gr->ctx_mutex); | 887 | mutex_init(&gr->ctx_mutex); |
885 | 888 | ||
889 | gr->sm_error_states = kzalloc( | ||
890 | sizeof(struct nvgpu_dbg_gpu_sm_error_state_record) * | ||
891 | gr->no_of_sm, GFP_KERNEL); | ||
892 | if (!gr->sm_error_states) { | ||
893 | err = -ENOMEM; | ||
894 | goto clean_up; | ||
895 | } | ||
896 | |||
886 | gr->remove_support = vgpu_remove_gr_support; | 897 | gr->remove_support = vgpu_remove_gr_support; |
887 | gr->sw_ready = true; | 898 | gr->sw_ready = true; |
888 | 899 | ||
@@ -1061,6 +1072,44 @@ static int vgpu_gr_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1061 | return err ? err : msg.ret; | 1072 | return err ? err : msg.ret; |
1062 | } | 1073 | } |
1063 | 1074 | ||
1075 | static int vgpu_gr_clear_sm_error_state(struct gk20a *g, | ||
1076 | struct channel_gk20a *ch, u32 sm_id) | ||
1077 | { | ||
1078 | struct gr_gk20a *gr = &g->gr; | ||
1079 | |||
1080 | mutex_lock(&g->dbg_sessions_lock); | ||
1081 | memset(&gr->sm_error_states[sm_id], 0, sizeof(*gr->sm_error_states)); | ||
1082 | mutex_unlock(&g->dbg_sessions_lock); | ||
1083 | |||
1084 | return 0; | ||
1085 | } | ||
1086 | |||
1087 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | ||
1088 | struct tegra_vgpu_sm_esr_info *info) | ||
1089 | { | ||
1090 | struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_states; | ||
1091 | |||
1092 | if (info->sm_id >= g->gr.no_of_sm) { | ||
1093 | gk20a_err(g->dev, "invalid smd_id %d / %d", | ||
1094 | info->sm_id, g->gr.no_of_sm); | ||
1095 | return; | ||
1096 | } | ||
1097 | |||
1098 | mutex_lock(&g->dbg_sessions_lock); | ||
1099 | |||
1100 | sm_error_states = &g->gr.sm_error_states[info->sm_id]; | ||
1101 | |||
1102 | sm_error_states->hww_global_esr = info->hww_global_esr; | ||
1103 | sm_error_states->hww_warp_esr = info->hww_warp_esr; | ||
1104 | sm_error_states->hww_warp_esr_pc = info->hww_warp_esr_pc; | ||
1105 | sm_error_states->hww_global_esr_report_mask = | ||
1106 | info->hww_global_esr_report_mask; | ||
1107 | sm_error_states->hww_warp_esr_report_mask = | ||
1108 | info->hww_warp_esr_report_mask; | ||
1109 | |||
1110 | mutex_unlock(&g->dbg_sessions_lock); | ||
1111 | } | ||
1112 | |||
1064 | void vgpu_init_gr_ops(struct gpu_ops *gops) | 1113 | void vgpu_init_gr_ops(struct gpu_ops *gops) |
1065 | { | 1114 | { |
1066 | gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch; | 1115 | gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch; |
@@ -1082,5 +1131,6 @@ void vgpu_init_gr_ops(struct gpu_ops *gops) | |||
1082 | gops->gr.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode; | 1131 | gops->gr.set_sm_debug_mode = vgpu_gr_set_sm_debug_mode; |
1083 | gops->gr.update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode; | 1132 | gops->gr.update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode; |
1084 | gops->gr.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode; | 1133 | gops->gr.update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode; |
1134 | gops->gr.clear_sm_error_state = vgpu_gr_clear_sm_error_state; | ||
1085 | gops->gr.dump_gr_regs = NULL; | 1135 | gops->gr.dump_gr_regs = NULL; |
1086 | } | 1136 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index da79de9d..c3dba7d1 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -128,6 +128,8 @@ static void vgpu_handle_channel_event(struct gk20a *g, | |||
128 | } | 128 | } |
129 | } | 129 | } |
130 | 130 | ||
131 | |||
132 | |||
131 | static int vgpu_intr_thread(void *dev_id) | 133 | static int vgpu_intr_thread(void *dev_id) |
132 | { | 134 | { |
133 | struct gk20a *g = dev_id; | 135 | struct gk20a *g = dev_id; |
@@ -174,6 +176,9 @@ static int vgpu_intr_thread(void *dev_id) | |||
174 | case TEGRA_VGPU_EVENT_CHANNEL: | 176 | case TEGRA_VGPU_EVENT_CHANNEL: |
175 | vgpu_handle_channel_event(g, &msg->info.channel_event); | 177 | vgpu_handle_channel_event(g, &msg->info.channel_event); |
176 | break; | 178 | break; |
179 | case TEGRA_VGPU_EVENT_SM_ESR: | ||
180 | vgpu_gr_handle_sm_esr_event(g, &msg->info.sm_esr); | ||
181 | break; | ||
177 | default: | 182 | default: |
178 | gk20a_err(g->dev, "unknown event %u", msg->event); | 183 | gk20a_err(g->dev, "unknown event %u", msg->event); |
179 | break; | 184 | break; |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.h b/drivers/gpu/nvgpu/vgpu/vgpu.h index 4a7a6b6c..e64b31b4 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/vgpu.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Virtualized GPU Interfaces | 2 | * Virtualized GPU Interfaces |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -73,6 +73,8 @@ int vgpu_gr_alloc_gr_ctx(struct gk20a *g, | |||
73 | u32 flags); | 73 | u32 flags); |
74 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, | 74 | void vgpu_gr_free_gr_ctx(struct gk20a *g, struct vm_gk20a *vm, |
75 | struct gr_ctx_desc *gr_ctx); | 75 | struct gr_ctx_desc *gr_ctx); |
76 | void vgpu_gr_handle_sm_esr_event(struct gk20a *g, | ||
77 | struct tegra_vgpu_sm_esr_info *info); | ||
76 | int vgpu_gr_init_ctx_state(struct gk20a *g); | 78 | int vgpu_gr_init_ctx_state(struct gk20a *g); |
77 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); | 79 | int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info); |
78 | int vgpu_fifo_nonstall_isr(struct gk20a *g, | 80 | int vgpu_fifo_nonstall_isr(struct gk20a *g, |