diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 17 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 6 |
13 files changed, 60 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c index bb99e644..0dba3542 100644 --- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.c | |||
@@ -106,6 +106,11 @@ u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp) | |||
106 | return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp)); | 106 | return nvgpu_readl(g, fuse_status_opt_rop_l2_fbp_r(fbp)); |
107 | } | 107 | } |
108 | 108 | ||
109 | u32 gm20b_fuse_status_opt_gpc(struct gk20a *g) | ||
110 | { | ||
111 | return nvgpu_readl(g, fuse_status_opt_gpc_r()); | ||
112 | } | ||
113 | |||
109 | u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc) | 114 | u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc) |
110 | { | 115 | { |
111 | return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc)); | 116 | return nvgpu_readl(g, fuse_status_opt_tpc_gpc_r(gpc)); |
diff --git a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h index 5e2d194b..b22499ad 100644 --- a/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h +++ b/drivers/gpu/nvgpu/common/fuse/fuse_gm20b.h | |||
@@ -36,6 +36,7 @@ int gm20b_fuse_check_priv_security(struct gk20a *g); | |||
36 | u32 gm20b_fuse_status_opt_fbio(struct gk20a *g); | 36 | u32 gm20b_fuse_status_opt_fbio(struct gk20a *g); |
37 | u32 gm20b_fuse_status_opt_fbp(struct gk20a *g); | 37 | u32 gm20b_fuse_status_opt_fbp(struct gk20a *g); |
38 | u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp); | 38 | u32 gm20b_fuse_status_opt_rop_l2_fbp(struct gk20a *g, u32 fbp); |
39 | u32 gm20b_fuse_status_opt_gpc(struct gk20a *g); | ||
39 | u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc); | 40 | u32 gm20b_fuse_status_opt_tpc_gpc(struct gk20a *g, u32 gpc); |
40 | void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val); | 41 | void gm20b_fuse_ctrl_opt_tpc_gpc(struct gk20a *g, u32 gpc, u32 val); |
41 | u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g); | 42 | u32 gm20b_fuse_opt_sec_debug_en(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 368c9321..c67f7870 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -550,6 +550,23 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | |||
550 | ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); | 550 | ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); |
551 | } | 551 | } |
552 | 552 | ||
553 | u32 gr_gm20b_get_gpc_mask(struct gk20a *g) | ||
554 | { | ||
555 | u32 val; | ||
556 | struct gr_gk20a *gr = &g->gr; | ||
557 | |||
558 | /* | ||
559 | * For register NV_FUSE_STATUS_OPT_GPC a set bit with index i indicates | ||
560 | * corresponding GPC is floorswept | ||
561 | * But for s/w mask a set bit means GPC is enabled and it is disabled | ||
562 | * otherwise | ||
563 | * Hence toggle the bits of register value to get s/w mask | ||
564 | */ | ||
565 | val = g->ops.fuse.fuse_status_opt_gpc(g); | ||
566 | |||
567 | return (~val) & (BIT32(gr->max_gpc_count) - 1U); | ||
568 | } | ||
569 | |||
553 | u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 570 | u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
554 | { | 571 | { |
555 | u32 val; | 572 | u32 val; |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 7402478d..084b6157 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -83,6 +83,7 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | |||
83 | u32 *ctrl_register_stride); | 83 | u32 *ctrl_register_stride); |
84 | u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | 84 | u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); |
85 | void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); | 85 | void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index); |
86 | u32 gr_gm20b_get_gpc_mask(struct gk20a *g); | ||
86 | void gr_gm20b_load_tpc_mask(struct gk20a *g); | 87 | void gr_gm20b_load_tpc_mask(struct gk20a *g); |
87 | void gr_gm20b_program_sm_id_numbering(struct gk20a *g, | 88 | void gr_gm20b_program_sm_id_numbering(struct gk20a *g, |
88 | u32 gpc, u32 tpc, u32 smid); | 89 | u32 gpc, u32 tpc, u32 smid); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 3a2fa71d..e8ad68c2 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -293,6 +293,7 @@ static const struct gpu_ops gp106_ops = { | |||
293 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, | 293 | .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments, |
294 | .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, | 294 | .set_gpc_tpc_mask = gr_gp10b_set_gpc_tpc_mask, |
295 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, | 295 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, |
296 | .get_gpc_mask = gr_gm20b_get_gpc_mask, | ||
296 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, | 297 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, |
297 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, | 298 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, |
298 | .get_zcull_info = gr_gk20a_get_zcull_info, | 299 | .get_zcull_info = gr_gk20a_get_zcull_info, |
@@ -794,6 +795,7 @@ static const struct gpu_ops gp106_ops = { | |||
794 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | 795 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, |
795 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | 796 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, |
796 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | 797 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, |
798 | .fuse_status_opt_gpc = gm20b_fuse_status_opt_gpc, | ||
797 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | 799 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, |
798 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | 800 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, |
799 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | 801 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 99ee2d10..6d37f4a2 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -330,6 +330,7 @@ static const struct gpu_ops gv100_ops = { | |||
330 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, | 330 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, |
331 | .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask, | 331 | .set_gpc_tpc_mask = gr_gv100_set_gpc_tpc_mask, |
332 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, | 332 | .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask, |
333 | .get_gpc_mask = gr_gm20b_get_gpc_mask, | ||
333 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, | 334 | .alloc_obj_ctx = gk20a_alloc_obj_ctx, |
334 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, | 335 | .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull, |
335 | .get_zcull_info = gr_gk20a_get_zcull_info, | 336 | .get_zcull_info = gr_gk20a_get_zcull_info, |
@@ -887,6 +888,7 @@ static const struct gpu_ops gv100_ops = { | |||
887 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, | 888 | .fuse_status_opt_fbio = gm20b_fuse_status_opt_fbio, |
888 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, | 889 | .fuse_status_opt_fbp = gm20b_fuse_status_opt_fbp, |
889 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, | 890 | .fuse_status_opt_rop_l2_fbp = gm20b_fuse_status_opt_rop_l2_fbp, |
891 | .fuse_status_opt_gpc = gm20b_fuse_status_opt_gpc, | ||
890 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, | 892 | .fuse_status_opt_tpc_gpc = gm20b_fuse_status_opt_tpc_gpc, |
891 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, | 893 | .fuse_ctrl_opt_tpc_gpc = gm20b_fuse_ctrl_opt_tpc_gpc, |
892 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, | 894 | .fuse_opt_sec_debug_en = gm20b_fuse_opt_sec_debug_en, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index d0f51055..593b553c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -264,6 +264,7 @@ struct gpu_ops { | |||
264 | struct gk20a_ctxsw_ucode_segments *segments, | 264 | struct gk20a_ctxsw_ucode_segments *segments, |
265 | u32 reg_offset); | 265 | u32 reg_offset); |
266 | int (*load_ctxsw_ucode)(struct gk20a *g); | 266 | int (*load_ctxsw_ucode)(struct gk20a *g); |
267 | u32 (*get_gpc_mask)(struct gk20a *g); | ||
267 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | 268 | u32 (*get_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); |
268 | void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); | 269 | void (*set_gpc_tpc_mask)(struct gk20a *g, u32 gpc_index); |
269 | int (*alloc_obj_ctx)(struct channel_gk20a *c, | 270 | int (*alloc_obj_ctx)(struct channel_gk20a *c, |
@@ -1270,6 +1271,7 @@ struct gpu_ops { | |||
1270 | u32 (*fuse_status_opt_fbio)(struct gk20a *g); | 1271 | u32 (*fuse_status_opt_fbio)(struct gk20a *g); |
1271 | u32 (*fuse_status_opt_fbp)(struct gk20a *g); | 1272 | u32 (*fuse_status_opt_fbp)(struct gk20a *g); |
1272 | u32 (*fuse_status_opt_rop_l2_fbp)(struct gk20a *g, u32 fbp); | 1273 | u32 (*fuse_status_opt_rop_l2_fbp)(struct gk20a *g, u32 fbp); |
1274 | u32 (*fuse_status_opt_gpc)(struct gk20a *g); | ||
1273 | u32 (*fuse_status_opt_tpc_gpc)(struct gk20a *g, u32 gpc); | 1275 | u32 (*fuse_status_opt_tpc_gpc)(struct gk20a *g, u32 gpc); |
1274 | void (*fuse_ctrl_opt_tpc_gpc)(struct gk20a *g, u32 gpc, u32 val); | 1276 | void (*fuse_ctrl_opt_tpc_gpc)(struct gk20a *g, u32 gpc, u32 val); |
1275 | u32 (*fuse_opt_sec_debug_en)(struct gk20a *g); | 1277 | u32 (*fuse_opt_sec_debug_en)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h index 99b4b3f3..d97eb7d8 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gm20b/hw_fuse_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -56,6 +56,10 @@ | |||
56 | #ifndef _hw_fuse_gm20b_h_ | 56 | #ifndef _hw_fuse_gm20b_h_ |
57 | #define _hw_fuse_gm20b_h_ | 57 | #define _hw_fuse_gm20b_h_ |
58 | 58 | ||
59 | static inline u32 fuse_status_opt_gpc_r(void) | ||
60 | { | ||
61 | return 0x00021c1cU; | ||
62 | } | ||
59 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) | 63 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) |
60 | { | 64 | { |
61 | return 0x00021c38U + i*4U; | 65 | return 0x00021c38U + i*4U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h index 7d1fb075..bfb19b9b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_fuse_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -56,6 +56,10 @@ | |||
56 | #ifndef _hw_fuse_gp106_h_ | 56 | #ifndef _hw_fuse_gp106_h_ |
57 | #define _hw_fuse_gp106_h_ | 57 | #define _hw_fuse_gp106_h_ |
58 | 58 | ||
59 | static inline u32 fuse_status_opt_gpc_r(void) | ||
60 | { | ||
61 | return 0x00021c1cU; | ||
62 | } | ||
59 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) | 63 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) |
60 | { | 64 | { |
61 | return 0x00021c38U + i*4U; | 65 | return 0x00021c38U + i*4U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h index 29107fb8..521dcfe2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fuse_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -56,6 +56,10 @@ | |||
56 | #ifndef _hw_fuse_gp10b_h_ | 56 | #ifndef _hw_fuse_gp10b_h_ |
57 | #define _hw_fuse_gp10b_h_ | 57 | #define _hw_fuse_gp10b_h_ |
58 | 58 | ||
59 | static inline u32 fuse_status_opt_gpc_r(void) | ||
60 | { | ||
61 | return 0x00021c1cU; | ||
62 | } | ||
59 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) | 63 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) |
60 | { | 64 | { |
61 | return 0x00021c38U + i*4U; | 65 | return 0x00021c38U + i*4U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h index f7eacd29..48194ea9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_fuse_gv100.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -56,6 +56,10 @@ | |||
56 | #ifndef _hw_fuse_gv100_h_ | 56 | #ifndef _hw_fuse_gv100_h_ |
57 | #define _hw_fuse_gv100_h_ | 57 | #define _hw_fuse_gv100_h_ |
58 | 58 | ||
59 | static inline u32 fuse_status_opt_gpc_r(void) | ||
60 | { | ||
61 | return 0x00021c1cU; | ||
62 | } | ||
59 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) | 63 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) |
60 | { | 64 | { |
61 | return 0x00021c38U + i*4U; | 65 | return 0x00021c38U + i*4U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h index f8d9b196..9395da3f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_fuse_gv11b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -56,6 +56,10 @@ | |||
56 | #ifndef _hw_fuse_gv11b_h_ | 56 | #ifndef _hw_fuse_gv11b_h_ |
57 | #define _hw_fuse_gv11b_h_ | 57 | #define _hw_fuse_gv11b_h_ |
58 | 58 | ||
59 | static inline u32 fuse_status_opt_gpc_r(void) | ||
60 | { | ||
61 | return 0x00021c1cU; | ||
62 | } | ||
59 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) | 63 | static inline u32 fuse_status_opt_tpc_gpc_r(u32 i) |
60 | { | 64 | { |
61 | return 0x00021c38U + i*4U; | 65 | return 0x00021c38U + i*4U; |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index 19b4286d..e8ed63f4 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | |||
@@ -262,7 +262,11 @@ gk20a_ctrl_ioctl_gpu_characteristics( | |||
262 | 262 | ||
263 | gpu.compression_page_size = g->ops.fb.compression_page_size(g); | 263 | gpu.compression_page_size = g->ops.fb.compression_page_size(g); |
264 | 264 | ||
265 | gpu.gpc_mask = (1 << g->gr.gpc_count)-1; | 265 | if (g->ops.gr.get_gpc_mask) { |
266 | gpu.gpc_mask = g->ops.gr.get_gpc_mask(g); | ||
267 | } else { | ||
268 | gpu.gpc_mask = BIT32(g->gr.gpc_count) - 1; | ||
269 | } | ||
266 | 270 | ||
267 | gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); | 271 | gpu.flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); |
268 | 272 | ||