diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gm20b.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gm20b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gv100.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gv100.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/tsg.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 |
12 files changed, 71 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c index f62bf9df..739274c5 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -311,7 +311,7 @@ bool gm20b_fb_debug_mode_enabled(struct gk20a *g) | |||
311 | fb_mmu_debug_ctrl_debug_enabled_v(); | 311 | fb_mmu_debug_ctrl_debug_enabled_v(); |
312 | } | 312 | } |
313 | 313 | ||
314 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | 314 | void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable) |
315 | { | 315 | { |
316 | u32 reg_val, fb_debug_ctrl; | 316 | u32 reg_val, fb_debug_ctrl; |
317 | 317 | ||
@@ -323,10 +323,15 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | |||
323 | g->mmu_debug_ctrl = false; | 323 | g->mmu_debug_ctrl = false; |
324 | } | 324 | } |
325 | 325 | ||
326 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | 326 | reg_val = nvgpu_readl(g, fb_mmu_debug_ctrl_r()); |
327 | reg_val = set_field(reg_val, | 327 | reg_val = set_field(reg_val, |
328 | fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); | 328 | fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); |
329 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | 329 | nvgpu_writel(g, fb_mmu_debug_ctrl_r(), reg_val); |
330 | } | ||
330 | 331 | ||
332 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | ||
333 | { | ||
334 | gm20b_fb_set_mmu_debug_mode(g, enable); | ||
331 | g->ops.gr.set_debug_mode(g, enable); | 335 | g->ops.gr.set_debug_mode(g, enable); |
332 | } | 336 | } |
337 | |||
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.h b/drivers/gpu/nvgpu/common/fb/fb_gm20b.h index d69f8618..aed9b43e 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.h +++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B FB | 2 | * GM20B FB |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -49,5 +49,6 @@ void gm20b_fb_read_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf); | |||
49 | int gm20b_fb_vpr_info_fetch(struct gk20a *g); | 49 | int gm20b_fb_vpr_info_fetch(struct gk20a *g); |
50 | bool gm20b_fb_debug_mode_enabled(struct gk20a *g); | 50 | bool gm20b_fb_debug_mode_enabled(struct gk20a *g); |
51 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable); | 51 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable); |
52 | void gm20b_fb_set_mmu_debug_mode(struct gk20a *g, bool enable); | ||
52 | 53 | ||
53 | #endif | 54 | #endif |
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.c b/drivers/gpu/nvgpu/common/fb/fb_gv100.c index 193cf2f0..508259e7 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 FB | 2 | * GV100 FB |
3 | * | 3 | * |
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -300,3 +300,27 @@ size_t gv100_fb_get_vidmem_size(struct gk20a *g) | |||
300 | 300 | ||
301 | return bytes; | 301 | return bytes; |
302 | } | 302 | } |
303 | |||
304 | void gv100_fb_set_mmu_debug_mode(struct gk20a *g, bool enable) | ||
305 | { | ||
306 | u32 data, fb_ctrl, hsmmu_ctrl; | ||
307 | |||
308 | if (enable) { | ||
309 | fb_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
310 | hsmmu_ctrl = fb_hsmmu_pri_mmu_debug_ctrl_debug_enabled_f(); | ||
311 | g->mmu_debug_ctrl = true; | ||
312 | } else { | ||
313 | fb_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
314 | hsmmu_ctrl = fb_hsmmu_pri_mmu_debug_ctrl_debug_disabled_f(); | ||
315 | g->mmu_debug_ctrl = false; | ||
316 | } | ||
317 | |||
318 | data = nvgpu_readl(g, fb_mmu_debug_ctrl_r()); | ||
319 | data = set_field(data, fb_mmu_debug_ctrl_debug_m(), fb_ctrl); | ||
320 | nvgpu_writel(g, fb_mmu_debug_ctrl_r(), data); | ||
321 | |||
322 | data = nvgpu_readl(g, fb_hsmmu_pri_mmu_debug_ctrl_r()); | ||
323 | data = set_field(data, | ||
324 | fb_hsmmu_pri_mmu_debug_ctrl_debug_m(), hsmmu_ctrl); | ||
325 | nvgpu_writel(g, fb_hsmmu_pri_mmu_debug_ctrl_r(), data); | ||
326 | } | ||
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv100.h b/drivers/gpu/nvgpu/common/fb/fb_gv100.h index 161d4cd7..b83f664a 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv100.h +++ b/drivers/gpu/nvgpu/common/fb/fb_gv100.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 FB | 2 | * GV100 FB |
3 | * | 3 | * |
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -34,5 +34,6 @@ int gv100_fb_memory_unlock(struct gk20a *g); | |||
34 | int gv100_fb_init_nvlink(struct gk20a *g); | 34 | int gv100_fb_init_nvlink(struct gk20a *g); |
35 | int gv100_fb_enable_nvlink(struct gk20a *g); | 35 | int gv100_fb_enable_nvlink(struct gk20a *g); |
36 | size_t gv100_fb_get_vidmem_size(struct gk20a *g); | 36 | size_t gv100_fb_get_vidmem_size(struct gk20a *g); |
37 | void gv100_fb_set_mmu_debug_mode(struct gk20a *g, bool enable); | ||
37 | 38 | ||
38 | #endif /* NVGPU_FB_GV100_H */ | 39 | #endif /* NVGPU_FB_GV100_H */ |
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 5883667f..7f61b273 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c | |||
@@ -452,13 +452,15 @@ int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, | |||
452 | struct gk20a *g; | 452 | struct gk20a *g; |
453 | int err = 0; | 453 | int err = 0; |
454 | u32 tsg_refcnt; | 454 | u32 tsg_refcnt; |
455 | u32 fb_refcnt; | ||
455 | 456 | ||
456 | if ((ch == NULL) || (tsg == NULL)) { | 457 | if ((ch == NULL) || (tsg == NULL)) { |
457 | return -EINVAL; | 458 | return -EINVAL; |
458 | } | 459 | } |
459 | g = ch->g; | 460 | g = ch->g; |
460 | 461 | ||
461 | if (g->ops.gr.set_mmu_debug_mode == NULL) { | 462 | if ((g->ops.fb.set_mmu_debug_mode == NULL) && |
463 | (g->ops.gr.set_mmu_debug_mode == NULL)) { | ||
462 | return -ENOSYS; | 464 | return -ENOSYS; |
463 | } | 465 | } |
464 | 466 | ||
@@ -468,26 +470,39 @@ int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, | |||
468 | return 0; | 470 | return 0; |
469 | } | 471 | } |
470 | tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U; | 472 | tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U; |
473 | fb_refcnt = g->mmu_debug_mode_refcnt + 1U; | ||
471 | } else { | 474 | } else { |
472 | if (!ch->mmu_debug_mode_enabled) { | 475 | if (!ch->mmu_debug_mode_enabled) { |
473 | /* already disabled for this channel */ | 476 | /* already disabled for this channel */ |
474 | return 0; | 477 | return 0; |
475 | } | 478 | } |
476 | tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U; | 479 | tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U; |
480 | fb_refcnt = g->mmu_debug_mode_refcnt - 1U; | ||
477 | } | 481 | } |
478 | 482 | ||
479 | /* | 483 | if (g->ops.gr.set_mmu_debug_mode != NULL) { |
480 | * enable GPC MMU debug mode if it was requested for at | 484 | /* |
481 | * least one channel in the TSG | 485 | * enable GPC MMU debug mode if it was requested for at |
482 | */ | 486 | * least one channel in the TSG |
483 | err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U); | 487 | */ |
484 | if (err != 0) { | 488 | err = g->ops.gr.set_mmu_debug_mode(g, ch, tsg_refcnt > 0U); |
485 | nvgpu_err(g, "set mmu debug mode failed, err=%d", err); | 489 | if (err != 0) { |
486 | return err; | 490 | nvgpu_err(g, "set mmu debug mode failed, err=%d", err); |
491 | return err; | ||
492 | } | ||
493 | } | ||
494 | |||
495 | if (g->ops.fb.set_mmu_debug_mode != NULL) { | ||
496 | /* | ||
497 | * enable FB/HS MMU debug mode if it was requested for | ||
498 | * at least one TSG | ||
499 | */ | ||
500 | g->ops.fb.set_mmu_debug_mode(g, fb_refcnt > 0U); | ||
487 | } | 501 | } |
488 | 502 | ||
489 | ch->mmu_debug_mode_enabled = enable; | 503 | ch->mmu_debug_mode_enabled = enable; |
490 | tsg->mmu_debug_mode_refcnt = tsg_refcnt; | 504 | tsg->mmu_debug_mode_refcnt = tsg_refcnt; |
505 | g->mmu_debug_mode_refcnt = fb_refcnt; | ||
491 | 506 | ||
492 | return err; | 507 | return err; |
493 | } | 508 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 0865ace4..9898c683 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -352,6 +352,7 @@ static const struct gpu_ops gm20b_ops = { | |||
352 | .read_wpr_info = gm20b_fb_read_wpr_info, | 352 | .read_wpr_info = gm20b_fb_read_wpr_info, |
353 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, | 353 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, |
354 | .set_debug_mode = gm20b_fb_set_debug_mode, | 354 | .set_debug_mode = gm20b_fb_set_debug_mode, |
355 | .set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode, | ||
355 | .tlb_invalidate = gm20b_fb_tlb_invalidate, | 356 | .tlb_invalidate = gm20b_fb_tlb_invalidate, |
356 | .mem_unlock = NULL, | 357 | .mem_unlock = NULL, |
357 | }, | 358 | }, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index eea40d5e..3cdba8ac 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -386,6 +386,7 @@ static const struct gpu_ops gp10b_ops = { | |||
386 | .read_wpr_info = gm20b_fb_read_wpr_info, | 386 | .read_wpr_info = gm20b_fb_read_wpr_info, |
387 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, | 387 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, |
388 | .set_debug_mode = gm20b_fb_set_debug_mode, | 388 | .set_debug_mode = gm20b_fb_set_debug_mode, |
389 | .set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode, | ||
389 | .tlb_invalidate = gm20b_fb_tlb_invalidate, | 390 | .tlb_invalidate = gm20b_fb_tlb_invalidate, |
390 | .mem_unlock = NULL, | 391 | .mem_unlock = NULL, |
391 | }, | 392 | }, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2e2c3b8f..f7fabf68 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -473,6 +473,7 @@ static const struct gpu_ops gv11b_ops = { | |||
473 | .read_wpr_info = gm20b_fb_read_wpr_info, | 473 | .read_wpr_info = gm20b_fb_read_wpr_info, |
474 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, | 474 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, |
475 | .set_debug_mode = gm20b_fb_set_debug_mode, | 475 | .set_debug_mode = gm20b_fb_set_debug_mode, |
476 | .set_mmu_debug_mode = gm20b_fb_set_mmu_debug_mode, | ||
476 | .tlb_invalidate = gm20b_fb_tlb_invalidate, | 477 | .tlb_invalidate = gm20b_fb_tlb_invalidate, |
477 | .hub_isr = gv11b_fb_hub_isr, | 478 | .hub_isr = gv11b_fb_hub_isr, |
478 | .handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault, | 479 | .handle_replayable_fault = gv11b_fb_handle_replayable_mmu_fault, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index f3a83602..8b6de266 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -570,6 +570,7 @@ struct gpu_ops { | |||
570 | struct wpr_carveout_info *inf); | 570 | struct wpr_carveout_info *inf); |
571 | bool (*is_debug_mode_enabled)(struct gk20a *g); | 571 | bool (*is_debug_mode_enabled)(struct gk20a *g); |
572 | void (*set_debug_mode)(struct gk20a *g, bool enable); | 572 | void (*set_debug_mode)(struct gk20a *g, bool enable); |
573 | void (*set_mmu_debug_mode)(struct gk20a *g, bool enable); | ||
573 | int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); | 574 | int (*tlb_invalidate)(struct gk20a *g, struct nvgpu_mem *pdb); |
574 | void (*hub_isr)(struct gk20a *g); | 575 | void (*hub_isr)(struct gk20a *g); |
575 | void (*handle_replayable_fault)(struct gk20a *g); | 576 | void (*handle_replayable_fault)(struct gk20a *g); |
@@ -1623,6 +1624,7 @@ struct gk20a { | |||
1623 | struct gk20a_fecs_trace *fecs_trace; | 1624 | struct gk20a_fecs_trace *fecs_trace; |
1624 | 1625 | ||
1625 | bool mmu_debug_ctrl; | 1626 | bool mmu_debug_ctrl; |
1627 | u32 mmu_debug_mode_refcnt; | ||
1626 | 1628 | ||
1627 | u32 tpc_fs_mask_user; | 1629 | u32 tpc_fs_mask_user; |
1628 | 1630 | ||
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 408bbc64..aeed07ce 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -1091,7 +1091,8 @@ static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( | |||
1091 | return -EINVAL; | 1091 | return -EINVAL; |
1092 | } | 1092 | } |
1093 | 1093 | ||
1094 | if (g->ops.gr.set_mmu_debug_mode == NULL) { | 1094 | if ((g->ops.fb.set_mmu_debug_mode == NULL) && |
1095 | (g->ops.gr.set_mmu_debug_mode == NULL)) { | ||
1095 | return -ENOSYS; | 1096 | return -ENOSYS; |
1096 | } | 1097 | } |
1097 | 1098 | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 917ac638..a4f02faa 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -250,6 +250,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
250 | .read_wpr_info = NULL, | 250 | .read_wpr_info = NULL, |
251 | .is_debug_mode_enabled = NULL, | 251 | .is_debug_mode_enabled = NULL, |
252 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | 252 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, |
253 | .set_mmu_debug_mode = NULL, | ||
253 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | 254 | .tlb_invalidate = vgpu_mm_tlb_invalidate, |
254 | }, | 255 | }, |
255 | .clock_gating = { | 256 | .clock_gating = { |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 41850c91..f51d4c35 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -291,6 +291,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
291 | .read_wpr_info = NULL, | 291 | .read_wpr_info = NULL, |
292 | .is_debug_mode_enabled = NULL, | 292 | .is_debug_mode_enabled = NULL, |
293 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, | 293 | .set_debug_mode = vgpu_mm_mmu_set_debug_mode, |
294 | .set_mmu_debug_mode = NULL, | ||
294 | .tlb_invalidate = vgpu_mm_tlb_invalidate, | 295 | .tlb_invalidate = vgpu_mm_tlb_invalidate, |
295 | .hub_isr = gv11b_fb_hub_isr, | 296 | .hub_isr = gv11b_fb_hub_isr, |
296 | .enable_hub_intr = gv11b_fb_enable_hub_intr, | 297 | .enable_hub_intr = gv11b_fb_enable_hub_intr, |