diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 56 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 3 |
14 files changed, 107 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c67f7870..d00181af 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -33,6 +33,7 @@ | |||
33 | #include <nvgpu/channel.h> | 33 | #include <nvgpu/channel.h> |
34 | 34 | ||
35 | #include "gk20a/gr_gk20a.h" | 35 | #include "gk20a/gr_gk20a.h" |
36 | #include "gk20a/regops_gk20a.h" | ||
36 | 37 | ||
37 | #include "gr_gm20b.h" | 38 | #include "gr_gm20b.h" |
38 | #include "pmu_gm20b.h" | 39 | #include "pmu_gm20b.h" |
@@ -1455,6 +1456,26 @@ u32 gr_gm20b_get_pmm_per_chiplet_offset(void) | |||
1455 | return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); | 1456 | return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); |
1456 | } | 1457 | } |
1457 | 1458 | ||
1459 | int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, | ||
1460 | struct channel_gk20a *ch, bool enable) | ||
1461 | { | ||
1462 | struct nvgpu_dbg_reg_op ctx_ops = { | ||
1463 | .op = REGOP(WRITE_32), | ||
1464 | .type = REGOP(TYPE_GR_CTX), | ||
1465 | .offset = gr_gpcs_pri_mmu_debug_ctrl_r(), | ||
1466 | .value_lo = enable ? | ||
1467 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f() : | ||
1468 | gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(), | ||
1469 | }; | ||
1470 | int err; | ||
1471 | |||
1472 | err = gr_gk20a_exec_ctx_ops(ch, &ctx_ops, 1, 1, 0, NULL); | ||
1473 | if (err != 0) { | ||
1474 | nvgpu_err(g, "Failed to access register"); | ||
1475 | } | ||
1476 | return err; | ||
1477 | } | ||
1478 | |||
1458 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) | 1479 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) |
1459 | { | 1480 | { |
1460 | u32 reg_val, gpc_debug_ctrl; | 1481 | u32 reg_val, gpc_debug_ctrl; |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 084b6157..81916c05 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -125,5 +125,7 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, | |||
125 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 125 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
126 | u32 global_esr); | 126 | u32 global_esr); |
127 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); | 127 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); |
128 | int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, | ||
129 | struct channel_gk20a *ch, bool enable); | ||
128 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); | 130 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); |
129 | #endif /* NVGPU_GM20B_GR_GM20B_H */ | 131 | #endif /* NVGPU_GM20B_GR_GM20B_H */ |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index c978f9aa..0865ace4 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Graphics | 2 | * GM20B Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -277,6 +277,7 @@ static const struct gpu_ops gm20b_ops = { | |||
277 | .get_lrf_tex_ltc_dram_override = NULL, | 277 | .get_lrf_tex_ltc_dram_override = NULL, |
278 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | 278 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, |
279 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 279 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
280 | .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode, | ||
280 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | 281 | .record_sm_error_state = gm20b_gr_record_sm_error_state, |
281 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | 282 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, |
282 | .suspend_contexts = gr_gk20a_suspend_contexts, | 283 | .suspend_contexts = gr_gk20a_suspend_contexts, |
@@ -753,6 +754,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
753 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 754 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
754 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 755 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
755 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); | 756 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); |
757 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | ||
756 | 758 | ||
757 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 759 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
758 | if (gops->fuse.check_priv_security(g)) { | 760 | if (gops->fuse.check_priv_security(g)) { |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 561d24d8..eea40d5e 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Tegra HAL interface | 2 | * GP10B Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -295,6 +295,7 @@ static const struct gpu_ops gp10b_ops = { | |||
295 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, | 295 | .get_lrf_tex_ltc_dram_override = get_ecc_override_val, |
296 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | 296 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, |
297 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 297 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
298 | .set_mmu_debug_mode = NULL, | ||
298 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | 299 | .record_sm_error_state = gm20b_gr_record_sm_error_state, |
299 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | 300 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, |
300 | .suspend_contexts = gr_gp10b_suspend_contexts, | 301 | .suspend_contexts = gr_gp10b_suspend_contexts, |
@@ -783,6 +784,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
783 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 784 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
784 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); | 785 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, false); |
785 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); | 786 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); |
787 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | ||
786 | 788 | ||
787 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | 789 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
788 | if (gops->fuse.check_priv_security(g)) { | 790 | if (gops->fuse.check_priv_security(g)) { |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9a3d2241..0e0417a0 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 Tegra HAL interface | 2 | * GV100 Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -404,6 +404,7 @@ static const struct gpu_ops gv100_ops = { | |||
404 | .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, | 404 | .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, |
405 | .set_pmm_register = gr_gv100_set_pmm_register, | 405 | .set_pmm_register = gr_gv100_set_pmm_register, |
406 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 406 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
407 | .set_mmu_debug_mode = NULL, | ||
407 | .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, | 408 | .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, |
408 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 409 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
409 | .clear_sm_error_state = gv11b_gr_clear_sm_error_state, | 410 | .clear_sm_error_state = gv11b_gr_clear_sm_error_state, |
@@ -1040,6 +1041,7 @@ int gv100_init_hal(struct gk20a *g) | |||
1040 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); | 1041 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); |
1041 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); | 1042 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); |
1042 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); | 1043 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, false); |
1044 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | ||
1043 | 1045 | ||
1044 | /* for now */ | 1046 | /* for now */ |
1045 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 1047 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 68ea78a6..d80bf0f0 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -356,6 +356,7 @@ static const struct gpu_ops gv11b_ops = { | |||
356 | .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, | 356 | .get_num_hwpm_perfmon = gr_gv100_get_num_hwpm_perfmon, |
357 | .set_pmm_register = gr_gv100_set_pmm_register, | 357 | .set_pmm_register = gr_gv100_set_pmm_register, |
358 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 358 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
359 | .set_mmu_debug_mode = gm20b_gr_set_mmu_debug_mode, | ||
359 | .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, | 360 | .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, |
360 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 361 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
361 | .clear_sm_error_state = gv11b_gr_clear_sm_error_state, | 362 | .clear_sm_error_state = gv11b_gr_clear_sm_error_state, |
@@ -955,6 +956,7 @@ int gv11b_init_hal(struct gk20a *g) | |||
955 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | 956 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
956 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); | 957 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_VA, true); |
957 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true); | 958 | __nvgpu_set_enabled(g, NVGPU_FECS_TRACE_FEATURE_CONTROL, true); |
959 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | ||
958 | 960 | ||
959 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); | 961 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MULTIPLE_WPR, false); |
960 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); | 962 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index fc7bab90..77b54ab9 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -181,10 +181,13 @@ struct gk20a; | |||
181 | /* PLATFORM_ATOMIC support */ | 181 | /* PLATFORM_ATOMIC support */ |
182 | #define NVGPU_SUPPORT_PLATFORM_ATOMIC 71 | 182 | #define NVGPU_SUPPORT_PLATFORM_ATOMIC 71 |
183 | 183 | ||
184 | /* NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE is available */ | ||
185 | #define NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE 72 | ||
186 | |||
184 | /* | 187 | /* |
185 | * Must be greater than the largest bit offset in the above list. | 188 | * Must be greater than the largest bit offset in the above list. |
186 | */ | 189 | */ |
187 | #define NVGPU_MAX_ENABLED_BITS 72 | 190 | #define NVGPU_MAX_ENABLED_BITS 73U |
188 | 191 | ||
189 | /** | 192 | /** |
190 | * nvgpu_is_enabled - Check if the passed flag is enabled. | 193 | * nvgpu_is_enabled - Check if the passed flag is enabled. |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index a0af0c5c..f3a83602 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -529,6 +529,8 @@ struct gpu_ops { | |||
529 | u32 num_ppcs, u32 reg_list_ppc_count, | 529 | u32 num_ppcs, u32 reg_list_ppc_count, |
530 | u32 *__offset_in_segment); | 530 | u32 *__offset_in_segment); |
531 | void (*set_debug_mode)(struct gk20a *g, bool enable); | 531 | void (*set_debug_mode)(struct gk20a *g, bool enable); |
532 | int (*set_mmu_debug_mode)(struct gk20a *g, | ||
533 | struct channel_gk20a *ch, bool enable); | ||
532 | } gr; | 534 | } gr; |
533 | struct { | 535 | struct { |
534 | void (*init_hw)(struct gk20a *g); | 536 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index dfa9edf3..8ad304bd 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2018, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2011-2020, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -224,6 +224,8 @@ static struct nvgpu_flags_mapping flags_mapping[] = { | |||
224 | NVGPU_SUPPORT_SCG}, | 224 | NVGPU_SUPPORT_SCG}, |
225 | {NVGPU_GPU_FLAGS_SUPPORT_VPR, | 225 | {NVGPU_GPU_FLAGS_SUPPORT_VPR, |
226 | NVGPU_SUPPORT_VPR}, | 226 | NVGPU_SUPPORT_VPR}, |
227 | {NVGPU_GPU_FLAGS_SUPPORT_SET_CTX_MMU_DEBUG_MODE, | ||
228 | NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE}, | ||
227 | }; | 229 | }; |
228 | 230 | ||
229 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) | 231 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index adf40d5d..f7a65f2b 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger/Profiler Driver | 2 | * Tegra GK20A GPU Debugger/Profiler Driver |
3 | * | 3 | * |
4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -117,6 +117,10 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
117 | static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | 117 | static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, |
118 | struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args); | 118 | struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args); |
119 | 119 | ||
120 | static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( | ||
121 | struct dbg_session_gk20a *dbg_s, | ||
122 | struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *args); | ||
123 | |||
120 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | 124 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( |
121 | struct dbg_session_gk20a *dbg_s, | 125 | struct dbg_session_gk20a *dbg_s, |
122 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args); | 126 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args); |
@@ -1072,6 +1076,51 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
1072 | return err; | 1076 | return err; |
1073 | } | 1077 | } |
1074 | 1078 | ||
1079 | static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode( | ||
1080 | struct dbg_session_gk20a *dbg_s, | ||
1081 | struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *args) | ||
1082 | { | ||
1083 | int err; | ||
1084 | struct gk20a *g = dbg_s->g; | ||
1085 | struct channel_gk20a *ch; | ||
1086 | bool enable = (args->mode == NVGPU_DBG_GPU_CTX_MMU_DEBUG_MODE_ENABLED); | ||
1087 | |||
1088 | nvgpu_log_fn(g, "mode=%u", args->mode); | ||
1089 | |||
1090 | if (args->reserved != 0U) { | ||
1091 | return -EINVAL; | ||
1092 | } | ||
1093 | |||
1094 | if (g->ops.gr.set_mmu_debug_mode == NULL) { | ||
1095 | return -ENOSYS; | ||
1096 | } | ||
1097 | |||
1098 | err = gk20a_busy(g); | ||
1099 | if (err) { | ||
1100 | nvgpu_err(g, "failed to poweron"); | ||
1101 | return err; | ||
1102 | } | ||
1103 | |||
1104 | /* Take the global lock, since we'll be doing global regops */ | ||
1105 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
1106 | |||
1107 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | ||
1108 | if (!ch) { | ||
1109 | nvgpu_err(g, "no bound channel for mmu debug mode"); | ||
1110 | goto clean_up; | ||
1111 | } | ||
1112 | |||
1113 | err = g->ops.gr.set_mmu_debug_mode(g, ch, enable); | ||
1114 | if (err) { | ||
1115 | nvgpu_err(g, "set mmu debug mode failed, err=%d", err); | ||
1116 | } | ||
1117 | |||
1118 | clean_up: | ||
1119 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
1120 | gk20a_idle(g); | ||
1121 | return err; | ||
1122 | } | ||
1123 | |||
1075 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | 1124 | static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( |
1076 | struct dbg_session_gk20a *dbg_s, | 1125 | struct dbg_session_gk20a *dbg_s, |
1077 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args) | 1126 | struct nvgpu_dbg_gpu_suspend_resume_all_sms_args *args) |
@@ -2030,6 +2079,11 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
2030 | (struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *)buf); | 2079 | (struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *)buf); |
2031 | break; | 2080 | break; |
2032 | 2081 | ||
2082 | case NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE: | ||
2083 | err = nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode(dbg_s, | ||
2084 | (struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *)buf); | ||
2085 | break; | ||
2086 | |||
2033 | default: | 2087 | default: |
2034 | nvgpu_err(g, | 2088 | nvgpu_err(g, |
2035 | "unrecognized dbg gpu ioctl cmd: 0x%x", | 2089 | "unrecognized dbg gpu ioctl cmd: 0x%x", |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 7c800d5f..917ac638 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2015-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -234,6 +234,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
234 | .get_offset_in_gpccs_segment = | 234 | .get_offset_in_gpccs_segment = |
235 | gr_gk20a_get_offset_in_gpccs_segment, | 235 | gr_gk20a_get_offset_in_gpccs_segment, |
236 | .set_debug_mode = gm20b_gr_set_debug_mode, | 236 | .set_debug_mode = gm20b_gr_set_debug_mode, |
237 | .set_mmu_debug_mode = NULL, | ||
237 | }, | 238 | }, |
238 | .fb = { | 239 | .fb = { |
239 | .init_hw = NULL, | 240 | .init_hw = NULL, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c index baddae13..2190478e 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_gv11b.c | |||
@@ -44,6 +44,7 @@ int vgpu_gv11b_init_gpu_characteristics(struct gk20a *g) | |||
44 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); | 44 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNCPOINT_ADDRESS, true); |
45 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); | 45 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_USER_SYNCPOINT, true); |
46 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); | 46 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PLATFORM_ATOMIC, true); |
47 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | ||
47 | 48 | ||
48 | return 0; | 49 | return 0; |
49 | } | 50 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 78ea5643..41850c91 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -189,6 +189,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
189 | .get_hw_accessor_stream_out_mode = | 189 | .get_hw_accessor_stream_out_mode = |
190 | gr_gv100_get_hw_accessor_stream_out_mode, | 190 | gr_gv100_get_hw_accessor_stream_out_mode, |
191 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | 191 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, |
192 | .set_mmu_debug_mode = NULL, | ||
192 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 193 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
193 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | 194 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, |
194 | .suspend_contexts = vgpu_gr_suspend_contexts, | 195 | .suspend_contexts = vgpu_gr_suspend_contexts, |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index 5a3f0046..e193ace9 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -282,6 +282,7 @@ int vgpu_init_gpu_characteristics(struct gk20a *g) | |||
282 | 282 | ||
283 | /* features vgpu does not support */ | 283 | /* features vgpu does not support */ |
284 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false); | 284 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false); |
285 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE, false); | ||
285 | 286 | ||
286 | return 0; | 287 | return 0; |
287 | } | 288 | } |