diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h | 4 |
2 files changed, 9 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index de2502ce..876ea610 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -148,7 +148,11 @@ static void gv11b_acr_default_sw_init(struct gk20a *g, struct hs_acr *hs_acr) | |||
148 | hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE; | 148 | hs_bl->bl_fw_name = HSBIN_ACR_BL_UCODE_IMAGE; |
149 | 149 | ||
150 | hs_acr->acr_type = ACR_DEFAULT; | 150 | hs_acr->acr_type = ACR_DEFAULT; |
151 | hs_acr->acr_fw_name = HSBIN_ACR_UCODE_IMAGE; | 151 | if (!g->ops.pmu.is_debug_mode_enabled(g)) { |
152 | hs_acr->acr_fw_name = HSBIN_ACR_PROD_UCODE; | ||
153 | } else { | ||
154 | hs_acr->acr_fw_name = HSBIN_ACR_DBG_UCODE; | ||
155 | } | ||
152 | 156 | ||
153 | hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1; | 157 | hs_acr->ptr_bl_dmem_desc = &hs_acr->bl_dmem_desc_v1; |
154 | hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); | 158 | hs_acr->bl_dmem_desc_size = sizeof(struct flcn_bl_dmem_desc_v1); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h index 7a0143e7..06d39595 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -40,6 +40,8 @@ struct nvgpu_acr; | |||
40 | 40 | ||
41 | #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" | 41 | #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" |
42 | #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" | 42 | #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" |
43 | #define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin" | ||
44 | #define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin" | ||
43 | #define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" | 45 | #define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" |
44 | #define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin" | 46 | #define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin" |
45 | #define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin" | 47 | #define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin" |