diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 187 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 25 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 172 |
4 files changed, 379 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ad34233c..d36aa6ec 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -192,24 +192,197 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
192 | 192 | ||
193 | } | 193 | } |
194 | 194 | ||
195 | static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
196 | bool *post_event, struct channel_gk20a *fault_ch, | ||
197 | u32 *hww_global_esr) | ||
198 | { | ||
199 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
200 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
201 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
202 | u32 lrf_ecc_status, lrf_ecc_corrected_err_status = 0; | ||
203 | u32 lrf_ecc_uncorrected_err_status = 0; | ||
204 | u32 lrf_corrected_err_count_delta = 0; | ||
205 | u32 lrf_uncorrected_err_count_delta = 0; | ||
206 | bool is_lrf_ecc_corrected_total_err_overflow = 0; | ||
207 | bool is_lrf_ecc_uncorrected_total_err_overflow = 0; | ||
208 | |||
209 | /* Check for LRF ECC errors. */ | ||
210 | lrf_ecc_status = gk20a_readl(g, | ||
211 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); | ||
212 | lrf_ecc_corrected_err_status = lrf_ecc_status & | ||
213 | (gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m() | | ||
214 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m() | | ||
215 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m() | | ||
216 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m() | | ||
217 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m() | | ||
218 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m() | | ||
219 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m() | | ||
220 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m()); | ||
221 | lrf_ecc_uncorrected_err_status = lrf_ecc_status & | ||
222 | (gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m() | | ||
223 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m() | | ||
224 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m() | | ||
225 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m() | | ||
226 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m() | | ||
227 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m() | | ||
228 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m() | | ||
229 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m()); | ||
230 | |||
231 | if ((lrf_ecc_corrected_err_status == 0) && (lrf_ecc_uncorrected_err_status == 0)) | ||
232 | return 0; | ||
233 | |||
234 | lrf_corrected_err_count_delta = | ||
235 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v( | ||
236 | gk20a_readl(g, | ||
237 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + | ||
238 | offset)); | ||
239 | lrf_uncorrected_err_count_delta = | ||
240 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v( | ||
241 | gk20a_readl(g, | ||
242 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + | ||
243 | offset)); | ||
244 | is_lrf_ecc_corrected_total_err_overflow = | ||
245 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(lrf_ecc_status); | ||
246 | is_lrf_ecc_uncorrected_total_err_overflow = | ||
247 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(lrf_ecc_status); | ||
248 | |||
249 | if ((lrf_corrected_err_count_delta > 0) || is_lrf_ecc_corrected_total_err_overflow) { | ||
250 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
251 | "corrected error (SBE) detected in SM LRF! err_mask [%08x] is_overf [%d]", | ||
252 | lrf_ecc_corrected_err_status, is_lrf_ecc_corrected_total_err_overflow); | ||
253 | |||
254 | /* HW uses 16-bits counter */ | ||
255 | lrf_corrected_err_count_delta += | ||
256 | (is_lrf_ecc_corrected_total_err_overflow << | ||
257 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s()); | ||
258 | g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += | ||
259 | lrf_corrected_err_count_delta; | ||
260 | gk20a_writel(g, | ||
261 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r() + offset, | ||
262 | 0); | ||
263 | } | ||
264 | if ((lrf_uncorrected_err_count_delta > 0) || is_lrf_ecc_uncorrected_total_err_overflow) { | ||
265 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
266 | "Uncorrected error (DBE) detected in SM LRF! err_mask [%08x] is_overf [%d]", | ||
267 | lrf_ecc_uncorrected_err_status, is_lrf_ecc_uncorrected_total_err_overflow); | ||
268 | |||
269 | /* HW uses 16-bits counter */ | ||
270 | lrf_uncorrected_err_count_delta += | ||
271 | (is_lrf_ecc_uncorrected_total_err_overflow << | ||
272 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s()); | ||
273 | g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += | ||
274 | lrf_uncorrected_err_count_delta; | ||
275 | gk20a_writel(g, | ||
276 | gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r() + offset, | ||
277 | 0); | ||
278 | } | ||
279 | |||
280 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, | ||
281 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f()); | ||
282 | |||
283 | return 0; | ||
284 | |||
285 | } | ||
286 | |||
287 | static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
288 | bool *post_event, struct channel_gk20a *fault_ch, | ||
289 | u32 *hww_global_esr) | ||
290 | { | ||
291 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
292 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
293 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
294 | u32 cbu_ecc_status, cbu_ecc_corrected_err_status = 0; | ||
295 | u32 cbu_ecc_uncorrected_err_status = 0; | ||
296 | u32 cbu_corrected_err_count_delta = 0; | ||
297 | u32 cbu_uncorrected_err_count_delta = 0; | ||
298 | bool is_cbu_ecc_corrected_total_err_overflow = 0; | ||
299 | bool is_cbu_ecc_uncorrected_total_err_overflow = 0; | ||
300 | |||
301 | /* Check for CBU ECC errors. */ | ||
302 | cbu_ecc_status = gk20a_readl(g, | ||
303 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r() + offset); | ||
304 | cbu_ecc_corrected_err_status = cbu_ecc_status & | ||
305 | (gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m() | | ||
306 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m() | | ||
307 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m() | | ||
308 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m()); | ||
309 | cbu_ecc_uncorrected_err_status = cbu_ecc_status & | ||
310 | (gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m() | | ||
311 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m() | | ||
312 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m() | | ||
313 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m()); | ||
314 | |||
315 | if ((cbu_ecc_corrected_err_status == 0) && (cbu_ecc_uncorrected_err_status == 0)) | ||
316 | return 0; | ||
317 | |||
318 | cbu_corrected_err_count_delta = | ||
319 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v( | ||
320 | gk20a_readl(g, | ||
321 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + | ||
322 | offset)); | ||
323 | cbu_uncorrected_err_count_delta = | ||
324 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v( | ||
325 | gk20a_readl(g, | ||
326 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + | ||
327 | offset)); | ||
328 | is_cbu_ecc_corrected_total_err_overflow = | ||
329 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(cbu_ecc_status); | ||
330 | is_cbu_ecc_uncorrected_total_err_overflow = | ||
331 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(cbu_ecc_status); | ||
332 | |||
333 | if ((cbu_corrected_err_count_delta > 0) || is_cbu_ecc_corrected_total_err_overflow) { | ||
334 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
335 | "corrected error (SBE) detected in SM CBU! err_mask [%08x] is_overf [%d]", | ||
336 | cbu_ecc_corrected_err_status, is_cbu_ecc_corrected_total_err_overflow); | ||
337 | |||
338 | /* HW uses 16-bits counter */ | ||
339 | cbu_corrected_err_count_delta += | ||
340 | (is_cbu_ecc_corrected_total_err_overflow << | ||
341 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s()); | ||
342 | g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count.counters[tpc] += | ||
343 | cbu_corrected_err_count_delta; | ||
344 | gk20a_writel(g, | ||
345 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r() + offset, | ||
346 | 0); | ||
347 | } | ||
348 | if ((cbu_uncorrected_err_count_delta > 0) || is_cbu_ecc_uncorrected_total_err_overflow) { | ||
349 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
350 | "Uncorrected error (DBE) detected in SM CBU! err_mask [%08x] is_overf [%d]", | ||
351 | cbu_ecc_uncorrected_err_status, is_cbu_ecc_uncorrected_total_err_overflow); | ||
352 | |||
353 | /* HW uses 16-bits counter */ | ||
354 | cbu_uncorrected_err_count_delta += | ||
355 | (is_cbu_ecc_uncorrected_total_err_overflow << | ||
356 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s()); | ||
357 | g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count.counters[tpc] += | ||
358 | cbu_uncorrected_err_count_delta; | ||
359 | gk20a_writel(g, | ||
360 | gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r() + offset, | ||
361 | 0); | ||
362 | } | ||
363 | |||
364 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r() + offset, | ||
365 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f()); | ||
366 | |||
367 | return 0; | ||
368 | |||
369 | } | ||
370 | |||
195 | static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | 371 | static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, |
196 | bool *post_event, struct channel_gk20a *fault_ch, | 372 | bool *post_event, struct channel_gk20a *fault_ch, |
197 | u32 *hww_global_esr) | 373 | u32 *hww_global_esr) |
198 | { | 374 | { |
199 | int ret = 0; | 375 | int ret = 0; |
200 | u32 offset = proj_gpc_stride_v() * gpc + | ||
201 | proj_tpc_in_gpc_stride_v() * tpc; | ||
202 | u32 lrf_ecc_status; | ||
203 | 376 | ||
204 | /* Check for L1 tag ECC errors. */ | 377 | /* Check for L1 tag ECC errors. */ |
205 | gr_gv11b_handle_l1_tag_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); | 378 | gr_gv11b_handle_l1_tag_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); |
206 | 379 | ||
207 | /* Check for LRF ECC errors. */ | 380 | /* Check for LRF ECC errors. */ |
208 | lrf_ecc_status = gk20a_readl(g, | 381 | gr_gv11b_handle_lrf_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); |
209 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); | 382 | |
383 | /* Check for CBU ECC errors. */ | ||
384 | gr_gv11b_handle_cbu_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); | ||
210 | 385 | ||
211 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, | ||
212 | lrf_ecc_status); | ||
213 | return ret; | 386 | return ret; |
214 | } | 387 | } |
215 | 388 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 2d6e3d1f..b350862c 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -39,6 +39,8 @@ struct gr_t19x { | |||
39 | struct { | 39 | struct { |
40 | struct gr_gp10b_ecc_stat sm_l1_tag_corrected_err_count; | 40 | struct gr_gp10b_ecc_stat sm_l1_tag_corrected_err_count; |
41 | struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; | 41 | struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; |
42 | struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; | ||
43 | struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; | ||
42 | } ecc_stats; | 44 | } ecc_stats; |
43 | }; | 45 | }; |
44 | 46 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index 8ca9dd30..d235b261 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | |||
@@ -125,6 +125,8 @@ struct gk20a_platform t19x_gpu_tegra_platform = { | |||
125 | 125 | ||
126 | static struct device_attribute *dev_attr_sm_l1_tag_ecc_corrected_err_count_array; | 126 | static struct device_attribute *dev_attr_sm_l1_tag_ecc_corrected_err_count_array; |
127 | static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array; | 127 | static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array; |
128 | static struct device_attribute *dev_attr_sm_cbu_ecc_corrected_err_count_array; | ||
129 | static struct device_attribute *dev_attr_sm_cbu_ecc_uncorrected_err_count_array; | ||
128 | 130 | ||
129 | void gr_gv11b_create_sysfs(struct device *dev) | 131 | void gr_gv11b_create_sysfs(struct device *dev) |
130 | { | 132 | { |
@@ -151,6 +153,18 @@ void gr_gv11b_create_sysfs(struct device *dev) | |||
151 | &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, | 153 | &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, |
152 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); | 154 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); |
153 | 155 | ||
156 | error |= gr_gp10b_ecc_stat_create(dev, | ||
157 | 0, | ||
158 | "sm_cbu_ecc_corrected_err_count", | ||
159 | &g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count, | ||
160 | dev_attr_sm_cbu_ecc_corrected_err_count_array); | ||
161 | |||
162 | error |= gr_gp10b_ecc_stat_create(dev, | ||
163 | 0, | ||
164 | "sm_cbu_ecc_uncorrected_err_count", | ||
165 | &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, | ||
166 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | ||
167 | |||
154 | if (error) | 168 | if (error) |
155 | dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); | 169 | dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); |
156 | } | 170 | } |
@@ -168,4 +182,15 @@ static void gr_gv11b_remove_sysfs(struct device *dev) | |||
168 | 0, | 182 | 0, |
169 | &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, | 183 | &g->gr.t19x.ecc_stats.sm_l1_tag_uncorrected_err_count, |
170 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); | 184 | dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array); |
185 | |||
186 | gr_gp10b_ecc_stat_remove(dev, | ||
187 | 0, | ||
188 | &g->gr.t19x.ecc_stats.sm_cbu_corrected_err_count, | ||
189 | dev_attr_sm_cbu_ecc_corrected_err_count_array); | ||
190 | |||
191 | gr_gp10b_ecc_stat_remove(dev, | ||
192 | 0, | ||
193 | &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, | ||
194 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | ||
195 | |||
171 | } | 196 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index d45385a8..4b2e8c32 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -482,6 +482,106 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) | |||
482 | { | 482 | { |
483 | return 0x00504358; | 483 | return 0x00504358; |
484 | } | 484 | } |
485 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp0_m(void) | ||
486 | { | ||
487 | return 0x1 << 0; | ||
488 | } | ||
489 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp1_m(void) | ||
490 | { | ||
491 | return 0x1 << 1; | ||
492 | } | ||
493 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp2_m(void) | ||
494 | { | ||
495 | return 0x1 << 2; | ||
496 | } | ||
497 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp3_m(void) | ||
498 | { | ||
499 | return 0x1 << 3; | ||
500 | } | ||
501 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp4_m(void) | ||
502 | { | ||
503 | return 0x1 << 4; | ||
504 | } | ||
505 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp5_m(void) | ||
506 | { | ||
507 | return 0x1 << 5; | ||
508 | } | ||
509 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp6_m(void) | ||
510 | { | ||
511 | return 0x1 << 6; | ||
512 | } | ||
513 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_qrfdp7_m(void) | ||
514 | { | ||
515 | return 0x1 << 7; | ||
516 | } | ||
517 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp0_m(void) | ||
518 | { | ||
519 | return 0x1 << 8; | ||
520 | } | ||
521 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp1_m(void) | ||
522 | { | ||
523 | return 0x1 << 9; | ||
524 | } | ||
525 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp2_m(void) | ||
526 | { | ||
527 | return 0x1 << 10; | ||
528 | } | ||
529 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp3_m(void) | ||
530 | { | ||
531 | return 0x1 << 11; | ||
532 | } | ||
533 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp4_m(void) | ||
534 | { | ||
535 | return 0x1 << 12; | ||
536 | } | ||
537 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp5_m(void) | ||
538 | { | ||
539 | return 0x1 << 13; | ||
540 | } | ||
541 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m(void) | ||
542 | { | ||
543 | return 0x1 << 14; | ||
544 | } | ||
545 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m(void) | ||
546 | { | ||
547 | return 0x1 << 15; | ||
548 | } | ||
549 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
550 | { | ||
551 | return (r >> 24) & 0x1; | ||
552 | } | ||
553 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
554 | { | ||
555 | return (r >> 26) & 0x1; | ||
556 | } | ||
557 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_reset_task_f(void) | ||
558 | { | ||
559 | return 0x40000000; | ||
560 | } | ||
561 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_r(void) | ||
562 | { | ||
563 | return 0x0050435c; | ||
564 | } | ||
565 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_s(void) | ||
566 | { | ||
567 | return 16; | ||
568 | } | ||
569 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v(u32 r) | ||
570 | { | ||
571 | return (r >> 0) & 0xffff; | ||
572 | } | ||
573 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_r(void) | ||
574 | { | ||
575 | return 0x00504360; | ||
576 | } | ||
577 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_s(void) | ||
578 | { | ||
579 | return 16; | ||
580 | } | ||
581 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 r) | ||
582 | { | ||
583 | return (r >> 0) & 0xffff; | ||
584 | } | ||
485 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) | 585 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) |
486 | { | 586 | { |
487 | return 0x00504624; | 587 | return 0x00504624; |
@@ -554,6 +654,78 @@ static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_uncorrected_err_count_total_v(u | |||
554 | { | 654 | { |
555 | return (r >> 0) & 0xffff; | 655 | return (r >> 0) & 0xffff; |
556 | } | 656 | } |
657 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_r(void) | ||
658 | { | ||
659 | return 0x00504638; | ||
660 | } | ||
661 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm0_m(void) | ||
662 | { | ||
663 | return 0x1 << 0; | ||
664 | } | ||
665 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_warp_sm1_m(void) | ||
666 | { | ||
667 | return 0x1 << 1; | ||
668 | } | ||
669 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm0_m(void) | ||
670 | { | ||
671 | return 0x1 << 2; | ||
672 | } | ||
673 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_barrier_sm1_m(void) | ||
674 | { | ||
675 | return 0x1 << 3; | ||
676 | } | ||
677 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm0_m(void) | ||
678 | { | ||
679 | return 0x1 << 4; | ||
680 | } | ||
681 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_warp_sm1_m(void) | ||
682 | { | ||
683 | return 0x1 << 5; | ||
684 | } | ||
685 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m(void) | ||
686 | { | ||
687 | return 0x1 << 6; | ||
688 | } | ||
689 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m(void) | ||
690 | { | ||
691 | return 0x1 << 7; | ||
692 | } | ||
693 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
694 | { | ||
695 | return (r >> 16) & 0x1; | ||
696 | } | ||
697 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
698 | { | ||
699 | return (r >> 18) & 0x1; | ||
700 | } | ||
701 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_status_reset_task_f(void) | ||
702 | { | ||
703 | return 0x40000000; | ||
704 | } | ||
705 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_r(void) | ||
706 | { | ||
707 | return 0x0050463c; | ||
708 | } | ||
709 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_s(void) | ||
710 | { | ||
711 | return 16; | ||
712 | } | ||
713 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v(u32 r) | ||
714 | { | ||
715 | return (r >> 0) & 0xffff; | ||
716 | } | ||
717 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_r(void) | ||
718 | { | ||
719 | return 0x00504640; | ||
720 | } | ||
721 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_s(void) | ||
722 | { | ||
723 | return 16; | ||
724 | } | ||
725 | static inline u32 gr_pri_gpc0_tpc0_sm_cbu_ecc_uncorrected_err_count_total_v(u32 r) | ||
726 | { | ||
727 | return (r >> 0) & 0xffff; | ||
728 | } | ||
557 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) | 729 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) |
558 | { | 730 | { |
559 | return 0x005042c4; | 731 | return 0x005042c4; |