diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 95 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmu.h | 9 |
6 files changed, 106 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 664134f9..1c5fdce0 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -37,15 +37,6 @@ | |||
37 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> | 37 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> |
38 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | 38 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> |
39 | 39 | ||
40 | /*! | ||
41 | * Structure/object which single register write need to be done during PG init | ||
42 | * sequence to set PROD values. | ||
43 | */ | ||
44 | struct pg_init_sequence_list { | ||
45 | u32 regaddr; | ||
46 | u32 writeval; | ||
47 | }; | ||
48 | |||
49 | #define gm20b_dbg_pmu(fmt, arg...) \ | 40 | #define gm20b_dbg_pmu(fmt, arg...) \ |
50 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 41 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
51 | 42 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 147cd020..d368bad7 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -39,14 +39,6 @@ | |||
39 | 39 | ||
40 | #define gp10b_dbg_pmu(fmt, arg...) \ | 40 | #define gp10b_dbg_pmu(fmt, arg...) \ |
41 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 41 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
42 | /*! | ||
43 | * Structure/object which single register write need to be done during PG init | ||
44 | * sequence to set PROD values. | ||
45 | */ | ||
46 | struct pg_init_sequence_list { | ||
47 | u32 regaddr; | ||
48 | u32 writeval; | ||
49 | }; | ||
50 | 42 | ||
51 | /* PROD settings for ELPG sequencing registers*/ | 43 | /* PROD settings for ELPG sequencing registers*/ |
52 | static struct pg_init_sequence_list _pginitseq_gp10b[] = { | 44 | static struct pg_init_sequence_list _pginitseq_gp10b[] = { |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index bdf741d9..6a21eb2d 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -589,7 +589,7 @@ static const struct gpu_ops gv11b_ops = { | |||
589 | .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, | 589 | .elcg_init_idle_filters = gv11b_elcg_init_idle_filters, |
590 | }, | 590 | }, |
591 | .pmu = { | 591 | .pmu = { |
592 | .pmu_setup_elpg = gp10b_pmu_setup_elpg, | 592 | .pmu_setup_elpg = gv11b_pmu_setup_elpg, |
593 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | 593 | .pmu_get_queue_head = pwr_pmu_queue_head_r, |
594 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, | 594 | .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v, |
595 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | 595 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, |
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 3e80a51a..4b244f5a 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -42,6 +42,101 @@ | |||
42 | 42 | ||
43 | #define ALIGN_4KB 12 | 43 | #define ALIGN_4KB 12 |
44 | 44 | ||
45 | /* PROD settings for ELPG sequencing registers*/ | ||
46 | static struct pg_init_sequence_list _pginitseq_gv11b[] = { | ||
47 | {0x0010e0a8, 0x00000000} , | ||
48 | {0x0010e0ac, 0x00000000} , | ||
49 | {0x0010e198, 0x00000200} , | ||
50 | {0x0010e19c, 0x00000000} , | ||
51 | {0x0010e19c, 0x00000000} , | ||
52 | {0x0010e19c, 0x00000000} , | ||
53 | {0x0010e19c, 0x00000000} , | ||
54 | {0x0010aba8, 0x00000200} , | ||
55 | {0x0010abac, 0x00000000} , | ||
56 | {0x0010abac, 0x00000000} , | ||
57 | {0x0010abac, 0x00000000} , | ||
58 | {0x0010e09c, 0x00000731} , | ||
59 | {0x0010e18c, 0x00000731} , | ||
60 | {0x0010ab9c, 0x00000731} , | ||
61 | {0x0010e0a0, 0x00000200} , | ||
62 | {0x0010e0a4, 0x00000004} , | ||
63 | {0x0010e0a4, 0x80000000} , | ||
64 | {0x0010e0a4, 0x80000009} , | ||
65 | {0x0010e0a4, 0x8000001A} , | ||
66 | {0x0010e0a4, 0x8000001E} , | ||
67 | {0x0010e0a4, 0x8000002A} , | ||
68 | {0x0010e0a4, 0x8000002E} , | ||
69 | {0x0010e0a4, 0x80000016} , | ||
70 | {0x0010e0a4, 0x80000022} , | ||
71 | {0x0010e0a4, 0x80000026} , | ||
72 | {0x0010e0a4, 0x00000005} , | ||
73 | {0x0010e0a4, 0x80000001} , | ||
74 | {0x0010e0a4, 0x8000000A} , | ||
75 | {0x0010e0a4, 0x8000001B} , | ||
76 | {0x0010e0a4, 0x8000001F} , | ||
77 | {0x0010e0a4, 0x8000002B} , | ||
78 | {0x0010e0a4, 0x8000002F} , | ||
79 | {0x0010e0a4, 0x80000017} , | ||
80 | {0x0010e0a4, 0x80000023} , | ||
81 | {0x0010e0a4, 0x80000027} , | ||
82 | {0x0010e0a4, 0x00000006} , | ||
83 | {0x0010e0a4, 0x80000002} , | ||
84 | {0x0010e0a4, 0x8000000B} , | ||
85 | {0x0010e0a4, 0x8000001C} , | ||
86 | {0x0010e0a4, 0x80000020} , | ||
87 | {0x0010e0a4, 0x8000002C} , | ||
88 | {0x0010e0a4, 0x80000030} , | ||
89 | {0x0010e0a4, 0x80000018} , | ||
90 | {0x0010e0a4, 0x80000024} , | ||
91 | {0x0010e0a4, 0x80000028} , | ||
92 | {0x0010e0a4, 0x00000007} , | ||
93 | {0x0010e0a4, 0x80000003} , | ||
94 | {0x0010e0a4, 0x8000000C} , | ||
95 | {0x0010e0a4, 0x8000001D} , | ||
96 | {0x0010e0a4, 0x80000021} , | ||
97 | {0x0010e0a4, 0x8000002D} , | ||
98 | {0x0010e0a4, 0x80000031} , | ||
99 | {0x0010e0a4, 0x80000019} , | ||
100 | {0x0010e0a4, 0x80000025} , | ||
101 | {0x0010e0a4, 0x80000029} , | ||
102 | {0x0010e0a4, 0x80000012} , | ||
103 | {0x0010e0a4, 0x80000010} , | ||
104 | {0x0010e0a4, 0x00000013} , | ||
105 | {0x0010e0a4, 0x80000011} , | ||
106 | {0x0010e0a4, 0x80000008} , | ||
107 | {0x0010e0a4, 0x8000000D} , | ||
108 | {0x0010e190, 0x00000200} , | ||
109 | {0x0010e194, 0x80000015} , | ||
110 | {0x0010e194, 0x80000014} , | ||
111 | {0x0010aba0, 0x00000200} , | ||
112 | {0x0010aba4, 0x8000000E} , | ||
113 | {0x0010aba4, 0x0000000F} , | ||
114 | {0x0010ab34, 0x00000001} , | ||
115 | {0x00020004, 0x00000000} , | ||
116 | }; | ||
117 | |||
118 | int gv11b_pmu_setup_elpg(struct gk20a *g) | ||
119 | { | ||
120 | int ret = 0; | ||
121 | u32 reg_writes; | ||
122 | u32 index; | ||
123 | |||
124 | gk20a_dbg_fn(""); | ||
125 | |||
126 | if (g->elpg_enabled) { | ||
127 | reg_writes = ((sizeof(_pginitseq_gv11b) / | ||
128 | sizeof((_pginitseq_gv11b)[0]))); | ||
129 | /* Initialize registers with production values*/ | ||
130 | for (index = 0; index < reg_writes; index++) { | ||
131 | gk20a_writel(g, _pginitseq_gv11b[index].regaddr, | ||
132 | _pginitseq_gv11b[index].writeval); | ||
133 | } | ||
134 | } | ||
135 | |||
136 | gk20a_dbg_fn("done"); | ||
137 | return ret; | ||
138 | } | ||
139 | |||
45 | bool gv11b_is_pmu_supported(struct gk20a *g) | 140 | bool gv11b_is_pmu_supported(struct gk20a *g) |
46 | { | 141 | { |
47 | return true; | 142 | return true; |
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index 809970ff..e917188d 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | |||
@@ -33,5 +33,6 @@ int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); | |||
33 | int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); | 33 | int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); |
34 | bool gv11b_is_lazy_bootstrap(u32 falcon_id); | 34 | bool gv11b_is_lazy_bootstrap(u32 falcon_id); |
35 | bool gv11b_is_priv_load(u32 falcon_id); | 35 | bool gv11b_is_priv_load(u32 falcon_id); |
36 | int gv11b_pmu_setup_elpg(struct gk20a *g); | ||
36 | 37 | ||
37 | #endif /*__PMU_GV11B_H_*/ | 38 | #endif /*__PMU_GV11B_H_*/ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index a818f3d0..c0ceca61 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -380,6 +380,15 @@ struct pmu_pg_stats_data { | |||
380 | u32 avg_exit_latency_us; | 380 | u32 avg_exit_latency_us; |
381 | }; | 381 | }; |
382 | 382 | ||
383 | /*! | ||
384 | * Structure/object which single register write need to be done during PG init | ||
385 | * sequence to set PROD values. | ||
386 | */ | ||
387 | struct pg_init_sequence_list { | ||
388 | u32 regaddr; | ||
389 | u32 writeval; | ||
390 | }; | ||
391 | |||
383 | /* PMU IPC Methods */ | 392 | /* PMU IPC Methods */ |
384 | void nvgpu_pmu_seq_init(struct nvgpu_pmu *pmu); | 393 | void nvgpu_pmu_seq_init(struct nvgpu_pmu *pmu); |
385 | 394 | ||