diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_arb.c | 119 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_arb.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 22 |
3 files changed, 93 insertions, 49 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index 550c77e0..9232c3dc 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c | |||
@@ -313,7 +313,7 @@ int nvgpu_clk_arb_init_arbiter(struct gk20a *g) | |||
313 | spin_lock_init(&arb->users_lock); | 313 | spin_lock_init(&arb->users_lock); |
314 | 314 | ||
315 | err = g->ops.clk_arb.get_arbiter_clk_default(g, | 315 | err = g->ops.clk_arb.get_arbiter_clk_default(g, |
316 | NVGPU_GPU_CLK_DOMAIN_MCLK, &default_mhz); | 316 | CTRL_CLK_DOMAIN_MCLK, &default_mhz); |
317 | if (err < 0) { | 317 | if (err < 0) { |
318 | err = -EINVAL; | 318 | err = -EINVAL; |
319 | goto init_fail; | 319 | goto init_fail; |
@@ -322,7 +322,7 @@ int nvgpu_clk_arb_init_arbiter(struct gk20a *g) | |||
322 | arb->mclk_default_mhz = default_mhz; | 322 | arb->mclk_default_mhz = default_mhz; |
323 | 323 | ||
324 | err = g->ops.clk_arb.get_arbiter_clk_default(g, | 324 | err = g->ops.clk_arb.get_arbiter_clk_default(g, |
325 | NVGPU_GPU_CLK_DOMAIN_GPC2CLK, &default_mhz); | 325 | CTRL_CLK_DOMAIN_GPC2CLK, &default_mhz); |
326 | if (err < 0) { | 326 | if (err < 0) { |
327 | err = -EINVAL; | 327 | err = -EINVAL; |
328 | goto init_fail; | 328 | goto init_fail; |
@@ -672,15 +672,14 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
672 | &arb->vf_table_pool[0]; | 672 | &arb->vf_table_pool[0]; |
673 | 673 | ||
674 | /* Get allowed memory ranges */ | 674 | /* Get allowed memory ranges */ |
675 | if (nvgpu_clk_arb_get_arbiter_clk_range(g, NVGPU_GPU_CLK_DOMAIN_GPC2CLK, | 675 | if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_GPC2CLK, |
676 | &gpc2clk_min, | 676 | &gpc2clk_min, &gpc2clk_max) < 0) { |
677 | &gpc2clk_max) < 0) { | ||
678 | gk20a_err(dev_from_gk20a(g), | 677 | gk20a_err(dev_from_gk20a(g), |
679 | "failed to fetch GPC2CLK range"); | 678 | "failed to fetch GPC2CLK range"); |
680 | goto exit_vf_table; | 679 | goto exit_vf_table; |
681 | } | 680 | } |
682 | if (nvgpu_clk_arb_get_arbiter_clk_range(g, NVGPU_GPU_CLK_DOMAIN_MCLK, | 681 | if (g->ops.clk_arb.get_arbiter_clk_range(g, CTRL_CLK_DOMAIN_MCLK, |
683 | &mclk_min, &mclk_max) < 0) { | 682 | &mclk_min, &mclk_max) < 0) { |
684 | gk20a_err(dev_from_gk20a(g), | 683 | gk20a_err(dev_from_gk20a(g), |
685 | "failed to fetch MCLK range"); | 684 | "failed to fetch MCLK range"); |
686 | goto exit_vf_table; | 685 | goto exit_vf_table; |
@@ -689,14 +688,14 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb) | |||
689 | table->gpc2clk_num_points = MAX_F_POINTS; | 688 | table->gpc2clk_num_points = MAX_F_POINTS; |
690 | table->mclk_num_points = MAX_F_POINTS; | 689 | table->mclk_num_points = MAX_F_POINTS; |
691 | 690 | ||
692 | if (clk_domain_get_f_points(arb->g, NVGPU_GPU_CLK_DOMAIN_GPC2CLK, | 691 | if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_GPC2CLK, |
693 | &table->gpc2clk_num_points, arb->gpc2clk_f_points)) { | 692 | &table->gpc2clk_num_points, arb->gpc2clk_f_points)) { |
694 | gk20a_err(dev_from_gk20a(g), | 693 | gk20a_err(dev_from_gk20a(g), |
695 | "failed to fetch GPC2CLK frequency points"); | 694 | "failed to fetch GPC2CLK frequency points"); |
696 | goto exit_vf_table; | 695 | goto exit_vf_table; |
697 | } | 696 | } |
698 | 697 | ||
699 | if (clk_domain_get_f_points(arb->g, NVGPU_GPU_CLK_DOMAIN_MCLK, | 698 | if (clk_domain_get_f_points(arb->g, CTRL_CLK_DOMAIN_MCLK, |
700 | &table->mclk_num_points, arb->mclk_f_points)) { | 699 | &table->mclk_num_points, arb->mclk_f_points)) { |
701 | gk20a_err(dev_from_gk20a(g), | 700 | gk20a_err(dev_from_gk20a(g), |
702 | "failed to fetch MCLK frequency points"); | 701 | "failed to fetch MCLK frequency points"); |
@@ -1629,17 +1628,15 @@ int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session, | |||
1629 | 1628 | ||
1630 | switch (api_domain) { | 1629 | switch (api_domain) { |
1631 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1630 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1631 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1632 | dev->mclk_target_mhz = target_mhz; | 1632 | dev->mclk_target_mhz = target_mhz; |
1633 | break; | 1633 | break; |
1634 | 1634 | ||
1635 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1635 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1636 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1636 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; | 1637 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; |
1637 | break; | 1638 | break; |
1638 | 1639 | ||
1639 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: | ||
1640 | dev->gpc2clk_target_mhz = target_mhz; | ||
1641 | break; | ||
1642 | |||
1643 | default: | 1640 | default: |
1644 | err = -EINVAL; | 1641 | err = -EINVAL; |
1645 | } | 1642 | } |
@@ -1662,17 +1659,15 @@ int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session, | |||
1662 | 1659 | ||
1663 | switch (api_domain) { | 1660 | switch (api_domain) { |
1664 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1661 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1662 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1665 | *freq_mhz = target->mclk; | 1663 | *freq_mhz = target->mclk; |
1666 | break; | 1664 | break; |
1667 | 1665 | ||
1668 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1666 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1667 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1669 | *freq_mhz = target->gpc2clk / 2ULL; | 1668 | *freq_mhz = target->gpc2clk / 2ULL; |
1670 | break; | 1669 | break; |
1671 | 1670 | ||
1672 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: | ||
1673 | *freq_mhz = target->gpc2clk; | ||
1674 | break; | ||
1675 | |||
1676 | default: | 1671 | default: |
1677 | *freq_mhz = 0; | 1672 | *freq_mhz = 0; |
1678 | err = -EINVAL; | 1673 | err = -EINVAL; |
@@ -1695,17 +1690,15 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | |||
1695 | 1690 | ||
1696 | switch (api_domain) { | 1691 | switch (api_domain) { |
1697 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 1692 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1693 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1698 | *freq_mhz = actual->mclk; | 1694 | *freq_mhz = actual->mclk; |
1699 | break; | 1695 | break; |
1700 | 1696 | ||
1701 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 1697 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1698 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1702 | *freq_mhz = actual->gpc2clk / 2ULL; | 1699 | *freq_mhz = actual->gpc2clk / 2ULL; |
1703 | break; | 1700 | break; |
1704 | 1701 | ||
1705 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: | ||
1706 | *freq_mhz = actual->gpc2clk; | ||
1707 | break; | ||
1708 | |||
1709 | default: | 1702 | default: |
1710 | *freq_mhz = 0; | 1703 | *freq_mhz = 0; |
1711 | err = -EINVAL; | 1704 | err = -EINVAL; |
@@ -1717,12 +1710,20 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | |||
1717 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | 1710 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, |
1718 | u32 api_domain, u16 *freq_mhz) | 1711 | u32 api_domain, u16 *freq_mhz) |
1719 | { | 1712 | { |
1720 | if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) | 1713 | switch(api_domain) { |
1721 | *freq_mhz = g->ops.clk.get_rate(g, | 1714 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1722 | NVGPU_GPU_CLK_DOMAIN_GPC2CLK) / 2; | 1715 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: |
1723 | else | 1716 | *freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_MCLK); |
1724 | *freq_mhz = g->ops.clk.get_rate(g, api_domain); | 1717 | return 0; |
1725 | return 0; | 1718 | |
1719 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
1720 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1721 | *freq_mhz = g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_GPC2CLK) / 2; | ||
1722 | return 0; | ||
1723 | |||
1724 | default: | ||
1725 | return -EINVAL; | ||
1726 | } | ||
1726 | } | 1727 | } |
1727 | 1728 | ||
1728 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | 1729 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, |
@@ -1730,30 +1731,58 @@ int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | |||
1730 | { | 1731 | { |
1731 | int ret; | 1732 | int ret; |
1732 | 1733 | ||
1733 | if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) { | 1734 | switch(api_domain) { |
1735 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
1736 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1737 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
1738 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); | ||
1739 | return ret; | ||
1740 | |||
1741 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
1742 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1734 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | 1743 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, |
1735 | NVGPU_GPU_CLK_DOMAIN_GPC2CLK, | 1744 | CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); |
1736 | min_mhz, max_mhz); | ||
1737 | if (!ret) { | 1745 | if (!ret) { |
1738 | *min_mhz /= 2; | 1746 | *min_mhz /= 2; |
1739 | *max_mhz /= 2; | 1747 | *max_mhz /= 2; |
1740 | } | 1748 | } |
1741 | } else { | 1749 | return ret; |
1742 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, api_domain, | ||
1743 | min_mhz, max_mhz); | ||
1744 | } | ||
1745 | 1750 | ||
1746 | return ret; | 1751 | default: |
1752 | return -EINVAL; | ||
1753 | } | ||
1747 | } | 1754 | } |
1748 | 1755 | ||
1749 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) | 1756 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) |
1750 | { | 1757 | { |
1751 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | 1758 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); |
1759 | u32 api_domains = 0; | ||
1752 | 1760 | ||
1753 | if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) | 1761 | if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) |
1754 | clk_domains |= CTRL_CLK_DOMAIN_GPCCLK; | 1762 | api_domains |= NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS; |
1763 | |||
1764 | if (clk_domains & CTRL_CLK_DOMAIN_MCLK) | ||
1765 | api_domains |= NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS; | ||
1755 | 1766 | ||
1756 | return clk_domains; | 1767 | return api_domains; |
1768 | } | ||
1769 | |||
1770 | bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain) | ||
1771 | { | ||
1772 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | ||
1773 | |||
1774 | switch(api_domain) { | ||
1775 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
1776 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1777 | return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0); | ||
1778 | |||
1779 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
1780 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1781 | return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0); | ||
1782 | |||
1783 | default: | ||
1784 | return false; | ||
1785 | } | ||
1757 | } | 1786 | } |
1758 | 1787 | ||
1759 | int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | 1788 | int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, |
@@ -1762,19 +1791,23 @@ int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | |||
1762 | int err; | 1791 | int err; |
1763 | u32 i; | 1792 | u32 i; |
1764 | 1793 | ||
1765 | if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) { | 1794 | switch (api_domain) { |
1766 | err = clk_domain_get_f_points(g, NVGPU_GPU_CLK_DOMAIN_GPC2CLK, | 1795 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: |
1796 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK_ALIAS: | ||
1797 | err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK, | ||
1767 | max_points, fpoints); | 1798 | max_points, fpoints); |
1768 | if (err || !fpoints) | 1799 | if (err || !fpoints) |
1769 | return err; | 1800 | return err; |
1770 | for (i = 0; i < *max_points; i++) | 1801 | for (i = 0; i < *max_points; i++) |
1771 | fpoints[i] /= 2; | 1802 | fpoints[i] /= 2; |
1772 | } else { | 1803 | return 0; |
1773 | err = clk_domain_get_f_points(g, api_domain, | 1804 | case NVGPU_GPU_CLK_DOMAIN_MCLK: |
1805 | case NVGPU_GPU_CLK_DOMAIN_MCLK_ALIAS: | ||
1806 | return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK, | ||
1774 | max_points, fpoints); | 1807 | max_points, fpoints); |
1808 | default: | ||
1809 | return -EINVAL; | ||
1775 | } | 1810 | } |
1776 | |||
1777 | return err; | ||
1778 | } | 1811 | } |
1779 | 1812 | ||
1780 | static u8 nvgpu_clk_arb_find_vf_point(struct nvgpu_clk_arb *arb, | 1813 | static u8 nvgpu_clk_arb_find_vf_point(struct nvgpu_clk_arb *arb, |
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.h b/drivers/gpu/nvgpu/clk/clk_arb.h index c7dc8d19..45d8ed73 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.h +++ b/drivers/gpu/nvgpu/clk/clk_arb.h | |||
@@ -34,6 +34,7 @@ int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | |||
34 | u32 api_domain, u32 *max_points, u16 *fpoints); | 34 | u32 api_domain, u32 *max_points, u16 *fpoints); |
35 | 35 | ||
36 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g); | 36 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g); |
37 | bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain); | ||
37 | 38 | ||
38 | void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g); | 39 | void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g); |
39 | 40 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index aa2c4959..5c9baf77 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -869,7 +869,7 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | |||
869 | clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g); | 869 | clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g); |
870 | args->num_entries = 0; | 870 | args->num_entries = 0; |
871 | 871 | ||
872 | if ((args->clk_domain & clk_domains) == 0) | 872 | if (!nvgpu_clk_arb_is_valid_domain(g, args->clk_domain)) |
873 | return -EINVAL; | 873 | return -EINVAL; |
874 | 874 | ||
875 | err = nvgpu_clk_arb_get_arbiter_clk_f_points(g, | 875 | err = nvgpu_clk_arb_get_arbiter_clk_f_points(g, |
@@ -987,7 +987,10 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g, | |||
987 | return -EFAULT; | 987 | return -EFAULT; |
988 | } else { | 988 | } else { |
989 | bit = ffs(clk_domains) - 1; | 989 | bit = ffs(clk_domains) - 1; |
990 | clk_range.clk_domain = BIT(bit); | 990 | if (bit <= NVGPU_GPU_CLK_DOMAIN_GPCCLK) |
991 | clk_range.clk_domain = bit; | ||
992 | else | ||
993 | clk_range.clk_domain = BIT(bit); | ||
991 | clk_domains &= ~BIT(bit); | 994 | clk_domains &= ~BIT(bit); |
992 | } | 995 | } |
993 | 996 | ||
@@ -1031,6 +1034,8 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
1031 | if (!session || args->flags) | 1034 | if (!session || args->flags) |
1032 | return -EINVAL; | 1035 | return -EINVAL; |
1033 | 1036 | ||
1037 | gk20a_dbg_info("line=%d", __LINE__); | ||
1038 | |||
1034 | clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g); | 1039 | clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g); |
1035 | if (!clk_domains) | 1040 | if (!clk_domains) |
1036 | return -EINVAL; | 1041 | return -EINVAL; |
@@ -1038,15 +1043,17 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
1038 | entry = (struct nvgpu_gpu_clk_info __user *) | 1043 | entry = (struct nvgpu_gpu_clk_info __user *) |
1039 | (uintptr_t)args->clk_info_entries; | 1044 | (uintptr_t)args->clk_info_entries; |
1040 | 1045 | ||
1046 | gk20a_dbg_info("line=%d", __LINE__); | ||
1047 | |||
1041 | for (i = 0; i < args->num_entries; i++, entry++) { | 1048 | for (i = 0; i < args->num_entries; i++, entry++) { |
1042 | 1049 | ||
1050 | gk20a_dbg_info("line=%d", __LINE__); | ||
1043 | if (copy_from_user(&clk_info, entry, sizeof(clk_info))) | 1051 | if (copy_from_user(&clk_info, entry, sizeof(clk_info))) |
1044 | return -EFAULT; | 1052 | return -EFAULT; |
1045 | 1053 | ||
1046 | if ((clk_info.clk_domain & clk_domains) != clk_info.clk_domain) | 1054 | gk20a_dbg_info("i=%d domain=0x%08x", i, clk_info.clk_domain); |
1047 | return -EINVAL; | ||
1048 | 1055 | ||
1049 | if (hweight_long(clk_info.clk_domain) != 1) | 1056 | if (!nvgpu_clk_arb_is_valid_domain(g, clk_info.clk_domain)) |
1050 | return -EINVAL; | 1057 | return -EINVAL; |
1051 | } | 1058 | } |
1052 | 1059 | ||
@@ -1132,7 +1139,10 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1132 | return -EFAULT; | 1139 | return -EFAULT; |
1133 | } else { | 1140 | } else { |
1134 | bit = ffs(clk_domains) - 1; | 1141 | bit = ffs(clk_domains) - 1; |
1135 | clk_info.clk_domain = BIT(bit); | 1142 | if (bit <= NVGPU_GPU_CLK_DOMAIN_GPCCLK) |
1143 | clk_info.clk_domain = bit; | ||
1144 | else | ||
1145 | clk_info.clk_domain = BIT(bit); | ||
1136 | clk_domains &= ~BIT(bit); | 1146 | clk_domains &= ~BIT(bit); |
1137 | clk_info.clk_type = args->clk_type; | 1147 | clk_info.clk_type = args->clk_type; |
1138 | } | 1148 | } |