diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_mclk.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/mclk_gp106.c | 61 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/types.h | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pstate/pstate.h | 6 |
7 files changed, 55 insertions, 43 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.h b/drivers/gpu/nvgpu/clk/clk_mclk.h index a0d3fd5d..00356c98 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.h +++ b/drivers/gpu/nvgpu/clk/clk_mclk.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -25,10 +25,10 @@ | |||
25 | 25 | ||
26 | #include <nvgpu/lock.h> | 26 | #include <nvgpu/lock.h> |
27 | 27 | ||
28 | #define GP106_MCLK_LOW_SPEED 0 | 28 | #define GP106_MCLK_LOW_SPEED 0U |
29 | #define GP106_MCLK_MID_SPEED 1 | 29 | #define GP106_MCLK_MID_SPEED 1U |
30 | #define GP106_MCLK_HIGH_SPEED 2 | 30 | #define GP106_MCLK_HIGH_SPEED 2U |
31 | #define GP106_MCLK_NUM_SPEED 3 | 31 | #define GP106_MCLK_NUM_SPEED 3U |
32 | 32 | ||
33 | enum gk20a_mclk_speed { | 33 | enum gk20a_mclk_speed { |
34 | gk20a_mclk_low_speed, | 34 | gk20a_mclk_low_speed, |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e9497ea7..dd63a105 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1653,10 +1653,10 @@ static inline bool nvgpu_is_timeouts_enabled(struct gk20a *g) | |||
1653 | return nvgpu_atomic_read(&g->timeouts_disabled_refcount) == 0; | 1653 | return nvgpu_atomic_read(&g->timeouts_disabled_refcount) == 0; |
1654 | } | 1654 | } |
1655 | 1655 | ||
1656 | static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) | 1656 | static inline u32 gk20a_get_gr_idle_timeout(struct gk20a *g) |
1657 | { | 1657 | { |
1658 | return nvgpu_is_timeouts_enabled(g) ? | 1658 | return nvgpu_is_timeouts_enabled(g) ? |
1659 | g->gr_idle_timeout_default : ULONG_MAX; | 1659 | g->gr_idle_timeout_default : UINT_MAX; |
1660 | } | 1660 | } |
1661 | 1661 | ||
1662 | #define MULTICHAR_TAG(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) | 1662 | #define MULTICHAR_TAG(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d)) |
diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c index 6a49e83b..b4f553ec 100644 --- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c | |||
@@ -39,14 +39,9 @@ | |||
39 | 39 | ||
40 | #define VREG_COUNT 24 | 40 | #define VREG_COUNT 24 |
41 | 41 | ||
42 | #define GP106_MCLK_LOW_SPEED 0 | 42 | #define GP106_MEM_CONFIG_GDDR5_PG418 0U |
43 | #define GP106_MCLK_MID_SPEED 1 | 43 | #define GP106_MEM_CONFIG_GDDR5_PG419 1U |
44 | #define GP106_MCLK_HIGH_SPEED 2 | 44 | #define GP106_MEM_CONFIG_GDDR5_PG419_8606580012 2U |
45 | #define GP106_MCLK_NUM_SPEED 3 | ||
46 | |||
47 | #define GP106_MEM_CONFIG_GDDR5_PG418 0 | ||
48 | #define GP106_MEM_CONFIG_GDDR5_PG419 1 | ||
49 | #define GP106_MEM_CONFIG_GDDR5_PG419_8606580012 2 | ||
50 | 45 | ||
51 | struct memory_link_training_pattern { | 46 | struct memory_link_training_pattern { |
52 | u32 regaddr; | 47 | u32 regaddr; |
@@ -2939,7 +2934,7 @@ static int mclk_debugfs_init(struct gk20a *g); | |||
2939 | 2934 | ||
2940 | struct memory_config { | 2935 | struct memory_config { |
2941 | struct memory_link_training_pattern *pattern_ptr; | 2936 | struct memory_link_training_pattern *pattern_ptr; |
2942 | u32 pattern_size; | 2937 | size_t pattern_size; |
2943 | struct { | 2938 | struct { |
2944 | u8 *addr; | 2939 | u8 *addr; |
2945 | u32 size; | 2940 | u32 size; |
@@ -2949,7 +2944,7 @@ struct memory_config { | |||
2949 | #undef S | 2944 | #undef S |
2950 | #define S(from, to, script) \ | 2945 | #define S(from, to, script) \ |
2951 | [GP106_MCLK_##from##_SPEED][GP106_MCLK_##to##_SPEED] = \ | 2946 | [GP106_MCLK_##from##_SPEED][GP106_MCLK_##to##_SPEED] = \ |
2952 | { script, sizeof(script) } | 2947 | { script, (u32)sizeof(script) } |
2953 | 2948 | ||
2954 | static struct memory_config mem_config[] = { | 2949 | static struct memory_config mem_config[] = { |
2955 | [GP106_MEM_CONFIG_GDDR5_PG418] = { | 2950 | [GP106_MEM_CONFIG_GDDR5_PG418] = { |
@@ -2998,7 +2993,8 @@ static void mclk_seq_pmucmdhandler(struct gk20a *g, struct pmu_msg *_msg, | |||
2998 | { | 2993 | { |
2999 | struct nv_pmu_seq_msg *msg = (struct nv_pmu_seq_msg *)_msg; | 2994 | struct nv_pmu_seq_msg *msg = (struct nv_pmu_seq_msg *)_msg; |
3000 | struct nv_pmu_seq_msg_run_script *seq_msg; | 2995 | struct nv_pmu_seq_msg_run_script *seq_msg; |
3001 | u32 msg_status = 0; | 2996 | int msg_status = 0; |
2997 | bool *seq_running = (bool *)param; /* to report back completion */ | ||
3002 | 2998 | ||
3003 | nvgpu_log_info(g, " "); | 2999 | nvgpu_log_info(g, " "); |
3004 | 3000 | ||
@@ -3021,7 +3017,7 @@ static void mclk_seq_pmucmdhandler(struct gk20a *g, struct pmu_msg *_msg, | |||
3021 | } | 3017 | } |
3022 | 3018 | ||
3023 | status_update: | 3019 | status_update: |
3024 | *((u32 *)param) = msg_status; | 3020 | *seq_running = (msg_status != 0); |
3025 | } | 3021 | } |
3026 | 3022 | ||
3027 | static int mclk_get_memclk_table(struct gk20a *g) | 3023 | static int mclk_get_memclk_table(struct gk20a *g) |
@@ -3087,8 +3083,8 @@ static int mclk_get_memclk_table(struct gk20a *g) | |||
3087 | VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX); | 3083 | VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX); |
3088 | 3084 | ||
3089 | script_ptr = nvgpu_bios_read_u32(g, | 3085 | script_ptr = nvgpu_bios_read_u32(g, |
3090 | memclock_table_header.script_list_ptr + | 3086 | (u32)(memclock_table_header.script_list_ptr + |
3091 | script_index * sizeof(u32)); | 3087 | script_index * sizeof(u32))); |
3092 | 3088 | ||
3093 | if (!script_ptr) { | 3089 | if (!script_ptr) { |
3094 | continue; | 3090 | continue; |
@@ -3142,8 +3138,8 @@ static int mclk_get_memclk_table(struct gk20a *g) | |||
3142 | VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX); | 3138 | VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX); |
3143 | 3139 | ||
3144 | cmd_script_ptr = nvgpu_bios_read_u32(g, | 3140 | cmd_script_ptr = nvgpu_bios_read_u32(g, |
3145 | memclock_table_header.cmd_script_list_ptr + | 3141 | (u32)(memclock_table_header.cmd_script_list_ptr + |
3146 | cmd_script_index * sizeof(u32)); | 3142 | cmd_script_index * sizeof(u32))); |
3147 | 3143 | ||
3148 | if (!cmd_script_ptr) { | 3144 | if (!cmd_script_ptr) { |
3149 | continue; | 3145 | continue; |
@@ -3268,14 +3264,14 @@ int gp106_mclk_init(struct gk20a *g) | |||
3268 | 3264 | ||
3269 | p5_info = pstate_get_clk_set_info(g, | 3265 | p5_info = pstate_get_clk_set_info(g, |
3270 | CTRL_PERF_PSTATE_P5, clkwhich_mclk); | 3266 | CTRL_PERF_PSTATE_P5, clkwhich_mclk); |
3271 | if (!p5_info) { | 3267 | if (p5_info == NULL) { |
3272 | err = -EINVAL; | 3268 | err = -EINVAL; |
3273 | goto fail_data_mutex; | 3269 | goto fail_data_mutex; |
3274 | } | 3270 | } |
3275 | 3271 | ||
3276 | p0_info = pstate_get_clk_set_info(g, | 3272 | p0_info = pstate_get_clk_set_info(g, |
3277 | CTRL_PERF_PSTATE_P0, clkwhich_mclk); | 3273 | CTRL_PERF_PSTATE_P0, clkwhich_mclk); |
3278 | if (!p0_info) { | 3274 | if (p0_info == NULL) { |
3279 | err = -EINVAL; | 3275 | err = -EINVAL; |
3280 | goto fail_data_mutex; | 3276 | goto fail_data_mutex; |
3281 | } | 3277 | } |
@@ -3284,7 +3280,7 @@ int gp106_mclk_init(struct gk20a *g) | |||
3284 | mclk->p0_min = p0_info->min_mhz; | 3280 | mclk->p0_min = p0_info->min_mhz; |
3285 | 3281 | ||
3286 | mclk->vreg_buf = nvgpu_kcalloc(g, VREG_COUNT, sizeof(u32)); | 3282 | mclk->vreg_buf = nvgpu_kcalloc(g, VREG_COUNT, sizeof(u32)); |
3287 | if (!mclk->vreg_buf) { | 3283 | if (mclk->vreg_buf == NULL) { |
3288 | nvgpu_err(g, "unable to allocate memory for VREG"); | 3284 | nvgpu_err(g, "unable to allocate memory for VREG"); |
3289 | err = -ENOMEM; | 3285 | err = -ENOMEM; |
3290 | goto fail_data_mutex; | 3286 | goto fail_data_mutex; |
@@ -3318,13 +3314,14 @@ int gp106_mclk_change(struct gk20a *g, u16 val) | |||
3318 | int status = 0; | 3314 | int status = 0; |
3319 | struct memory_config *m = &mem_config[g->mem_config_idx]; | 3315 | struct memory_config *m = &mem_config[g->mem_config_idx]; |
3320 | 3316 | ||
3321 | u32 seq_completion_status = ~0x0; | 3317 | bool seq_running = true; |
3322 | u8 *seq_script_ptr = NULL; | 3318 | u8 *seq_script_ptr = NULL; |
3323 | size_t seq_script_size = 0; | 3319 | u32 seq_script_size = 0; |
3324 | #ifdef CONFIG_DEBUG_FS | 3320 | #ifdef CONFIG_DEBUG_FS |
3325 | u64 t0, t1; | 3321 | u64 t0, t1; |
3326 | #endif | 3322 | #endif |
3327 | u32 speed; | 3323 | u32 speed; |
3324 | u64 cmd_hdr_size; | ||
3328 | 3325 | ||
3329 | nvgpu_log_info(g, " "); | 3326 | nvgpu_log_info(g, " "); |
3330 | 3327 | ||
@@ -3357,8 +3354,14 @@ int gp106_mclk_change(struct gk20a *g, u16 val) | |||
3357 | /* Fill command header with SEQ ID & size */ | 3354 | /* Fill command header with SEQ ID & size */ |
3358 | memset(&cmd, 0, sizeof(cmd)); | 3355 | memset(&cmd, 0, sizeof(cmd)); |
3359 | cmd.hdr.unit_id = PMU_UNIT_SEQ; | 3356 | cmd.hdr.unit_id = PMU_UNIT_SEQ; |
3360 | cmd.hdr.size = sizeof(struct nv_pmu_seq_cmd_run_script) + | 3357 | cmd_hdr_size = sizeof(struct nv_pmu_seq_cmd_run_script) + |
3361 | sizeof(struct pmu_hdr); | 3358 | sizeof(struct pmu_hdr); |
3359 | if (cmd_hdr_size > U8_MAX) { | ||
3360 | nvgpu_err(g, "Invalid command header size"); | ||
3361 | status = -EINVAL; | ||
3362 | goto exit_status; | ||
3363 | } | ||
3364 | cmd.hdr.size = (u8)cmd_hdr_size; | ||
3362 | 3365 | ||
3363 | /* Fill RM_PMU_SEQ_CMD_RUN_SCRIPT struct */ | 3366 | /* Fill RM_PMU_SEQ_CMD_RUN_SCRIPT struct */ |
3364 | pseq_cmd = &cmd.run_script; | 3367 | pseq_cmd = &cmd.run_script; |
@@ -3379,24 +3382,24 @@ int gp106_mclk_change(struct gk20a *g, u16 val) | |||
3379 | 3382 | ||
3380 | /* Read sequencer binary*/ | 3383 | /* Read sequencer binary*/ |
3381 | payload.in.buf = seq_script_ptr; | 3384 | payload.in.buf = seq_script_ptr; |
3382 | payload.in.size = seq_script_size; | 3385 | payload.in.size = (u32)seq_script_size; |
3383 | payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; | 3386 | payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; |
3384 | payload.in.offset = offsetof(struct nv_pmu_seq_cmd_run_script, | 3387 | payload.in.offset = (u32)offsetof(struct nv_pmu_seq_cmd_run_script, |
3385 | script_alloc); | 3388 | script_alloc); |
3386 | 3389 | ||
3387 | memset(mclk->vreg_buf, 0, (sizeof(u32) * VREG_COUNT)); | 3390 | memset(mclk->vreg_buf, 0, (sizeof(u32) * VREG_COUNT)); |
3388 | 3391 | ||
3389 | payload.out.buf = mclk->vreg_buf; | 3392 | payload.out.buf = mclk->vreg_buf; |
3390 | payload.out.size = (VREG_COUNT * sizeof(u32)); | 3393 | payload.out.size = (VREG_COUNT * (u32)sizeof(u32)); |
3391 | payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; | 3394 | payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED; |
3392 | payload.out.offset = offsetof(struct nv_pmu_seq_cmd_run_script, | 3395 | payload.out.offset = (u32)offsetof(struct nv_pmu_seq_cmd_run_script, |
3393 | reg_alloc); | 3396 | reg_alloc); |
3394 | 3397 | ||
3395 | /* Send command to PMU to execute sequencer script */ | 3398 | /* Send command to PMU to execute sequencer script */ |
3396 | status = nvgpu_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload, | 3399 | status = nvgpu_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload, |
3397 | PMU_COMMAND_QUEUE_LPQ, | 3400 | PMU_COMMAND_QUEUE_LPQ, |
3398 | mclk_seq_pmucmdhandler, | 3401 | mclk_seq_pmucmdhandler, |
3399 | &seq_completion_status, &seqdesc, ~0); | 3402 | &seq_running, &seqdesc, ~0UL); |
3400 | if (status) { | 3403 | if (status) { |
3401 | nvgpu_err(g, "unable to post seq script exec cmd for unit %x", | 3404 | nvgpu_err(g, "unable to post seq script exec cmd for unit %x", |
3402 | cmd.hdr.unit_id); | 3405 | cmd.hdr.unit_id); |
@@ -3404,8 +3407,8 @@ int gp106_mclk_change(struct gk20a *g, u16 val) | |||
3404 | } | 3407 | } |
3405 | /* wait till sequencer script complete */ | 3408 | /* wait till sequencer script complete */ |
3406 | pmu_wait_message_cond(&g->pmu, (gk20a_get_gr_idle_timeout(g)), | 3409 | pmu_wait_message_cond(&g->pmu, (gk20a_get_gr_idle_timeout(g)), |
3407 | &seq_completion_status, 0); | 3410 | &seq_running, (u8)false); |
3408 | if (seq_completion_status != 0) { | 3411 | if (seq_running) { |
3409 | nvgpu_err(g, "seq_script update failed"); | 3412 | nvgpu_err(g, "seq_script update failed"); |
3410 | status = -EBUSY; | 3413 | status = -EBUSY; |
3411 | goto exit_status; | 3414 | goto exit_status; |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 92e0165f..2fb700f0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -2169,7 +2169,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g, | |||
2169 | struct nvgpu_timeout timeout; | 2169 | struct nvgpu_timeout timeout; |
2170 | 2170 | ||
2171 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, | 2171 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, |
2172 | "CILP preempt pending, waiting %lu msecs for preemption", | 2172 | "CILP preempt pending, waiting %u msecs for preemption", |
2173 | gk20a_get_gr_idle_timeout(g)); | 2173 | gk20a_get_gr_idle_timeout(g)); |
2174 | 2174 | ||
2175 | tsg = tsg_gk20a_from_ch(cilp_preempt_pending_ch); | 2175 | tsg = tsg_gk20a_from_ch(cilp_preempt_pending_ch); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 10b220b7..5965d177 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -596,10 +596,12 @@ struct vbios_memory_clock_base_entry_11 { | |||
596 | 596 | ||
597 | /* Script Pointer Index */ | 597 | /* Script Pointer Index */ |
598 | /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX 3:2*/ | 598 | /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX 3:2*/ |
599 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK 0xc | 599 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK \ |
600 | ((u8)0xc) | ||
600 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2 | 601 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT 2 |
601 | /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX 1:0*/ | 602 | /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX 1:0*/ |
602 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK 0x3 | 603 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK \ |
604 | ((u8)0x3) | ||
603 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 | 605 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 |
604 | 606 | ||
605 | #define VBIOS_POWER_SENSORS_VERSION_2X 0x20 | 607 | #define VBIOS_POWER_SENSORS_VERSION_2X 0x20 |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/types.h b/drivers/gpu/nvgpu/include/nvgpu/types.h index 8320721b..d4d88d4d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/types.h +++ b/drivers/gpu/nvgpu/include/nvgpu/types.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -60,4 +60,11 @@ | |||
60 | #define U32(x) ((u32)(x)) | 60 | #define U32(x) ((u32)(x)) |
61 | #define U64(x) ((u64)(x)) | 61 | #define U64(x) ((u64)(x)) |
62 | 62 | ||
63 | /* Linux uses U8_MAX instead of UCHAR_MAX. We define it here for non-Linux | ||
64 | * OSes | ||
65 | */ | ||
66 | #if !defined(__KERNEL__) && !defined(U8_MAX) | ||
67 | #define U8_MAX ((u8)255) | ||
68 | #endif | ||
69 | |||
63 | #endif | 70 | #endif |
diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h index 55726d55..0860b46e 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.h +++ b/drivers/gpu/nvgpu/pstate/pstate.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * general p state infrastructure | 2 | * general p state infrastructure |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -39,8 +39,8 @@ struct gk20a; | |||
39 | struct clk_set_info { | 39 | struct clk_set_info { |
40 | enum nv_pmu_clk_clkwhich clkwhich; | 40 | enum nv_pmu_clk_clkwhich clkwhich; |
41 | u32 nominal_mhz; | 41 | u32 nominal_mhz; |
42 | u32 min_mhz; | 42 | u16 min_mhz; |
43 | u32 max_mhz; | 43 | u16 max_mhz; |
44 | }; | 44 | }; |
45 | 45 | ||
46 | struct clk_set_info_list { | 46 | struct clk_set_info_list { |