diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fb_gk20a.c | 101 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fb_gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 103 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fb_gm20b.c | 72 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.c | 69 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mm_gm20b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/mm_vgpu.c | 10 |
15 files changed, 197 insertions, 187 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index e2a97caa..5a4a2251 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -385,7 +385,7 @@ static int nvgpu_gpu_ioctl_set_mmu_debug_mode( | |||
385 | } | 385 | } |
386 | 386 | ||
387 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 387 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
388 | g->ops.mm.set_debug_mode(g, args->state == 1); | 388 | g->ops.fb.set_debug_mode(g, args->state == 1); |
389 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 389 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
390 | 390 | ||
391 | gk20a_idle(g->dev); | 391 | gk20a_idle(g->dev); |
diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c index 1efa56fb..4b8baad5 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c | |||
@@ -14,6 +14,8 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <trace/events/gk20a.h> | ||
18 | #include <linux/delay.h> | ||
17 | 19 | ||
18 | #include "gk20a.h" | 20 | #include "gk20a.h" |
19 | #include "kind_gk20a.h" | 21 | #include "kind_gk20a.h" |
@@ -40,6 +42,13 @@ void fb_gk20a_reset(struct gk20a *g) | |||
40 | gk20a_writel(g, mc_elpg_enable_r(), val); | 42 | gk20a_writel(g, mc_elpg_enable_r(), val); |
41 | } | 43 | } |
42 | 44 | ||
45 | void gk20a_fb_init_hw(struct gk20a *g) | ||
46 | { | ||
47 | gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), | ||
48 | g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0) | ||
49 | >> 8); | ||
50 | } | ||
51 | |||
43 | static void gk20a_fb_set_mmu_page_size(struct gk20a *g) | 52 | static void gk20a_fb_set_mmu_page_size(struct gk20a *g) |
44 | { | 53 | { |
45 | /* set large page size in fb */ | 54 | /* set large page size in fb */ |
@@ -62,12 +71,104 @@ static unsigned int gk20a_fb_compressible_page_size(struct gk20a *g) | |||
62 | return SZ_64K; | 71 | return SZ_64K; |
63 | } | 72 | } |
64 | 73 | ||
74 | bool gk20a_fb_debug_mode_enabled(struct gk20a *g) | ||
75 | { | ||
76 | u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
77 | return fb_mmu_debug_ctrl_debug_v(debug_ctrl) == | ||
78 | fb_mmu_debug_ctrl_debug_enabled_v(); | ||
79 | } | ||
80 | |||
81 | static void gk20a_fb_set_debug_mode(struct gk20a *g, bool enable) | ||
82 | { | ||
83 | u32 reg_val, debug_ctrl; | ||
84 | |||
85 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
86 | if (enable) { | ||
87 | debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
88 | g->mmu_debug_ctrl = true; | ||
89 | } else { | ||
90 | debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
91 | g->mmu_debug_ctrl = false; | ||
92 | } | ||
93 | |||
94 | reg_val = set_field(reg_val, | ||
95 | fb_mmu_debug_ctrl_debug_m(), debug_ctrl); | ||
96 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | ||
97 | } | ||
98 | |||
99 | void gk20a_fb_tlb_invalidate(struct gk20a *g, struct mem_desc *pdb) | ||
100 | { | ||
101 | struct nvgpu_timeout timeout; | ||
102 | u32 addr_lo; | ||
103 | u32 data; | ||
104 | |||
105 | gk20a_dbg_fn(""); | ||
106 | |||
107 | /* pagetables are considered sw states which are preserved after | ||
108 | prepare_poweroff. When gk20a deinit releases those pagetables, | ||
109 | common code in vm unmap path calls tlb invalidate that touches | ||
110 | hw. Use the power_on flag to skip tlb invalidation when gpu | ||
111 | power is turned off */ | ||
112 | |||
113 | if (!g->power_on) | ||
114 | return; | ||
115 | |||
116 | addr_lo = u64_lo32(gk20a_mem_get_base_addr(g, pdb, 0) >> 12); | ||
117 | |||
118 | nvgpu_mutex_acquire(&g->mm.tlb_lock); | ||
119 | |||
120 | trace_gk20a_mm_tlb_invalidate(dev_name(g->dev)); | ||
121 | |||
122 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); | ||
123 | |||
124 | do { | ||
125 | data = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
126 | if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0) | ||
127 | break; | ||
128 | udelay(2); | ||
129 | } while (!nvgpu_timeout_expired_msg(&timeout, | ||
130 | "wait mmu fifo space")); | ||
131 | |||
132 | if (nvgpu_timeout_peek_expired(&timeout)) | ||
133 | goto out; | ||
134 | |||
135 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); | ||
136 | |||
137 | gk20a_writel(g, fb_mmu_invalidate_pdb_r(), | ||
138 | fb_mmu_invalidate_pdb_addr_f(addr_lo) | | ||
139 | gk20a_aperture_mask(g, pdb, | ||
140 | fb_mmu_invalidate_pdb_aperture_sys_mem_f(), | ||
141 | fb_mmu_invalidate_pdb_aperture_vid_mem_f())); | ||
142 | |||
143 | gk20a_writel(g, fb_mmu_invalidate_r(), | ||
144 | fb_mmu_invalidate_all_va_true_f() | | ||
145 | fb_mmu_invalidate_trigger_true_f()); | ||
146 | |||
147 | do { | ||
148 | data = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
149 | if (fb_mmu_ctrl_pri_fifo_empty_v(data) != | ||
150 | fb_mmu_ctrl_pri_fifo_empty_false_f()) | ||
151 | break; | ||
152 | udelay(2); | ||
153 | } while (!nvgpu_timeout_expired_msg(&timeout, | ||
154 | "wait mmu invalidate")); | ||
155 | |||
156 | trace_gk20a_mm_tlb_invalidate_done(dev_name(g->dev)); | ||
157 | |||
158 | out: | ||
159 | nvgpu_mutex_release(&g->mm.tlb_lock); | ||
160 | } | ||
161 | |||
65 | void gk20a_init_fb(struct gpu_ops *gops) | 162 | void gk20a_init_fb(struct gpu_ops *gops) |
66 | { | 163 | { |
164 | gops->fb.init_hw = gk20a_fb_init_hw; | ||
67 | gops->fb.reset = fb_gk20a_reset; | 165 | gops->fb.reset = fb_gk20a_reset; |
68 | gops->fb.set_mmu_page_size = gk20a_fb_set_mmu_page_size; | 166 | gops->fb.set_mmu_page_size = gk20a_fb_set_mmu_page_size; |
69 | gops->fb.compression_page_size = gk20a_fb_compression_page_size; | 167 | gops->fb.compression_page_size = gk20a_fb_compression_page_size; |
70 | gops->fb.compressible_page_size = gk20a_fb_compressible_page_size; | 168 | gops->fb.compressible_page_size = gk20a_fb_compressible_page_size; |
169 | gops->fb.is_debug_mode_enabled = gk20a_fb_debug_mode_enabled; | ||
170 | gops->fb.set_debug_mode = gk20a_fb_set_debug_mode; | ||
171 | gops->fb.tlb_invalidate = gk20a_fb_tlb_invalidate; | ||
71 | gk20a_init_uncompressed_kind_map(); | 172 | gk20a_init_uncompressed_kind_map(); |
72 | gk20a_init_kind_attr(); | 173 | gk20a_init_kind_attr(); |
73 | } | 174 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.h b/drivers/gpu/nvgpu/gk20a/fb_gk20a.h index e5ea9e42..a808ba6d 100644 --- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.h | |||
@@ -13,8 +13,13 @@ | |||
13 | 13 | ||
14 | #ifndef FB_GK20A_H | 14 | #ifndef FB_GK20A_H |
15 | #define FB_GK20A_H | 15 | #define FB_GK20A_H |
16 | |||
16 | struct gk20a; | 17 | struct gk20a; |
18 | struct mem_desc; | ||
17 | 19 | ||
18 | void gk20a_init_fb(struct gpu_ops *gops); | 20 | void gk20a_init_fb(struct gpu_ops *gops); |
19 | void fb_gk20a_reset(struct gk20a *g); | 21 | void fb_gk20a_reset(struct gk20a *g); |
22 | void gk20a_fb_init_hw(struct gk20a *g); | ||
23 | void gk20a_fb_tlb_invalidate(struct gk20a *g, struct mem_desc *pdb); | ||
24 | |||
20 | #endif | 25 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index de1c82dc..edc0f13d 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1267,7 +1267,7 @@ static bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id, | |||
1267 | /* channel recovery is only deferred if an sm debugger | 1267 | /* channel recovery is only deferred if an sm debugger |
1268 | is attached and has MMU debug mode is enabled */ | 1268 | is attached and has MMU debug mode is enabled */ |
1269 | if (!gk20a_gr_sm_debugger_attached(g) || | 1269 | if (!gk20a_gr_sm_debugger_attached(g) || |
1270 | !g->ops.mm.is_debug_mode_enabled(g)) | 1270 | !g->ops.fb.is_debug_mode_enabled(g)) |
1271 | return false; | 1271 | return false; |
1272 | 1272 | ||
1273 | /* if this fault is fake (due to RC recovery), don't defer recovery */ | 1273 | /* if this fault is fake (due to RC recovery), don't defer recovery */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index e995dcbf..30c0f2fb 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1083,7 +1083,7 @@ int gk20a_pm_finalize_poweron(struct device *dev) | |||
1083 | } | 1083 | } |
1084 | 1084 | ||
1085 | /* Restore the debug setting */ | 1085 | /* Restore the debug setting */ |
1086 | g->ops.mm.set_debug_mode(g, g->mmu_debug_ctrl); | 1086 | g->ops.fb.set_debug_mode(g, g->mmu_debug_ctrl); |
1087 | 1087 | ||
1088 | gk20a_channel_resume(g); | 1088 | gk20a_channel_resume(g); |
1089 | set_user_nice(current, nice_value); | 1089 | set_user_nice(current, nice_value); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 695d2d1a..73123fa9 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -349,6 +349,7 @@ struct gpu_ops { | |||
349 | } gr; | 349 | } gr; |
350 | const char *name; | 350 | const char *name; |
351 | struct { | 351 | struct { |
352 | void (*init_hw)(struct gk20a *g); | ||
352 | void (*init_fs_state)(struct gk20a *g); | 353 | void (*init_fs_state)(struct gk20a *g); |
353 | void (*reset)(struct gk20a *g); | 354 | void (*reset)(struct gk20a *g); |
354 | void (*init_uncompressed_kind_map)(struct gk20a *g); | 355 | void (*init_uncompressed_kind_map)(struct gk20a *g); |
@@ -358,6 +359,10 @@ struct gpu_ops { | |||
358 | unsigned int (*compression_page_size)(struct gk20a *g); | 359 | unsigned int (*compression_page_size)(struct gk20a *g); |
359 | unsigned int (*compressible_page_size)(struct gk20a *g); | 360 | unsigned int (*compressible_page_size)(struct gk20a *g); |
360 | void (*dump_vpr_wpr_info)(struct gk20a *g); | 361 | void (*dump_vpr_wpr_info)(struct gk20a *g); |
362 | int (*vpr_info_fetch)(struct gk20a *g); | ||
363 | bool (*is_debug_mode_enabled)(struct gk20a *g); | ||
364 | void (*set_debug_mode)(struct gk20a *g, bool enable); | ||
365 | void (*tlb_invalidate)(struct gk20a *g, struct mem_desc *pdb); | ||
361 | } fb; | 366 | } fb; |
362 | struct { | 367 | struct { |
363 | void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); | 368 | void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); |
@@ -573,8 +578,6 @@ struct gpu_ops { | |||
573 | } fecs_trace; | 578 | } fecs_trace; |
574 | struct { | 579 | struct { |
575 | bool (*support_sparse)(struct gk20a *g); | 580 | bool (*support_sparse)(struct gk20a *g); |
576 | bool (*is_debug_mode_enabled)(struct gk20a *g); | ||
577 | void (*set_debug_mode)(struct gk20a *g, bool enable); | ||
578 | u64 (*gmmu_map)(struct vm_gk20a *vm, | 581 | u64 (*gmmu_map)(struct vm_gk20a *vm, |
579 | u64 map_offset, | 582 | u64 map_offset, |
580 | struct sg_table *sgt, | 583 | struct sg_table *sgt, |
@@ -607,7 +610,6 @@ struct gpu_ops { | |||
607 | void (*l2_invalidate)(struct gk20a *g); | 610 | void (*l2_invalidate)(struct gk20a *g); |
608 | void (*l2_flush)(struct gk20a *g, bool invalidate); | 611 | void (*l2_flush)(struct gk20a *g, bool invalidate); |
609 | void (*cbc_clean)(struct gk20a *g); | 612 | void (*cbc_clean)(struct gk20a *g); |
610 | void (*tlb_invalidate)(struct vm_gk20a *vm); | ||
611 | void (*set_big_page_size)(struct gk20a *g, | 613 | void (*set_big_page_size)(struct gk20a *g, |
612 | struct mem_desc *mem, int size); | 614 | struct mem_desc *mem, int size); |
613 | u32 (*get_big_page_sizes)(void); | 615 | u32 (*get_big_page_sizes)(void); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 4dec9e99..2451786b 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8583,7 +8583,7 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | |||
8583 | bool locked_down; | 8583 | bool locked_down; |
8584 | bool no_error_pending; | 8584 | bool no_error_pending; |
8585 | u32 delay = GR_IDLE_CHECK_DEFAULT; | 8585 | u32 delay = GR_IDLE_CHECK_DEFAULT; |
8586 | bool mmu_debug_mode_enabled = g->ops.mm.is_debug_mode_enabled(g); | 8586 | bool mmu_debug_mode_enabled = g->ops.fb.is_debug_mode_enabled(g); |
8587 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 8587 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); |
8588 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | 8588 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); |
8589 | u32 offset = | 8589 | u32 offset = |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index dd62ab42..32d1f32f 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -42,7 +42,6 @@ | |||
42 | #include "kind_gk20a.h" | 42 | #include "kind_gk20a.h" |
43 | 43 | ||
44 | #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h> | 44 | #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h> |
45 | #include <nvgpu/hw/gk20a/hw_fb_gk20a.h> | ||
46 | #include <nvgpu/hw/gk20a/hw_bus_gk20a.h> | 45 | #include <nvgpu/hw/gk20a/hw_bus_gk20a.h> |
47 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 46 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
48 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> | 47 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> |
@@ -1084,9 +1083,7 @@ int gk20a_init_mm_setup_hw(struct gk20a *g) | |||
1084 | mm->use_full_comp_tag_line = | 1083 | mm->use_full_comp_tag_line = |
1085 | g->ops.fb.set_use_full_comp_tag_line(g); | 1084 | g->ops.fb.set_use_full_comp_tag_line(g); |
1086 | 1085 | ||
1087 | gk20a_writel(g, fb_niso_flush_sysmem_addr_r(), | 1086 | g->ops.fb.init_hw(g); |
1088 | g->ops.mm.get_iova_addr(g, g->mm.sysmem_flush.sgt->sgl, 0) | ||
1089 | >> 8); | ||
1090 | 1087 | ||
1091 | if (g->ops.mm.bar1_bind) | 1088 | if (g->ops.mm.bar1_bind) |
1092 | g->ops.mm.bar1_bind(g, &mm->bar1.inst_block); | 1089 | g->ops.mm.bar1_bind(g, &mm->bar1.inst_block); |
@@ -1538,7 +1535,7 @@ void gk20a_vm_mapping_batch_finish_locked( | |||
1538 | 1535 | ||
1539 | if (mapping_batch->need_tlb_invalidate) { | 1536 | if (mapping_batch->need_tlb_invalidate) { |
1540 | struct gk20a *g = gk20a_from_vm(vm); | 1537 | struct gk20a *g = gk20a_from_vm(vm); |
1541 | g->ops.mm.tlb_invalidate(vm); | 1538 | g->ops.fb.tlb_invalidate(g, &vm->pdb.mem); |
1542 | } | 1539 | } |
1543 | } | 1540 | } |
1544 | 1541 | ||
@@ -1959,7 +1956,7 @@ u64 gk20a_locked_gmmu_map(struct vm_gk20a *vm, | |||
1959 | } | 1956 | } |
1960 | 1957 | ||
1961 | if (!batch) | 1958 | if (!batch) |
1962 | g->ops.mm.tlb_invalidate(vm); | 1959 | g->ops.fb.tlb_invalidate(g, &vm->pdb.mem); |
1963 | else | 1960 | else |
1964 | batch->need_tlb_invalidate = true; | 1961 | batch->need_tlb_invalidate = true; |
1965 | 1962 | ||
@@ -2018,7 +2015,7 @@ void gk20a_locked_gmmu_unmap(struct vm_gk20a *vm, | |||
2018 | 2015 | ||
2019 | if (!batch) { | 2016 | if (!batch) { |
2020 | gk20a_mm_l2_flush(g, true); | 2017 | gk20a_mm_l2_flush(g, true); |
2021 | g->ops.mm.tlb_invalidate(vm); | 2018 | g->ops.fb.tlb_invalidate(g, &vm->pdb.mem); |
2022 | } else { | 2019 | } else { |
2023 | if (!batch->gpu_l2_flushed) { | 2020 | if (!batch->gpu_l2_flushed) { |
2024 | gk20a_mm_l2_flush(g, true); | 2021 | gk20a_mm_l2_flush(g, true); |
@@ -5344,70 +5341,6 @@ int gk20a_vm_find_buffer(struct vm_gk20a *vm, u64 gpu_va, | |||
5344 | return 0; | 5341 | return 0; |
5345 | } | 5342 | } |
5346 | 5343 | ||
5347 | void gk20a_mm_tlb_invalidate(struct vm_gk20a *vm) | ||
5348 | { | ||
5349 | struct gk20a *g = gk20a_from_vm(vm); | ||
5350 | struct nvgpu_timeout timeout; | ||
5351 | u32 addr_lo; | ||
5352 | u32 data; | ||
5353 | |||
5354 | gk20a_dbg_fn(""); | ||
5355 | |||
5356 | /* pagetables are considered sw states which are preserved after | ||
5357 | prepare_poweroff. When gk20a deinit releases those pagetables, | ||
5358 | common code in vm unmap path calls tlb invalidate that touches | ||
5359 | hw. Use the power_on flag to skip tlb invalidation when gpu | ||
5360 | power is turned off */ | ||
5361 | |||
5362 | if (!g->power_on) | ||
5363 | return; | ||
5364 | |||
5365 | addr_lo = u64_lo32(gk20a_mem_get_base_addr(g, &vm->pdb.mem, 0) >> 12); | ||
5366 | |||
5367 | nvgpu_mutex_acquire(&g->mm.tlb_lock); | ||
5368 | |||
5369 | trace_gk20a_mm_tlb_invalidate(dev_name(g->dev)); | ||
5370 | |||
5371 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); | ||
5372 | |||
5373 | do { | ||
5374 | data = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
5375 | if (fb_mmu_ctrl_pri_fifo_space_v(data) != 0) | ||
5376 | break; | ||
5377 | udelay(2); | ||
5378 | } while (!nvgpu_timeout_expired_msg(&timeout, | ||
5379 | "wait mmu fifo space")); | ||
5380 | |||
5381 | if (nvgpu_timeout_peek_expired(&timeout)) | ||
5382 | goto out; | ||
5383 | |||
5384 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); | ||
5385 | |||
5386 | gk20a_writel(g, fb_mmu_invalidate_pdb_r(), | ||
5387 | fb_mmu_invalidate_pdb_addr_f(addr_lo) | | ||
5388 | gk20a_aperture_mask(g, &vm->pdb.mem, | ||
5389 | fb_mmu_invalidate_pdb_aperture_sys_mem_f(), | ||
5390 | fb_mmu_invalidate_pdb_aperture_vid_mem_f())); | ||
5391 | |||
5392 | gk20a_writel(g, fb_mmu_invalidate_r(), | ||
5393 | fb_mmu_invalidate_all_va_true_f() | | ||
5394 | fb_mmu_invalidate_trigger_true_f()); | ||
5395 | |||
5396 | do { | ||
5397 | data = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
5398 | if (fb_mmu_ctrl_pri_fifo_empty_v(data) != | ||
5399 | fb_mmu_ctrl_pri_fifo_empty_false_f()) | ||
5400 | break; | ||
5401 | udelay(2); | ||
5402 | } while (!nvgpu_timeout_expired_msg(&timeout, | ||
5403 | "wait mmu invalidate")); | ||
5404 | |||
5405 | trace_gk20a_mm_tlb_invalidate_done(dev_name(g->dev)); | ||
5406 | |||
5407 | out: | ||
5408 | nvgpu_mutex_release(&g->mm.tlb_lock); | ||
5409 | } | ||
5410 | |||
5411 | int gk20a_mm_suspend(struct gk20a *g) | 5344 | int gk20a_mm_suspend(struct gk20a *g) |
5412 | { | 5345 | { |
5413 | gk20a_dbg_fn(""); | 5346 | gk20a_dbg_fn(""); |
@@ -5423,31 +5356,6 @@ int gk20a_mm_suspend(struct gk20a *g) | |||
5423 | return 0; | 5356 | return 0; |
5424 | } | 5357 | } |
5425 | 5358 | ||
5426 | bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g) | ||
5427 | { | ||
5428 | u32 debug_ctrl = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
5429 | return fb_mmu_debug_ctrl_debug_v(debug_ctrl) == | ||
5430 | fb_mmu_debug_ctrl_debug_enabled_v(); | ||
5431 | } | ||
5432 | |||
5433 | static void gk20a_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) | ||
5434 | { | ||
5435 | u32 reg_val, debug_ctrl; | ||
5436 | |||
5437 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
5438 | if (enable) { | ||
5439 | debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
5440 | g->mmu_debug_ctrl = true; | ||
5441 | } else { | ||
5442 | debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
5443 | g->mmu_debug_ctrl = false; | ||
5444 | } | ||
5445 | |||
5446 | reg_val = set_field(reg_val, | ||
5447 | fb_mmu_debug_ctrl_debug_m(), debug_ctrl); | ||
5448 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | ||
5449 | } | ||
5450 | |||
5451 | u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g) | 5359 | u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g) |
5452 | { | 5360 | { |
5453 | return 34; | 5361 | return 34; |
@@ -5510,8 +5418,6 @@ void gk20a_mm_debugfs_init(struct device *dev) | |||
5510 | 5418 | ||
5511 | void gk20a_init_mm(struct gpu_ops *gops) | 5419 | void gk20a_init_mm(struct gpu_ops *gops) |
5512 | { | 5420 | { |
5513 | gops->mm.is_debug_mode_enabled = gk20a_mm_mmu_debug_mode_enabled; | ||
5514 | gops->mm.set_debug_mode = gk20a_mm_mmu_set_debug_mode; | ||
5515 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; | 5421 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; |
5516 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; | 5422 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; |
5517 | gops->mm.vm_remove = gk20a_vm_remove_support; | 5423 | gops->mm.vm_remove = gk20a_vm_remove_support; |
@@ -5521,7 +5427,6 @@ void gk20a_init_mm(struct gpu_ops *gops) | |||
5521 | gops->mm.l2_invalidate = gk20a_mm_l2_invalidate; | 5427 | gops->mm.l2_invalidate = gk20a_mm_l2_invalidate; |
5522 | gops->mm.l2_flush = gk20a_mm_l2_flush; | 5428 | gops->mm.l2_flush = gk20a_mm_l2_flush; |
5523 | gops->mm.cbc_clean = gk20a_mm_cbc_clean; | 5429 | gops->mm.cbc_clean = gk20a_mm_cbc_clean; |
5524 | gops->mm.tlb_invalidate = gk20a_mm_tlb_invalidate; | ||
5525 | gops->mm.get_iova_addr = gk20a_mm_iova_addr; | 5430 | gops->mm.get_iova_addr = gk20a_mm_iova_addr; |
5526 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; | 5431 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; |
5527 | gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; | 5432 | gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; |
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h index 6c713e49..0d3547e1 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h | |||
@@ -679,9 +679,6 @@ void gk20a_vm_put_buffers(struct vm_gk20a *vm, | |||
679 | struct mapped_buffer_node **mapped_buffers, | 679 | struct mapped_buffer_node **mapped_buffers, |
680 | int num_buffers); | 680 | int num_buffers); |
681 | 681 | ||
682 | /* invalidate tlbs for the vm area */ | ||
683 | void gk20a_mm_tlb_invalidate(struct vm_gk20a *vm); | ||
684 | |||
685 | /* find buffer corresponding to va */ | 682 | /* find buffer corresponding to va */ |
686 | int gk20a_vm_find_buffer(struct vm_gk20a *vm, u64 gpu_va, | 683 | int gk20a_vm_find_buffer(struct vm_gk20a *vm, u64 gpu_va, |
687 | struct dma_buf **dmabuf, | 684 | struct dma_buf **dmabuf, |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 2d932b67..bcad4437 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -397,7 +397,7 @@ int prepare_ucode_blob(struct gk20a *g) | |||
397 | plsfm = &lsfm_l; | 397 | plsfm = &lsfm_l; |
398 | memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr)); | 398 | memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr)); |
399 | gm20b_dbg_pmu("fetching GMMU regs\n"); | 399 | gm20b_dbg_pmu("fetching GMMU regs\n"); |
400 | gm20b_mm_mmu_vpr_info_fetch(g); | 400 | g->ops.fb.vpr_info_fetch(g); |
401 | gr_gk20a_init_ctxsw_ucode(g); | 401 | gr_gk20a_init_ctxsw_ucode(g); |
402 | 402 | ||
403 | g->ops.pmu.get_wpr(g, &wpr_inf); | 403 | g->ops.pmu.get_wpr(g, &wpr_inf); |
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c index 985248b0..b50cb2d1 100644 --- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c | |||
@@ -22,6 +22,9 @@ | |||
22 | #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> | 22 | #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> |
23 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | 23 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> |
24 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> | 24 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> |
25 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | ||
26 | |||
27 | #define VPR_INFO_FETCH_WAIT (5) | ||
25 | 28 | ||
26 | static void fb_gm20b_init_fs_state(struct gk20a *g) | 29 | static void fb_gm20b_init_fs_state(struct gk20a *g) |
27 | { | 30 | { |
@@ -140,15 +143,84 @@ static void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) | |||
140 | 143 | ||
141 | } | 144 | } |
142 | 145 | ||
146 | static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g, | ||
147 | unsigned int msec) | ||
148 | { | ||
149 | struct nvgpu_timeout timeout; | ||
150 | |||
151 | nvgpu_timeout_init(g, &timeout, msec, NVGPU_TIMER_CPU_TIMER); | ||
152 | |||
153 | do { | ||
154 | u32 val; | ||
155 | |||
156 | val = gk20a_readl(g, fb_mmu_vpr_info_r()); | ||
157 | if (fb_mmu_vpr_info_fetch_v(val) == | ||
158 | fb_mmu_vpr_info_fetch_false_v()) | ||
159 | return 0; | ||
160 | |||
161 | } while (!nvgpu_timeout_expired(&timeout)); | ||
162 | |||
163 | return -ETIMEDOUT; | ||
164 | } | ||
165 | |||
166 | int gm20b_fb_vpr_info_fetch(struct gk20a *g) | ||
167 | { | ||
168 | if (gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) { | ||
169 | return -ETIME; | ||
170 | } | ||
171 | |||
172 | gk20a_writel(g, fb_mmu_vpr_info_r(), | ||
173 | fb_mmu_vpr_info_fetch_true_v()); | ||
174 | |||
175 | return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); | ||
176 | } | ||
177 | |||
178 | static bool gm20b_fb_debug_mode_enabled(struct gk20a *g) | ||
179 | { | ||
180 | u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | ||
181 | return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) == | ||
182 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); | ||
183 | } | ||
184 | |||
185 | static void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | ||
186 | { | ||
187 | u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; | ||
188 | |||
189 | if (enable) { | ||
190 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
191 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); | ||
192 | g->mmu_debug_ctrl = true; | ||
193 | } else { | ||
194 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
195 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); | ||
196 | g->mmu_debug_ctrl = false; | ||
197 | } | ||
198 | |||
199 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
200 | reg_val = set_field(reg_val, | ||
201 | fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); | ||
202 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | ||
203 | |||
204 | reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | ||
205 | reg_val = set_field(reg_val, | ||
206 | gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); | ||
207 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); | ||
208 | } | ||
209 | |||
143 | void gm20b_init_fb(struct gpu_ops *gops) | 210 | void gm20b_init_fb(struct gpu_ops *gops) |
144 | { | 211 | { |
145 | gops->fb.reset = fb_gk20a_reset; | 212 | gops->fb.reset = fb_gk20a_reset; |
213 | gops->fb.init_hw = gk20a_fb_init_hw; | ||
146 | gops->fb.init_fs_state = fb_gm20b_init_fs_state; | 214 | gops->fb.init_fs_state = fb_gm20b_init_fs_state; |
147 | gops->fb.set_mmu_page_size = gm20b_fb_set_mmu_page_size; | 215 | gops->fb.set_mmu_page_size = gm20b_fb_set_mmu_page_size; |
148 | gops->fb.set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line; | 216 | gops->fb.set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line; |
149 | gops->fb.compression_page_size = gm20b_fb_compression_page_size; | 217 | gops->fb.compression_page_size = gm20b_fb_compression_page_size; |
150 | gops->fb.compressible_page_size = gm20b_fb_compressible_page_size; | 218 | gops->fb.compressible_page_size = gm20b_fb_compressible_page_size; |
219 | gops->fb.vpr_info_fetch = gm20b_fb_vpr_info_fetch; | ||
151 | gops->fb.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info; | 220 | gops->fb.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info; |
221 | gops->fb.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled; | ||
222 | gops->fb.set_debug_mode = gm20b_fb_set_debug_mode; | ||
223 | gops->fb.tlb_invalidate = gk20a_fb_tlb_invalidate; | ||
152 | gm20b_init_uncompressed_kind_map(); | 224 | gm20b_init_uncompressed_kind_map(); |
153 | gm20b_init_kind_attr(); | 225 | gm20b_init_kind_attr(); |
154 | } | 226 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c index cd1a106d..0b3192cc 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c | |||
@@ -22,75 +22,9 @@ | |||
22 | #include <nvgpu/timers.h> | 22 | #include <nvgpu/timers.h> |
23 | 23 | ||
24 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> | 24 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> |
25 | #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> | ||
26 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | ||
27 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | 25 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> |
28 | #include <nvgpu/hw/gm20b/hw_bus_gm20b.h> | 26 | #include <nvgpu/hw/gm20b/hw_bus_gm20b.h> |
29 | 27 | ||
30 | static int gm20b_mm_mmu_vpr_info_fetch_wait(struct gk20a *g, | ||
31 | unsigned int msec) | ||
32 | { | ||
33 | struct nvgpu_timeout timeout; | ||
34 | |||
35 | nvgpu_timeout_init(g, &timeout, msec, NVGPU_TIMER_CPU_TIMER); | ||
36 | |||
37 | do { | ||
38 | u32 val; | ||
39 | |||
40 | val = gk20a_readl(g, fb_mmu_vpr_info_r()); | ||
41 | if (fb_mmu_vpr_info_fetch_v(val) == | ||
42 | fb_mmu_vpr_info_fetch_false_v()) | ||
43 | return 0; | ||
44 | |||
45 | } while (!nvgpu_timeout_expired(&timeout)); | ||
46 | |||
47 | return -ETIMEDOUT; | ||
48 | } | ||
49 | |||
50 | int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g) | ||
51 | { | ||
52 | if (gm20b_mm_mmu_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) { | ||
53 | return -ETIME; | ||
54 | } | ||
55 | |||
56 | gk20a_writel(g, fb_mmu_vpr_info_r(), | ||
57 | fb_mmu_vpr_info_fetch_true_v()); | ||
58 | |||
59 | return gm20b_mm_mmu_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); | ||
60 | } | ||
61 | |||
62 | static bool gm20b_mm_mmu_debug_mode_enabled(struct gk20a *g) | ||
63 | { | ||
64 | u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | ||
65 | return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) == | ||
66 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); | ||
67 | } | ||
68 | |||
69 | static void gm20b_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) | ||
70 | { | ||
71 | u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; | ||
72 | |||
73 | if (enable) { | ||
74 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
75 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); | ||
76 | g->mmu_debug_ctrl = true; | ||
77 | } else { | ||
78 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
79 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); | ||
80 | g->mmu_debug_ctrl = false; | ||
81 | } | ||
82 | |||
83 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
84 | reg_val = set_field(reg_val, | ||
85 | fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); | ||
86 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | ||
87 | |||
88 | reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | ||
89 | reg_val = set_field(reg_val, | ||
90 | gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); | ||
91 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); | ||
92 | } | ||
93 | |||
94 | static void gm20b_mm_set_big_page_size(struct gk20a *g, | 28 | static void gm20b_mm_set_big_page_size(struct gk20a *g, |
95 | struct mem_desc *mem, int size) | 29 | struct mem_desc *mem, int size) |
96 | { | 30 | { |
@@ -157,8 +91,6 @@ static bool gm20b_mm_is_bar1_supported(struct gk20a *g) | |||
157 | void gm20b_init_mm(struct gpu_ops *gops) | 91 | void gm20b_init_mm(struct gpu_ops *gops) |
158 | { | 92 | { |
159 | gops->mm.support_sparse = gm20b_mm_support_sparse; | 93 | gops->mm.support_sparse = gm20b_mm_support_sparse; |
160 | gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled; | ||
161 | gops->mm.set_debug_mode = gm20b_mm_mmu_set_debug_mode; | ||
162 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; | 94 | gops->mm.gmmu_map = gk20a_locked_gmmu_map; |
163 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; | 95 | gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; |
164 | gops->mm.vm_remove = gk20a_vm_remove_support; | 96 | gops->mm.vm_remove = gk20a_vm_remove_support; |
@@ -168,7 +100,6 @@ void gm20b_init_mm(struct gpu_ops *gops) | |||
168 | gops->mm.l2_invalidate = gk20a_mm_l2_invalidate; | 100 | gops->mm.l2_invalidate = gk20a_mm_l2_invalidate; |
169 | gops->mm.l2_flush = gk20a_mm_l2_flush; | 101 | gops->mm.l2_flush = gk20a_mm_l2_flush; |
170 | gops->mm.cbc_clean = gk20a_mm_cbc_clean; | 102 | gops->mm.cbc_clean = gk20a_mm_cbc_clean; |
171 | gops->mm.tlb_invalidate = gk20a_mm_tlb_invalidate; | ||
172 | gops->mm.set_big_page_size = gm20b_mm_set_big_page_size; | 103 | gops->mm.set_big_page_size = gm20b_mm_set_big_page_size; |
173 | gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes; | 104 | gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes; |
174 | gops->mm.get_iova_addr = gk20a_mm_iova_addr; | 105 | gops->mm.get_iova_addr = gk20a_mm_iova_addr; |
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h index 6939fc1a..99d6c161 100644 --- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h | |||
@@ -19,7 +19,6 @@ struct gk20a; | |||
19 | 19 | ||
20 | #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) | 20 | #define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1)) |
21 | #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) | 21 | #define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1)) |
22 | #define VPR_INFO_FETCH_WAIT (5) | ||
23 | 22 | ||
24 | void gm20b_init_mm(struct gpu_ops *gops); | 23 | void gm20b_init_mm(struct gpu_ops *gops); |
25 | int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g); | 24 | int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 8c744a73..f5228136 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -394,8 +394,6 @@ static int gp106_prepare_ucode_blob(struct gk20a *g) | |||
394 | } | 394 | } |
395 | plsfm = &lsfm_l; | 395 | plsfm = &lsfm_l; |
396 | memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1)); | 396 | memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr_v1)); |
397 | gp106_dbg_pmu("fetching GMMU regs\n"); | ||
398 | gm20b_mm_mmu_vpr_info_fetch(g); | ||
399 | gr_gk20a_init_ctxsw_ucode(g); | 397 | gr_gk20a_init_ctxsw_ucode(g); |
400 | 398 | ||
401 | g->ops.pmu.get_wpr(g, &wpr_inf); | 399 | g->ops.pmu.get_wpr(g, &wpr_inf); |
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c index 10bbbccb..1bcdc17b 100644 --- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c | |||
@@ -498,11 +498,11 @@ static void vgpu_mm_l2_flush(struct gk20a *g, bool invalidate) | |||
498 | vgpu_cache_maint(vgpu_get_handle(g), op); | 498 | vgpu_cache_maint(vgpu_get_handle(g), op); |
499 | } | 499 | } |
500 | 500 | ||
501 | static void vgpu_mm_tlb_invalidate(struct vm_gk20a *vm) | 501 | static void vgpu_mm_tlb_invalidate(struct gk20a *g, struct mem_desc *pdb) |
502 | { | 502 | { |
503 | gk20a_dbg_fn(""); | 503 | gk20a_dbg_fn(""); |
504 | 504 | ||
505 | gk20a_err(dev_from_vm(vm), "%s: call to RM server not supported", | 505 | gk20a_err(g->dev, "%s: call to RM server not supported", |
506 | __func__); | 506 | __func__); |
507 | } | 507 | } |
508 | 508 | ||
@@ -523,8 +523,8 @@ static void vgpu_mm_mmu_set_debug_mode(struct gk20a *g, bool enable) | |||
523 | 523 | ||
524 | void vgpu_init_mm_ops(struct gpu_ops *gops) | 524 | void vgpu_init_mm_ops(struct gpu_ops *gops) |
525 | { | 525 | { |
526 | gops->mm.is_debug_mode_enabled = NULL; | 526 | gops->fb.is_debug_mode_enabled = NULL; |
527 | gops->mm.set_debug_mode = vgpu_mm_mmu_set_debug_mode; | 527 | gops->fb.set_debug_mode = vgpu_mm_mmu_set_debug_mode; |
528 | gops->mm.gmmu_map = vgpu_locked_gmmu_map; | 528 | gops->mm.gmmu_map = vgpu_locked_gmmu_map; |
529 | gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap; | 529 | gops->mm.gmmu_unmap = vgpu_locked_gmmu_unmap; |
530 | gops->mm.vm_remove = vgpu_vm_remove_support; | 530 | gops->mm.vm_remove = vgpu_vm_remove_support; |
@@ -533,7 +533,7 @@ void vgpu_init_mm_ops(struct gpu_ops *gops) | |||
533 | gops->mm.fb_flush = vgpu_mm_fb_flush; | 533 | gops->mm.fb_flush = vgpu_mm_fb_flush; |
534 | gops->mm.l2_invalidate = vgpu_mm_l2_invalidate; | 534 | gops->mm.l2_invalidate = vgpu_mm_l2_invalidate; |
535 | gops->mm.l2_flush = vgpu_mm_l2_flush; | 535 | gops->mm.l2_flush = vgpu_mm_l2_flush; |
536 | gops->mm.tlb_invalidate = vgpu_mm_tlb_invalidate; | 536 | gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate; |
537 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; | 537 | gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits; |
538 | gops->mm.get_iova_addr = gk20a_mm_iova_addr; | 538 | gops->mm.get_iova_addr = gk20a_mm_iova_addr; |
539 | gops->mm.init_mm_setup_hw = NULL; | 539 | gops->mm.init_mm_setup_hw = NULL; |