diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 5258e4ce..0158d706 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1334,6 +1334,87 @@ fail_free: | |||
1334 | return err; | 1334 | return err; |
1335 | } | 1335 | } |
1336 | 1336 | ||
1337 | static void gr_gv11b_dump_gr_per_sm_regs(struct gk20a *g, | ||
1338 | struct gk20a_debug_output *o, | ||
1339 | u32 gpc, u32 tpc, u32 sm, u32 offset) | ||
1340 | { | ||
1341 | |||
1342 | gk20a_debug_output(o, | ||
1343 | "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_WARP_ESR: 0x%x\n", | ||
1344 | gpc, tpc, sm, gk20a_readl(g, | ||
1345 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset)); | ||
1346 | |||
1347 | gk20a_debug_output(o, | ||
1348 | "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_WARP_ESR_REPORT_MASK: 0x%x\n", | ||
1349 | gpc, tpc, sm, gk20a_readl(g, | ||
1350 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset)); | ||
1351 | |||
1352 | gk20a_debug_output(o, | ||
1353 | "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_GLOBAL_ESR: 0x%x\n", | ||
1354 | gpc, tpc, sm, gk20a_readl(g, | ||
1355 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset)); | ||
1356 | |||
1357 | gk20a_debug_output(o, | ||
1358 | "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x\n", | ||
1359 | gpc, tpc, sm, gk20a_readl(g, | ||
1360 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset)); | ||
1361 | |||
1362 | gk20a_debug_output(o, | ||
1363 | "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_DBGR_CONTROL0: 0x%x\n", | ||
1364 | gpc, tpc, sm, gk20a_readl(g, | ||
1365 | gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset)); | ||
1366 | |||
1367 | gk20a_debug_output(o, | ||
1368 | "NV_PGRAPH_PRI_GPC%d_TPC%d_SM%d_DBGR_STATUS0: 0x%x\n", | ||
1369 | gpc, tpc, sm, gk20a_readl(g, | ||
1370 | gr_gpc0_tpc0_sm0_dbgr_status0_r() + offset)); | ||
1371 | } | ||
1372 | |||
1373 | static int gr_gv11b_dump_gr_sm_regs(struct gk20a *g, | ||
1374 | struct gk20a_debug_output *o) | ||
1375 | { | ||
1376 | u32 gpc, tpc, sm, sm_per_tpc; | ||
1377 | u32 gpc_offset, tpc_offset, offset; | ||
1378 | |||
1379 | gk20a_debug_output(o, | ||
1380 | "NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR_REPORT_MASK: 0x%x\n", | ||
1381 | gk20a_readl(g, | ||
1382 | gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r())); | ||
1383 | gk20a_debug_output(o, | ||
1384 | "NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_WARP_ESR_REPORT_MASK: 0x%x\n", | ||
1385 | gk20a_readl(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r())); | ||
1386 | gk20a_debug_output(o, | ||
1387 | "NV_PGRAPH_PRI_GPCS_TPCS_SMS_HWW_GLOBAL_ESR: 0x%x\n", | ||
1388 | gk20a_readl(g, gr_gpcs_tpcs_sms_hww_global_esr_r())); | ||
1389 | gk20a_debug_output(o, | ||
1390 | "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_CONTROL0: 0x%x\n", | ||
1391 | gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_control0_r())); | ||
1392 | gk20a_debug_output(o, | ||
1393 | "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_STATUS0: 0x%x\n", | ||
1394 | gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_status0_r())); | ||
1395 | gk20a_debug_output(o, | ||
1396 | "NV_PGRAPH_PRI_GPCS_TPCS_SMS_DBGR_BPT_PAUSE_MASK: 0x%x\n", | ||
1397 | gk20a_readl(g, gr_gpcs_tpcs_sms_dbgr_bpt_pause_mask_r())); | ||
1398 | |||
1399 | sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); | ||
1400 | for (gpc = 0; gpc < g->gr.gpc_count; gpc++) { | ||
1401 | gpc_offset = gk20a_gr_gpc_offset(g, gpc); | ||
1402 | |||
1403 | for (tpc = 0; tpc < g->gr.tpc_count; tpc++) { | ||
1404 | tpc_offset = gk20a_gr_tpc_offset(g, tpc); | ||
1405 | |||
1406 | for (sm = 0; sm < sm_per_tpc; sm++) { | ||
1407 | offset = gpc_offset + tpc_offset + | ||
1408 | gv11b_gr_sm_offset(g, sm); | ||
1409 | |||
1410 | gr_gv11b_dump_gr_per_sm_regs(g, o, | ||
1411 | gpc, tpc, sm, offset); | ||
1412 | } | ||
1413 | } | ||
1414 | } | ||
1415 | |||
1416 | return 0; | ||
1417 | } | ||
1337 | 1418 | ||
1338 | static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | 1419 | static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, |
1339 | struct gk20a_debug_output *o) | 1420 | struct gk20a_debug_output *o) |
@@ -1441,6 +1522,10 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | |||
1441 | gk20a_readl(g, gr_fecs_current_ctx_r())); | 1522 | gk20a_readl(g, gr_fecs_current_ctx_r())); |
1442 | gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n", | 1523 | gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_NEW_CTX : 0x%x\n", |
1443 | gk20a_readl(g, gr_fecs_new_ctx_r())); | 1524 | gk20a_readl(g, gr_fecs_new_ctx_r())); |
1525 | gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_ENABLE : 0x%x\n", | ||
1526 | gk20a_readl(g, gr_fecs_host_int_enable_r())); | ||
1527 | gk20a_debug_output(o, "NV_PGRAPH_PRI_FECS_HOST_INT_STATUS : 0x%x\n", | ||
1528 | gk20a_readl(g, gr_fecs_host_int_status_r())); | ||
1444 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n", | 1529 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_CROP_STATUS1 : 0x%x\n", |
1445 | gk20a_readl(g, gr_pri_be0_crop_status1_r())); | 1530 | gk20a_readl(g, gr_pri_be0_crop_status1_r())); |
1446 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_CROP_STATUS1 : 0x%x\n", | 1531 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BES_CROP_STATUS1 : 0x%x\n", |
@@ -1465,6 +1550,9 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | |||
1465 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r())); | 1550 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_r())); |
1466 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n", | 1551 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_EXCEPTION_EN: 0x%x\n", |
1467 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r())); | 1552 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_exception_en_r())); |
1553 | |||
1554 | gr_gv11b_dump_gr_sm_regs(g, o); | ||
1555 | |||
1468 | return 0; | 1556 | return 0; |
1469 | } | 1557 | } |
1470 | 1558 | ||