diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/hw_proj_gm206.h | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 9 |
6 files changed, 75 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a263743f..dd64e3b2 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -119,6 +119,8 @@ enum gk20a_cbc_op { | |||
119 | #define GPU_LIT_LTS_STRIDE 21 | 119 | #define GPU_LIT_LTS_STRIDE 21 |
120 | #define GPU_LIT_NUM_FBPAS 22 | 120 | #define GPU_LIT_NUM_FBPAS 22 |
121 | #define GPU_LIT_FBPA_STRIDE 23 | 121 | #define GPU_LIT_FBPA_STRIDE 23 |
122 | #define GPU_LIT_FBPA_BASE 24 | ||
123 | #define GPU_LIT_FBPA_SHARED_BASE 25 | ||
122 | 124 | ||
123 | #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) | 125 | #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v) |
124 | 126 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index ee8b3b63..f5205d75 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -6567,6 +6567,13 @@ static int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr, | |||
6567 | else if (g->ops.gr.is_ltcn_ltss_addr(g, addr)) | 6567 | else if (g->ops.gr.is_ltcn_ltss_addr(g, addr)) |
6568 | *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS; | 6568 | *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS; |
6569 | return 0; | 6569 | return 0; |
6570 | } else if (pri_is_fbpa_addr(g, addr)) { | ||
6571 | *addr_type = CTXSW_ADDR_TYPE_FBPA; | ||
6572 | if (pri_is_fbpa_addr_shared(g, addr)) { | ||
6573 | *broadcast_flags |= PRI_BROADCAST_FLAGS_FBPA; | ||
6574 | return 0; | ||
6575 | } | ||
6576 | return 0; | ||
6570 | } else { | 6577 | } else { |
6571 | *addr_type = CTXSW_ADDR_TYPE_SYS; | 6578 | *addr_type = CTXSW_ADDR_TYPE_SYS; |
6572 | return 0; | 6579 | return 0; |
@@ -6609,6 +6616,7 @@ static int gr_gk20a_create_priv_addr_table(struct gk20a *g, | |||
6609 | u32 broadcast_flags; | 6616 | u32 broadcast_flags; |
6610 | u32 t; | 6617 | u32 t; |
6611 | int err; | 6618 | int err; |
6619 | u32 fbpa_num; | ||
6612 | 6620 | ||
6613 | t = 0; | 6621 | t = 0; |
6614 | *num_registers = 0; | 6622 | *num_registers = 0; |
@@ -6669,6 +6677,12 @@ static int gr_gk20a_create_priv_addr_table(struct gk20a *g, | |||
6669 | } else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTCS) { | 6677 | } else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTCS) { |
6670 | g->ops.gr.split_ltc_broadcast_addr(g, addr, | 6678 | g->ops.gr.split_ltc_broadcast_addr(g, addr, |
6671 | priv_addr_table, &t); | 6679 | priv_addr_table, &t); |
6680 | } else if (broadcast_flags & PRI_BROADCAST_FLAGS_FBPA) { | ||
6681 | for (fbpa_num = 0; | ||
6682 | fbpa_num < nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS); | ||
6683 | fbpa_num++) | ||
6684 | priv_addr_table[t++] = pri_fbpa_addr(g, | ||
6685 | pri_fbpa_addr_mask(g, addr), fbpa_num); | ||
6672 | } else if (!(broadcast_flags & PRI_BROADCAST_FLAGS_GPC)) { | 6686 | } else if (!(broadcast_flags & PRI_BROADCAST_FLAGS_GPC)) { |
6673 | if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC) | 6687 | if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC) |
6674 | for (tpc_num = 0; | 6688 | for (tpc_num = 0; |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h index 411430c7..c3ced432 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h | |||
@@ -109,6 +109,10 @@ static inline u32 pri_tpccs_addr_mask(u32 addr) | |||
109 | { | 109 | { |
110 | return addr & ((1 << pri_tpccs_addr_width()) - 1); | 110 | return addr & ((1 << pri_tpccs_addr_width()) - 1); |
111 | } | 111 | } |
112 | static inline u32 pri_fbpa_addr_mask(struct gk20a *g, u32 addr) | ||
113 | { | ||
114 | return addr & (nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE) - 1); | ||
115 | } | ||
112 | static inline u32 pri_tpc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 tpc) | 116 | static inline u32 pri_tpc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 tpc) |
113 | { | 117 | { |
114 | u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE); | 118 | u32 gpc_base = nvgpu_get_litter_value(g, GPU_LIT_GPC_BASE); |
@@ -127,7 +131,27 @@ static inline bool pri_is_tpc_addr_shared(struct gk20a *g, u32 addr) | |||
127 | (addr < (tpc_in_gpc_shared_base + | 131 | (addr < (tpc_in_gpc_shared_base + |
128 | tpc_in_gpc_stride)); | 132 | tpc_in_gpc_stride)); |
129 | } | 133 | } |
130 | 134 | static inline u32 pri_fbpa_addr(struct gk20a *g, u32 addr, u32 fbpa) | |
135 | { | ||
136 | return (nvgpu_get_litter_value(g, GPU_LIT_FBPA_BASE) + addr + | ||
137 | (fbpa * nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE))); | ||
138 | } | ||
139 | static inline bool pri_is_fbpa_addr_shared(struct gk20a *g, u32 addr) | ||
140 | { | ||
141 | u32 fbpa_shared_base = nvgpu_get_litter_value(g, GPU_LIT_FBPA_SHARED_BASE); | ||
142 | u32 fbpa_stride = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE); | ||
143 | return ((addr >= fbpa_shared_base) && | ||
144 | (addr < (fbpa_shared_base + fbpa_stride))); | ||
145 | } | ||
146 | static inline bool pri_is_fbpa_addr(struct gk20a *g, u32 addr) | ||
147 | { | ||
148 | u32 fbpa_base = nvgpu_get_litter_value(g, GPU_LIT_FBPA_BASE); | ||
149 | u32 fbpa_stride = nvgpu_get_litter_value(g, GPU_LIT_FBPA_STRIDE); | ||
150 | u32 num_fbpas = nvgpu_get_litter_value(g, GPU_LIT_NUM_FBPAS); | ||
151 | return (((addr >= fbpa_base) && | ||
152 | (addr < (fbpa_base + num_fbpas * fbpa_stride))) | ||
153 | || pri_is_fbpa_addr_shared(g, addr)); | ||
154 | } | ||
131 | /* | 155 | /* |
132 | * BE pri addressing | 156 | * BE pri addressing |
133 | */ | 157 | */ |
@@ -209,7 +233,8 @@ enum ctxsw_addr_type { | |||
209 | CTXSW_ADDR_TYPE_TPC = 2, | 233 | CTXSW_ADDR_TYPE_TPC = 2, |
210 | CTXSW_ADDR_TYPE_BE = 3, | 234 | CTXSW_ADDR_TYPE_BE = 3, |
211 | CTXSW_ADDR_TYPE_PPC = 4, | 235 | CTXSW_ADDR_TYPE_PPC = 4, |
212 | CTXSW_ADDR_TYPE_LTCS = 5 | 236 | CTXSW_ADDR_TYPE_LTCS = 5, |
237 | CTXSW_ADDR_TYPE_FBPA = 6, | ||
213 | }; | 238 | }; |
214 | 239 | ||
215 | #define PRI_BROADCAST_FLAGS_NONE 0 | 240 | #define PRI_BROADCAST_FLAGS_NONE 0 |
@@ -219,5 +244,6 @@ enum ctxsw_addr_type { | |||
219 | #define PRI_BROADCAST_FLAGS_PPC BIT(3) | 244 | #define PRI_BROADCAST_FLAGS_PPC BIT(3) |
220 | #define PRI_BROADCAST_FLAGS_LTCS BIT(4) | 245 | #define PRI_BROADCAST_FLAGS_LTCS BIT(4) |
221 | #define PRI_BROADCAST_FLAGS_LTSS BIT(5) | 246 | #define PRI_BROADCAST_FLAGS_LTSS BIT(5) |
247 | #define PRI_BROADCAST_FLAGS_FBPA BIT(6) | ||
222 | 248 | ||
223 | #endif /* GR_PRI_GK20A_H */ | 249 | #endif /* GR_PRI_GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 341c2e72..5b2b2552 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c | |||
@@ -34,6 +34,9 @@ | |||
34 | #include "dbg_gpu_gk20a.h" | 34 | #include "dbg_gpu_gk20a.h" |
35 | #include "css_gr_gk20a.h" | 35 | #include "css_gr_gk20a.h" |
36 | 36 | ||
37 | #define GK20A_FBPA_BASE 0x00110000 | ||
38 | #define GK20A_FBPA_SHARED_BASE 0x0010F000 | ||
39 | |||
37 | static struct gpu_ops gk20a_ops = { | 40 | static struct gpu_ops gk20a_ops = { |
38 | .clock_gating = { | 41 | .clock_gating = { |
39 | .slcg_gr_load_gating_prod = | 42 | .slcg_gr_load_gating_prod = |
@@ -124,6 +127,12 @@ static int gk20a_get_litter_value(struct gk20a *g, int value) | |||
124 | case GPU_LIT_FBPA_STRIDE: | 127 | case GPU_LIT_FBPA_STRIDE: |
125 | ret = proj_fbpa_stride_v(); | 128 | ret = proj_fbpa_stride_v(); |
126 | break; | 129 | break; |
130 | case GPU_LIT_FBPA_BASE: | ||
131 | ret = GK20A_FBPA_BASE; | ||
132 | break; | ||
133 | case GPU_LIT_FBPA_SHARED_BASE: | ||
134 | ret = GK20A_FBPA_SHARED_BASE; | ||
135 | break; | ||
127 | default: | 136 | default: |
128 | gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); | 137 | gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); |
129 | BUG(); | 138 | BUG(); |
diff --git a/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h b/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h index 6c21b39a..bdca905f 100644 --- a/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h +++ b/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h | |||
@@ -70,14 +70,26 @@ static inline u32 proj_lts_stride_v(void) | |||
70 | { | 70 | { |
71 | return 0x00000200; | 71 | return 0x00000200; |
72 | } | 72 | } |
73 | static inline u32 proj_fbpa_base_v(void) | ||
74 | { | ||
75 | return 0x00110000; | ||
76 | } | ||
77 | static inline u32 proj_fbpa_shared_base_v(void) | ||
78 | { | ||
79 | return 0x0010f000; | ||
80 | } | ||
73 | static inline u32 proj_fbpa_stride_v(void) | 81 | static inline u32 proj_fbpa_stride_v(void) |
74 | { | 82 | { |
75 | return 0x00004000; | 83 | return 0x00001000; |
76 | } | 84 | } |
77 | static inline u32 proj_ppc_in_gpc_base_v(void) | 85 | static inline u32 proj_ppc_in_gpc_base_v(void) |
78 | { | 86 | { |
79 | return 0x00003000; | 87 | return 0x00003000; |
80 | } | 88 | } |
89 | static inline u32 proj_ppc_in_gpc_shared_base_v(void) | ||
90 | { | ||
91 | return 0x00003e00; | ||
92 | } | ||
81 | static inline u32 proj_ppc_in_gpc_stride_v(void) | 93 | static inline u32 proj_ppc_in_gpc_stride_v(void) |
82 | { | 94 | { |
83 | return 0x00000200; | 95 | return 0x00000200; |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 35747f27..71ffe288 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -45,6 +45,9 @@ | |||
45 | 45 | ||
46 | #define PRIV_SECURITY_DISABLE 0x01 | 46 | #define PRIV_SECURITY_DISABLE 0x01 |
47 | 47 | ||
48 | #define GM20B_FBPA_BASE 0x00110000 | ||
49 | #define GM20B_FBPA_SHARED_BASE 0x0010F000 | ||
50 | |||
48 | static struct gpu_ops gm20b_ops = { | 51 | static struct gpu_ops gm20b_ops = { |
49 | .clock_gating = { | 52 | .clock_gating = { |
50 | .slcg_bus_load_gating_prod = | 53 | .slcg_bus_load_gating_prod = |
@@ -169,6 +172,12 @@ static int gm20b_get_litter_value(struct gk20a *g, int value) | |||
169 | case GPU_LIT_FBPA_STRIDE: | 172 | case GPU_LIT_FBPA_STRIDE: |
170 | ret = proj_fbpa_stride_v(); | 173 | ret = proj_fbpa_stride_v(); |
171 | break; | 174 | break; |
175 | case GPU_LIT_FBPA_BASE: | ||
176 | ret = GM20B_FBPA_BASE; | ||
177 | break; | ||
178 | case GPU_LIT_FBPA_SHARED_BASE: | ||
179 | ret = GM20B_FBPA_SHARED_BASE; | ||
180 | break; | ||
172 | default: | 181 | default: |
173 | gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); | 182 | gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); |
174 | BUG(); | 183 | BUG(); |