diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 14 |
5 files changed, 35 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ee78c6e2..273eeaf4 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -456,6 +456,7 @@ struct gpu_ops { | |||
456 | u8 grfeaturemask); | 456 | u8 grfeaturemask); |
457 | int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) | 457 | int (*send_lrf_tex_ltc_dram_overide_en_dis_cmd) |
458 | (struct gk20a *g, u32 mask); | 458 | (struct gk20a *g, u32 mask); |
459 | void (*dump_secure_fuses)(struct gk20a *g); | ||
459 | u32 lspmuwprinitdone; | 460 | u32 lspmuwprinitdone; |
460 | u32 lsfloadedfalconid; | 461 | u32 lsfloadedfalconid; |
461 | bool fecsbootstrapdone; | 462 | bool fecsbootstrapdone; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 60c87979..4edfe90c 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2772,6 +2772,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
2772 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; | 2772 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; |
2773 | gops->pmu.pmu_pg_grinit_param = NULL; | 2773 | gops->pmu.pmu_pg_grinit_param = NULL; |
2774 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | 2774 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; |
2775 | gops->pmu.dump_secure_fuses = NULL; | ||
2775 | } | 2776 | } |
2776 | 2777 | ||
2777 | int gk20a_init_pmu_support(struct gk20a *g) | 2778 | int gk20a_init_pmu_support(struct gk20a *g) |
@@ -3730,6 +3731,11 @@ void gk20a_pmu_isr(struct gk20a *g) | |||
3730 | gk20a_err(dev_from_gk20a(g), | 3731 | gk20a_err(dev_from_gk20a(g), |
3731 | "pmu halt intr not implemented"); | 3732 | "pmu halt intr not implemented"); |
3732 | pmu_dump_falcon_stats(pmu); | 3733 | pmu_dump_falcon_stats(pmu); |
3734 | if (gk20a_readl(g, pwr_pmu_mailbox_r | ||
3735 | (PMU_MODE_MISMATCH_STATUS_MAILBOX_R)) == | ||
3736 | PMU_MODE_MISMATCH_STATUS_VAL) | ||
3737 | if (g->ops.pmu.dump_secure_fuses) | ||
3738 | g->ops.pmu.dump_secure_fuses(g); | ||
3733 | } | 3739 | } |
3734 | if (intr & pwr_falcon_irqstat_exterr_true_f()) { | 3740 | if (intr & pwr_falcon_irqstat_exterr_true_f()) { |
3735 | gk20a_err(dev_from_gk20a(g), | 3741 | gk20a_err(dev_from_gk20a(g), |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 54d01947..c533ba8d 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -60,6 +60,11 @@ | |||
60 | #define APP_VERSION_1 17997577 | 60 | #define APP_VERSION_1 17997577 |
61 | #define APP_VERSION_0 16856675 | 61 | #define APP_VERSION_0 16856675 |
62 | 62 | ||
63 | /*Fuse defines*/ | ||
64 | #define FUSE_GCPLEX_CONFIG_FUSE_0 0x2C8 | ||
65 | #define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6 | ||
66 | #define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD | ||
67 | |||
63 | 68 | ||
64 | enum pmu_perfmon_cmd_start_fields { | 69 | enum pmu_perfmon_cmd_start_fields { |
65 | COUNTER_ALLOC | 70 | COUNTER_ALLOC |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h index a36709e3..62f68378 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_fuse_gm20b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -126,4 +126,12 @@ static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) | |||
126 | { | 126 | { |
127 | return (r >> (0 + i*0)) & 0x1; | 127 | return (r >> (0 + i*0)) & 0x1; |
128 | } | 128 | } |
129 | static inline u32 fuse_opt_sec_debug_en_r(void) | ||
130 | { | ||
131 | return 0x00021218; | ||
132 | } | ||
133 | static inline u32 fuse_opt_priv_sec_en_r(void) | ||
134 | { | ||
135 | return 0x00021434; | ||
136 | } | ||
129 | #endif | 137 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index ce3da2b6..34d1c30c 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -14,12 +14,14 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/delay.h> /* for udelay */ | 16 | #include <linux/delay.h> /* for udelay */ |
17 | #include <linux/tegra-fuse.h> | ||
17 | #include "gk20a/gk20a.h" | 18 | #include "gk20a/gk20a.h" |
18 | #include "gk20a/pmu_gk20a.h" | 19 | #include "gk20a/pmu_gk20a.h" |
19 | #include "acr_gm20b.h" | 20 | #include "acr_gm20b.h" |
20 | #include "pmu_gm20b.h" | 21 | #include "pmu_gm20b.h" |
21 | #include "hw_gr_gm20b.h" | 22 | #include "hw_gr_gm20b.h" |
22 | #include "hw_pwr_gm20b.h" | 23 | #include "hw_pwr_gm20b.h" |
24 | #include "hw_fuse_gm20b.h" | ||
23 | 25 | ||
24 | /*! | 26 | /*! |
25 | * Structure/object which single register write need to be done during PG init | 27 | * Structure/object which single register write need to be done during PG init |
@@ -289,6 +291,17 @@ static void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr) | |||
289 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); | 291 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); |
290 | } | 292 | } |
291 | 293 | ||
294 | /*Dump Security related fuses*/ | ||
295 | static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | ||
296 | { | ||
297 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | ||
298 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | ||
299 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | ||
300 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | ||
301 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | ||
302 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0)); | ||
303 | } | ||
304 | |||
292 | void gm20b_init_pmu_ops(struct gpu_ops *gops) | 305 | void gm20b_init_pmu_ops(struct gpu_ops *gops) |
293 | { | 306 | { |
294 | if (gops->privsecurity) { | 307 | if (gops->privsecurity) { |
@@ -309,4 +322,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) | |||
309 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; | 322 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; |
310 | gops->pmu.pmu_pg_grinit_param = NULL; | 323 | gops->pmu.pmu_pg_grinit_param = NULL; |
311 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | 324 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; |
325 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b; | ||
312 | } | 326 | } |