diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 56 |
1 files changed, 2 insertions, 54 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 84faa252..1b7dd405 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -163,28 +163,9 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g, | |||
163 | static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | 163 | static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, |
164 | struct zbc_entry *color_val, u32 index) | 164 | struct zbc_entry *color_val, u32 index) |
165 | { | 165 | { |
166 | struct fifo_gk20a *f = &g->fifo; | ||
167 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
168 | u32 i; | 166 | u32 i; |
169 | unsigned long end_jiffies = jiffies + | ||
170 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
171 | u32 ret; | ||
172 | u32 zbc_c; | 167 | u32 zbc_c; |
173 | 168 | ||
174 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
175 | if (ret) { | ||
176 | gk20a_err(dev_from_gk20a(g), | ||
177 | "failed to disable gr engine activity\n"); | ||
178 | return ret; | ||
179 | } | ||
180 | |||
181 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
182 | if (ret) { | ||
183 | gk20a_err(dev_from_gk20a(g), | ||
184 | "failed to idle graphics\n"); | ||
185 | goto clean_up; | ||
186 | } | ||
187 | |||
188 | /* update l2 table */ | 169 | /* update l2 table */ |
189 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); | 170 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); |
190 | 171 | ||
@@ -226,40 +207,14 @@ static int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | |||
226 | zbc_c |= color_val->format << (index % 4) * 6; | 207 | zbc_c |= color_val->format << (index % 4) * 6; |
227 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4), zbc_c); | 208 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + ALIGN(index, 4), zbc_c); |
228 | 209 | ||
229 | clean_up: | 210 | return 0; |
230 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
231 | if (ret) { | ||
232 | gk20a_err(dev_from_gk20a(g), | ||
233 | "failed to enable gr engine activity\n"); | ||
234 | } | ||
235 | |||
236 | return ret; | ||
237 | } | 211 | } |
238 | 212 | ||
239 | static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | 213 | static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, |
240 | struct zbc_entry *depth_val, u32 index) | 214 | struct zbc_entry *depth_val, u32 index) |
241 | { | 215 | { |
242 | struct fifo_gk20a *f = &g->fifo; | ||
243 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
244 | unsigned long end_jiffies = jiffies + | ||
245 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
246 | u32 ret; | ||
247 | u32 zbc_z; | 216 | u32 zbc_z; |
248 | 217 | ||
249 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
250 | if (ret) { | ||
251 | gk20a_err(dev_from_gk20a(g), | ||
252 | "failed to disable gr engine activity\n"); | ||
253 | return ret; | ||
254 | } | ||
255 | |||
256 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
257 | if (ret) { | ||
258 | gk20a_err(dev_from_gk20a(g), | ||
259 | "failed to idle graphics\n"); | ||
260 | goto clean_up; | ||
261 | } | ||
262 | |||
263 | /* update l2 table */ | 218 | /* update l2 table */ |
264 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); | 219 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); |
265 | 220 | ||
@@ -289,14 +244,7 @@ static int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | |||
289 | zbc_z |= depth_val->format << (index % 4) * 6; | 244 | zbc_z |= depth_val->format << (index % 4) * 6; |
290 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4), zbc_z); | 245 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + ALIGN(index, 4), zbc_z); |
291 | 246 | ||
292 | clean_up: | 247 | return 0; |
293 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
294 | if (ret) { | ||
295 | gk20a_err(dev_from_gk20a(g), | ||
296 | "failed to enable gr engine activity\n"); | ||
297 | } | ||
298 | |||
299 | return ret; | ||
300 | } | 248 | } |
301 | 249 | ||
302 | static u32 gr_gp10b_pagepool_default_size(struct gk20a *g) | 250 | static u32 gr_gp10b_pagepool_default_size(struct gk20a *g) |