diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | 1 |
4 files changed, 18 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 050423b0..63a32f03 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -760,6 +760,10 @@ void gk20a_pmu_init_perfmon_counter(struct gk20a *g) | |||
760 | pwr_pmu_idle_mask_gr_enabled_f() | | 760 | pwr_pmu_idle_mask_gr_enabled_f() | |
761 | pwr_pmu_idle_mask_ce_2_enabled_f()); | 761 | pwr_pmu_idle_mask_ce_2_enabled_f()); |
762 | 762 | ||
763 | /* assign same mask setting from GR ELPG to counter #3 */ | ||
764 | data = gk20a_readl(g, pwr_pmu_idle_mask_1_supp_r(0)); | ||
765 | gk20a_writel(g, pwr_pmu_idle_mask_1_r(3), data); | ||
766 | |||
763 | /* disable idle filtering for counters 3 and 6 */ | 767 | /* disable idle filtering for counters 3 and 6 */ |
764 | data = gk20a_readl(g, pwr_pmu_idle_ctrl_r(3)); | 768 | data = gk20a_readl(g, pwr_pmu_idle_ctrl_r(3)); |
765 | data = set_field(data, pwr_pmu_idle_ctrl_value_m() | | 769 | data = set_field(data, pwr_pmu_idle_ctrl_value_m() | |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 2f7b4abc..a2384fc8 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -720,7 +720,7 @@ static const struct gpu_ops gv11b_ops = { | |||
720 | .pmu_mutex_release = gk20a_pmu_mutex_release, | 720 | .pmu_mutex_release = gk20a_pmu_mutex_release, |
721 | .pmu_is_interrupted = gk20a_pmu_is_interrupted, | 721 | .pmu_is_interrupted = gk20a_pmu_is_interrupted, |
722 | .pmu_isr = gk20a_pmu_isr, | 722 | .pmu_isr = gk20a_pmu_isr, |
723 | .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, | 723 | .pmu_init_perfmon_counter = gv11b_pmu_init_perfmon_counter, |
724 | .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, | 724 | .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, |
725 | .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, | 725 | .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, |
726 | .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, | 726 | .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, |
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c index 1001ba16..5e586ec2 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.c | |||
@@ -30,6 +30,7 @@ | |||
30 | #include <nvgpu/utils.h> | 30 | #include <nvgpu/utils.h> |
31 | #include <nvgpu/gk20a.h> | 31 | #include <nvgpu/gk20a.h> |
32 | 32 | ||
33 | #include "gk20a/pmu_gk20a.h" | ||
33 | #include "gp10b/pmu_gp10b.h" | 34 | #include "gp10b/pmu_gp10b.h" |
34 | #include "gp106/pmu_gp106.h" | 35 | #include "gp106/pmu_gp106.h" |
35 | 36 | ||
@@ -440,6 +441,17 @@ static void pmu_handle_pg_param_msg(struct gk20a *g, struct pmu_msg *msg, | |||
440 | msg->msg.pg.msg_type); | 441 | msg->msg.pg.msg_type); |
441 | } | 442 | } |
442 | 443 | ||
444 | void gv11b_pmu_init_perfmon_counter(struct gk20a *g) | ||
445 | { | ||
446 | u32 data; | ||
447 | |||
448 | gk20a_pmu_init_perfmon_counter(g); | ||
449 | |||
450 | /* assign same mask setting from GR ELPG to counter #3 */ | ||
451 | data = gk20a_readl(g, pwr_pmu_idle_mask_2_supp_r(0)); | ||
452 | gk20a_writel(g, pwr_pmu_idle_mask_2_r(3), data); | ||
453 | } | ||
454 | |||
443 | int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | 455 | int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) |
444 | { | 456 | { |
445 | struct nvgpu_pmu *pmu = &g->pmu; | 457 | struct nvgpu_pmu *pmu = &g->pmu; |
diff --git a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h index 9cb6b222..06efa8f6 100644 --- a/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/pmu_gv11b.h | |||
@@ -29,6 +29,7 @@ struct gk20a; | |||
29 | 29 | ||
30 | bool gv11b_is_pmu_supported(struct gk20a *g); | 30 | bool gv11b_is_pmu_supported(struct gk20a *g); |
31 | int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu); | 31 | int gv11b_pmu_bootstrap(struct nvgpu_pmu *pmu); |
32 | void gv11b_pmu_init_perfmon_counter(struct gk20a *g); | ||
32 | int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); | 33 | int gv11b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); |
33 | int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); | 34 | int gv11b_pg_set_subfeature_mask(struct gk20a *g, u32 pg_engine_id); |
34 | bool gv11b_is_lazy_bootstrap(u32 falcon_id); | 35 | bool gv11b_is_lazy_bootstrap(u32 falcon_id); |