diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fb_gm20b.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 9 |
8 files changed, 47 insertions, 62 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 181e5301..386b266d 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -134,7 +134,7 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
134 | gm20b_dbg_pmu("requesting PMU ucode in GM20B\n"); | 134 | gm20b_dbg_pmu("requesting PMU ucode in GM20B\n"); |
135 | pmu_fw = nvgpu_request_firmware(g, GM20B_PMU_UCODE_IMAGE, 0); | 135 | pmu_fw = nvgpu_request_firmware(g, GM20B_PMU_UCODE_IMAGE, 0); |
136 | if (!pmu_fw) { | 136 | if (!pmu_fw) { |
137 | gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode!!"); | 137 | nvgpu_err(g, "failed to load pmu ucode!!"); |
138 | return -ENOENT; | 138 | return -ENOENT; |
139 | } | 139 | } |
140 | g->acr.pmu_fw = pmu_fw; | 140 | g->acr.pmu_fw = pmu_fw; |
@@ -143,13 +143,13 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
143 | gm20b_dbg_pmu("requesting PMU ucode desc in GM20B\n"); | 143 | gm20b_dbg_pmu("requesting PMU ucode desc in GM20B\n"); |
144 | pmu_desc = nvgpu_request_firmware(g, GM20B_PMU_UCODE_DESC, 0); | 144 | pmu_desc = nvgpu_request_firmware(g, GM20B_PMU_UCODE_DESC, 0); |
145 | if (!pmu_desc) { | 145 | if (!pmu_desc) { |
146 | gk20a_err(dev_from_gk20a(g), "failed to load pmu ucode desc!!"); | 146 | nvgpu_err(g, "failed to load pmu ucode desc!!"); |
147 | err = -ENOENT; | 147 | err = -ENOENT; |
148 | goto release_img_fw; | 148 | goto release_img_fw; |
149 | } | 149 | } |
150 | pmu_sig = nvgpu_request_firmware(g, GM20B_PMU_UCODE_SIG, 0); | 150 | pmu_sig = nvgpu_request_firmware(g, GM20B_PMU_UCODE_SIG, 0); |
151 | if (!pmu_sig) { | 151 | if (!pmu_sig) { |
152 | gk20a_err(dev_from_gk20a(g), "failed to load pmu sig!!"); | 152 | nvgpu_err(g, "failed to load pmu sig!!"); |
153 | err = -ENOENT; | 153 | err = -ENOENT; |
154 | goto release_desc; | 154 | goto release_desc; |
155 | } | 155 | } |
@@ -197,7 +197,7 @@ static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
197 | 197 | ||
198 | fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, 0); | 198 | fecs_sig = nvgpu_request_firmware(g, GM20B_FECS_UCODE_SIG, 0); |
199 | if (!fecs_sig) { | 199 | if (!fecs_sig) { |
200 | gk20a_err(dev_from_gk20a(g), "failed to load fecs sig"); | 200 | nvgpu_err(g, "failed to load fecs sig"); |
201 | return -ENOENT; | 201 | return -ENOENT; |
202 | } | 202 | } |
203 | lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc)); | 203 | lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc)); |
@@ -267,7 +267,7 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
267 | 267 | ||
268 | gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0); | 268 | gpccs_sig = nvgpu_request_firmware(g, T18x_GPCCS_UCODE_SIG, 0); |
269 | if (!gpccs_sig) { | 269 | if (!gpccs_sig) { |
270 | gk20a_err(dev_from_gk20a(g), "failed to load gpccs sig"); | 270 | nvgpu_err(g, "failed to load gpccs sig"); |
271 | return -ENOENT; | 271 | return -ENOENT; |
272 | } | 272 | } |
273 | lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc)); | 273 | lsf_desc = nvgpu_kzalloc(g, sizeof(struct lsf_ucode_desc)); |
@@ -412,12 +412,12 @@ int prepare_ucode_blob(struct gk20a *g) | |||
412 | 412 | ||
413 | sgt = nvgpu_kzalloc(g, sizeof(*sgt)); | 413 | sgt = nvgpu_kzalloc(g, sizeof(*sgt)); |
414 | if (!sgt) { | 414 | if (!sgt) { |
415 | gk20a_err(dev_from_gk20a(g), "failed to allocate memory\n"); | 415 | nvgpu_err(g, "failed to allocate memory"); |
416 | return -ENOMEM; | 416 | return -ENOMEM; |
417 | } | 417 | } |
418 | err = sg_alloc_table(sgt, 1, GFP_KERNEL); | 418 | err = sg_alloc_table(sgt, 1, GFP_KERNEL); |
419 | if (err) { | 419 | if (err) { |
420 | gk20a_err(dev_from_gk20a(g), "failed to allocate sg_table\n"); | 420 | nvgpu_err(g, "failed to allocate sg_table"); |
421 | goto free_sgt; | 421 | goto free_sgt; |
422 | } | 422 | } |
423 | page = phys_to_page(wpr_addr); | 423 | page = phys_to_page(wpr_addr); |
@@ -1088,7 +1088,7 @@ static int gm20b_bootstrap_hs_flcn(struct gk20a *g) | |||
1088 | /*First time init case*/ | 1088 | /*First time init case*/ |
1089 | acr_fw = nvgpu_request_firmware(g, GM20B_HSBIN_PMU_UCODE_IMAGE, 0); | 1089 | acr_fw = nvgpu_request_firmware(g, GM20B_HSBIN_PMU_UCODE_IMAGE, 0); |
1090 | if (!acr_fw) { | 1090 | if (!acr_fw) { |
1091 | gk20a_err(dev_from_gk20a(g), "pmu ucode get fail"); | 1091 | nvgpu_err(g, "pmu ucode get fail"); |
1092 | return -ENOENT; | 1092 | return -ENOENT; |
1093 | } | 1093 | } |
1094 | acr->acr_fw = acr_fw; | 1094 | acr->acr_fw = acr_fw; |
@@ -1111,7 +1111,7 @@ static int gm20b_bootstrap_hs_flcn(struct gk20a *g) | |||
1111 | acr->fw_hdr->patch_loc), | 1111 | acr->fw_hdr->patch_loc), |
1112 | (u32 *)(acr_fw->data + | 1112 | (u32 *)(acr_fw->data + |
1113 | acr->fw_hdr->patch_sig)) < 0) { | 1113 | acr->fw_hdr->patch_sig)) < 0) { |
1114 | gk20a_err(dev_from_gk20a(g), "patch signatures fail"); | 1114 | nvgpu_err(g, "patch signatures fail"); |
1115 | err = -1; | 1115 | err = -1; |
1116 | goto err_release_acr_fw; | 1116 | goto err_release_acr_fw; |
1117 | } | 1117 | } |
@@ -1386,7 +1386,6 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1386 | { | 1386 | { |
1387 | struct mm_gk20a *mm = &g->mm; | 1387 | struct mm_gk20a *mm = &g->mm; |
1388 | struct vm_gk20a *vm = &mm->pmu.vm; | 1388 | struct vm_gk20a *vm = &mm->pmu.vm; |
1389 | struct device *d = dev_from_gk20a(g); | ||
1390 | int err = 0; | 1389 | int err = 0; |
1391 | u32 bl_sz; | 1390 | u32 bl_sz; |
1392 | struct acr_desc *acr = &g->acr; | 1391 | struct acr_desc *acr = &g->acr; |
@@ -1399,7 +1398,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1399 | hsbl_fw = nvgpu_request_firmware(g, | 1398 | hsbl_fw = nvgpu_request_firmware(g, |
1400 | GM20B_HSBIN_PMU_BL_UCODE_IMAGE, 0); | 1399 | GM20B_HSBIN_PMU_BL_UCODE_IMAGE, 0); |
1401 | if (!hsbl_fw) { | 1400 | if (!hsbl_fw) { |
1402 | gk20a_err(dev_from_gk20a(g), "pmu ucode load fail"); | 1401 | nvgpu_err(g, "pmu ucode load fail"); |
1403 | return -ENOENT; | 1402 | return -ENOENT; |
1404 | } | 1403 | } |
1405 | acr->hsbl_fw = hsbl_fw; | 1404 | acr->hsbl_fw = hsbl_fw; |
@@ -1420,7 +1419,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1420 | err = nvgpu_dma_alloc_flags_sys(g, | 1419 | err = nvgpu_dma_alloc_flags_sys(g, |
1421 | NVGPU_DMA_READ_ONLY, bl_sz, &acr->hsbl_ucode); | 1420 | NVGPU_DMA_READ_ONLY, bl_sz, &acr->hsbl_ucode); |
1422 | if (err) { | 1421 | if (err) { |
1423 | gk20a_err(d, "failed to allocate memory\n"); | 1422 | nvgpu_err(g, "failed to allocate memory\n"); |
1424 | goto err_done; | 1423 | goto err_done; |
1425 | } | 1424 | } |
1426 | 1425 | ||
@@ -1430,7 +1429,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1430 | gk20a_mem_flag_read_only, false, | 1429 | gk20a_mem_flag_read_only, false, |
1431 | acr->hsbl_ucode.aperture); | 1430 | acr->hsbl_ucode.aperture); |
1432 | if (!acr->hsbl_ucode.gpu_va) { | 1431 | if (!acr->hsbl_ucode.gpu_va) { |
1433 | gk20a_err(d, "failed to map pmu ucode memory!!"); | 1432 | nvgpu_err(g, "failed to map pmu ucode memory!!"); |
1434 | goto err_free_ucode; | 1433 | goto err_free_ucode; |
1435 | } | 1434 | } |
1436 | 1435 | ||
@@ -1506,7 +1505,7 @@ static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms) | |||
1506 | } while (!nvgpu_timeout_expired(&timeout)); | 1505 | } while (!nvgpu_timeout_expired(&timeout)); |
1507 | 1506 | ||
1508 | if (ret) { | 1507 | if (ret) { |
1509 | gk20a_err(dev_from_gk20a(g), "ACR boot timed out"); | 1508 | nvgpu_err(g, "ACR boot timed out"); |
1510 | return ret; | 1509 | return ret; |
1511 | } | 1510 | } |
1512 | 1511 | ||
@@ -1514,8 +1513,7 @@ static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms) | |||
1514 | gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities); | 1513 | gm20b_dbg_pmu("ACR capabilities %x\n", g->acr.capabilities); |
1515 | data = gk20a_readl(g, pwr_falcon_mailbox0_r()); | 1514 | data = gk20a_readl(g, pwr_falcon_mailbox0_r()); |
1516 | if (data) { | 1515 | if (data) { |
1517 | gk20a_err(dev_from_gk20a(g), | 1516 | nvgpu_err(g, "ACR boot failed, err %x", data); |
1518 | "ACR boot failed, err %x", data); | ||
1519 | ret = -EAGAIN; | 1517 | ret = -EAGAIN; |
1520 | } | 1518 | } |
1521 | 1519 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 451dd7b6..644140d8 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -310,7 +310,7 @@ static int clk_config_calibration_params(struct gk20a *g) | |||
310 | * (non-production config), report error, but allow to use | 310 | * (non-production config), report error, but allow to use |
311 | * boot internal calibration with default slope. | 311 | * boot internal calibration with default slope. |
312 | */ | 312 | */ |
313 | gk20a_err(dev_from_gk20a(g), "ADC coeff are not fused\n"); | 313 | nvgpu_err(g, "ADC coeff are not fused"); |
314 | return -EINVAL; | 314 | return -EINVAL; |
315 | } | 315 | } |
316 | return 0; | 316 | return 0; |
@@ -532,7 +532,7 @@ static int clk_enbale_pll_dvfs(struct gk20a *g) | |||
532 | } while (delay > 0); | 532 | } while (delay > 0); |
533 | 533 | ||
534 | if (delay <= 0) { | 534 | if (delay <= 0) { |
535 | gk20a_err(dev_from_gk20a(g), "GPCPLL calibration timeout"); | 535 | nvgpu_err(g, "GPCPLL calibration timeout"); |
536 | return -ETIMEDOUT; | 536 | return -ETIMEDOUT; |
537 | } | 537 | } |
538 | 538 | ||
@@ -564,8 +564,7 @@ static void clk_setup_slide(struct gk20a *g, u32 clk_u) | |||
564 | step_b = 0x05; | 564 | step_b = 0x05; |
565 | break; | 565 | break; |
566 | default: | 566 | default: |
567 | gk20a_err(dev_from_gk20a(g), "Unexpected reference rate %u kHz", | 567 | nvgpu_err(g, "Unexpected reference rate %u kHz", clk_u); |
568 | clk_u); | ||
569 | BUG(); | 568 | BUG(); |
570 | } | 569 | } |
571 | 570 | ||
@@ -671,7 +670,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, struct pll *gpll) | |||
671 | gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r()); | 670 | gk20a_readl(g, trim_sys_gpcpll_ndiv_slowdown_r()); |
672 | 671 | ||
673 | if (ramp_timeout <= 0) { | 672 | if (ramp_timeout <= 0) { |
674 | gk20a_err(dev_from_gk20a(g), "gpcpll dynamic ramp timeout"); | 673 | nvgpu_err(g, "gpcpll dynamic ramp timeout"); |
675 | return -ETIMEDOUT; | 674 | return -ETIMEDOUT; |
676 | } | 675 | } |
677 | return 0; | 676 | return 0; |
@@ -1041,7 +1040,7 @@ static int clk_program_na_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
1041 | 1040 | ||
1042 | ret = clk_program_gpc_pll(g, &gpll_safe, 1); | 1041 | ret = clk_program_gpc_pll(g, &gpll_safe, 1); |
1043 | if (ret) { | 1042 | if (ret) { |
1044 | gk20a_err(dev_from_gk20a(g), "Safe dvfs program fail\n"); | 1043 | nvgpu_err(g, "Safe dvfs program fail"); |
1045 | return ret; | 1044 | return ret; |
1046 | } | 1045 | } |
1047 | } | 1046 | } |
@@ -1154,8 +1153,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1154 | #endif | 1153 | #endif |
1155 | 1154 | ||
1156 | if (IS_ERR(ref)) { | 1155 | if (IS_ERR(ref)) { |
1157 | gk20a_err(dev_from_gk20a(g), | 1156 | nvgpu_err(g, "failed to get GPCPLL reference clock"); |
1158 | "failed to get GPCPLL reference clock"); | ||
1159 | err = -EINVAL; | 1157 | err = -EINVAL; |
1160 | goto fail; | 1158 | goto fail; |
1161 | } | 1159 | } |
@@ -1163,8 +1161,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1163 | clk->gpc_pll.id = GK20A_GPC_PLL; | 1161 | clk->gpc_pll.id = GK20A_GPC_PLL; |
1164 | clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; | 1162 | clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; |
1165 | if (clk->gpc_pll.clk_in == 0) { | 1163 | if (clk->gpc_pll.clk_in == 0) { |
1166 | gk20a_err(dev_from_gk20a(g), | 1164 | nvgpu_err(g, "GPCPLL reference clock is zero"); |
1167 | "GPCPLL reference clock is zero"); | ||
1168 | err = -EINVAL; | 1165 | err = -EINVAL; |
1169 | goto fail; | 1166 | goto fail; |
1170 | } | 1167 | } |
@@ -1327,8 +1324,7 @@ int gm20b_register_gpcclk(struct gk20a *g) { | |||
1327 | clk->hw.init = &init; | 1324 | clk->hw.init = &init; |
1328 | c = clk_register(g->dev, &clk->hw); | 1325 | c = clk_register(g->dev, &clk->hw); |
1329 | if (IS_ERR(c)) { | 1326 | if (IS_ERR(c)) { |
1330 | gk20a_err(dev_from_gk20a(g), | 1327 | nvgpu_err(g, "Failed to register GPCPLL clock"); |
1331 | "Failed to register GPCPLL clock"); | ||
1332 | return -EINVAL; | 1328 | return -EINVAL; |
1333 | } | 1329 | } |
1334 | 1330 | ||
@@ -1405,8 +1401,7 @@ static int set_pll_target(struct gk20a *g, u32 freq, u32 old_freq) | |||
1405 | /* gpc_pll.freq is changed to new value here */ | 1401 | /* gpc_pll.freq is changed to new value here */ |
1406 | if (clk_config_pll(clk, &clk->gpc_pll, &gpc_pll_params, | 1402 | if (clk_config_pll(clk, &clk->gpc_pll, &gpc_pll_params, |
1407 | &freq, true)) { | 1403 | &freq, true)) { |
1408 | gk20a_err(dev_from_gk20a(g), | 1404 | nvgpu_err(g, "failed to set pll target for %d", freq); |
1409 | "failed to set pll target for %d", freq); | ||
1410 | return -EINVAL; | 1405 | return -EINVAL; |
1411 | } | 1406 | } |
1412 | } | 1407 | } |
@@ -1442,8 +1437,7 @@ static int set_pll_freq(struct gk20a *g, int allow_slide) | |||
1442 | * Just report error but not restore PLL since dvfs could already change | 1437 | * Just report error but not restore PLL since dvfs could already change |
1443 | * voltage even when programming failed. | 1438 | * voltage even when programming failed. |
1444 | */ | 1439 | */ |
1445 | gk20a_err(dev_from_gk20a(g), "failed to set pll to %d", | 1440 | nvgpu_err(g, "failed to set pll to %d", clk->gpc_pll.freq); |
1446 | clk->gpc_pll.freq); | ||
1447 | return err; | 1441 | return err; |
1448 | } | 1442 | } |
1449 | 1443 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c index 9c5b730b..c49d2da9 100644 --- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c | |||
@@ -121,7 +121,7 @@ static void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) | |||
121 | val &= ~0x3; | 121 | val &= ~0x3; |
122 | val |= fb_mmu_vpr_info_index_addr_lo_v(); | 122 | val |= fb_mmu_vpr_info_index_addr_lo_v(); |
123 | gk20a_writel(g, fb_mmu_vpr_info_r(), val); | 123 | gk20a_writel(g, fb_mmu_vpr_info_r(), val); |
124 | gk20a_err(dev_from_gk20a(g), "VPR: %08x %08x %08x %08x", | 124 | nvgpu_err(g, "VPR: %08x %08x %08x %08x", |
125 | gk20a_readl(g, fb_mmu_vpr_info_r()), | 125 | gk20a_readl(g, fb_mmu_vpr_info_r()), |
126 | gk20a_readl(g, fb_mmu_vpr_info_r()), | 126 | gk20a_readl(g, fb_mmu_vpr_info_r()), |
127 | gk20a_readl(g, fb_mmu_vpr_info_r()), | 127 | gk20a_readl(g, fb_mmu_vpr_info_r()), |
@@ -131,7 +131,7 @@ static void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) | |||
131 | val &= ~0xf; | 131 | val &= ~0xf; |
132 | val |= (fb_mmu_wpr_info_index_allow_read_v()); | 132 | val |= (fb_mmu_wpr_info_index_allow_read_v()); |
133 | gk20a_writel(g, fb_mmu_wpr_info_r(), val); | 133 | gk20a_writel(g, fb_mmu_wpr_info_r(), val); |
134 | gk20a_err(dev_from_gk20a(g), "WPR: %08x %08x %08x %08x %08x %08x", | 134 | nvgpu_err(g, "WPR: %08x %08x %08x %08x %08x %08x", |
135 | gk20a_readl(g, fb_mmu_wpr_info_r()), | 135 | gk20a_readl(g, fb_mmu_wpr_info_r()), |
136 | gk20a_readl(g, fb_mmu_wpr_info_r()), | 136 | gk20a_readl(g, fb_mmu_wpr_info_r()), |
137 | gk20a_readl(g, fb_mmu_wpr_info_r()), | 137 | gk20a_readl(g, fb_mmu_wpr_info_r()), |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 6c34689b..e3aa43d6 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include "fifo_gm20b.h" | 21 | #include "fifo_gm20b.h" |
22 | 22 | ||
23 | #include <nvgpu/timers.h> | 23 | #include <nvgpu/timers.h> |
24 | #include <nvgpu/log.h> | ||
24 | 25 | ||
25 | #include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h> | 26 | #include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h> |
26 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | 27 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> |
@@ -64,7 +65,7 @@ static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id) | |||
64 | if (engine_info) { | 65 | if (engine_info) { |
65 | fault_id = engine_info->fault_id; | 66 | fault_id = engine_info->fault_id; |
66 | } else { | 67 | } else { |
67 | gk20a_err(g->dev, "engine_id is not in active list/invalid %d", engine_id); | 68 | nvgpu_err(g, "engine_id is not in active list/invalid %d", engine_id); |
68 | } | 69 | } |
69 | return fault_id; | 70 | return fault_id; |
70 | } | 71 | } |
@@ -80,8 +81,7 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | |||
80 | /* trigger faults for all bad engines */ | 81 | /* trigger faults for all bad engines */ |
81 | for_each_set_bit(engine_id, &engine_ids, 32) { | 82 | for_each_set_bit(engine_id, &engine_ids, 32) { |
82 | if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) { | 83 | if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) { |
83 | gk20a_err(dev_from_gk20a(g), | 84 | nvgpu_err(g, "faulting unknown engine %ld", engine_id); |
84 | "faulting unknown engine %ld", engine_id); | ||
85 | } else { | 85 | } else { |
86 | u32 mmu_id = gm20b_engine_id_to_mmu_id(g, | 86 | u32 mmu_id = gm20b_engine_id_to_mmu_id(g, |
87 | engine_id); | 87 | engine_id); |
@@ -107,7 +107,7 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | |||
107 | } while (!nvgpu_timeout_expired(&timeout)); | 107 | } while (!nvgpu_timeout_expired(&timeout)); |
108 | 108 | ||
109 | if (ret) | 109 | if (ret) |
110 | gk20a_err(dev_from_gk20a(g), "mmu fault timeout"); | 110 | nvgpu_err(g, "mmu fault timeout"); |
111 | 111 | ||
112 | /* release mmu fault trigger */ | 112 | /* release mmu fault trigger */ |
113 | for_each_set_bit(engine_id, &engine_ids, 32) | 113 | for_each_set_bit(engine_id, &engine_ids, 32) |
@@ -136,7 +136,7 @@ static void gm20b_device_info_data_parse(struct gk20a *g, | |||
136 | top_device_info_data_fault_id_enum_v(table_entry); | 136 | top_device_info_data_fault_id_enum_v(table_entry); |
137 | } | 137 | } |
138 | } else | 138 | } else |
139 | gk20a_err(g->dev, "unknown device_info_data %d", | 139 | nvgpu_err(g, "unknown device_info_data %d", |
140 | top_device_info_data_type_v(table_entry)); | 140 | top_device_info_data_type_v(table_entry)); |
141 | } | 141 | } |
142 | 142 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index ab169a60..74c35c02 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include <dt-bindings/soc/gm20b-fuse.h> | 21 | #include <dt-bindings/soc/gm20b-fuse.h> |
22 | 22 | ||
23 | #include <nvgpu/kmem.h> | 23 | #include <nvgpu/kmem.h> |
24 | #include <nvgpu/log.h> | ||
24 | 25 | ||
25 | #include "gk20a/gk20a.h" | 26 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/gr_gk20a.h" | 27 | #include "gk20a/gr_gk20a.h" |
@@ -754,8 +755,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
754 | (1 << LSF_FALCON_ID_GPCCS)); | 755 | (1 << LSF_FALCON_ID_GPCCS)); |
755 | } | 756 | } |
756 | if (err) { | 757 | if (err) { |
757 | gk20a_err(dev_from_gk20a(g), | 758 | nvgpu_err(g, "Unable to recover GR falcon"); |
758 | "Unable to recover GR falcon"); | ||
759 | return err; | 759 | return err; |
760 | } | 760 | } |
761 | 761 | ||
@@ -775,8 +775,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
775 | err = g->ops.pmu.load_lsfalcon_ucode(g, falcon_id_mask); | 775 | err = g->ops.pmu.load_lsfalcon_ucode(g, falcon_id_mask); |
776 | 776 | ||
777 | if (err) { | 777 | if (err) { |
778 | gk20a_err(dev_from_gk20a(g), | 778 | nvgpu_err(g, "Unable to boot GPCCS"); |
779 | "Unable to boot GPCCS\n"); | ||
780 | return err; | 779 | return err; |
781 | } | 780 | } |
782 | } | 781 | } |
@@ -1294,7 +1293,7 @@ static int gm20b_gr_update_sm_error_state(struct gk20a *g, | |||
1294 | 1293 | ||
1295 | err = gr_gk20a_disable_ctxsw(g); | 1294 | err = gr_gk20a_disable_ctxsw(g); |
1296 | if (err) { | 1295 | if (err) { |
1297 | gk20a_err(dev_from_gk20a(g), "unable to stop gr ctxsw\n"); | 1296 | nvgpu_err(g, "unable to stop gr ctxsw"); |
1298 | goto fail; | 1297 | goto fail; |
1299 | } | 1298 | } |
1300 | 1299 | ||
@@ -1356,7 +1355,7 @@ static int gm20b_gr_clear_sm_error_state(struct gk20a *g, | |||
1356 | 1355 | ||
1357 | err = gr_gk20a_disable_ctxsw(g); | 1356 | err = gr_gk20a_disable_ctxsw(g); |
1358 | if (err) { | 1357 | if (err) { |
1359 | gk20a_err(dev_from_gk20a(g), "unable to stop gr ctxsw\n"); | 1358 | nvgpu_err(g, "unable to stop gr ctxsw"); |
1360 | goto fail; | 1359 | goto fail; |
1361 | } | 1360 | } |
1362 | 1361 | ||
@@ -1434,8 +1433,7 @@ static int gm20b_gr_fuse_override(struct gk20a *g) | |||
1434 | gm20b_gr_tpc_disable_override(g, value); | 1433 | gm20b_gr_tpc_disable_override(g, value); |
1435 | break; | 1434 | break; |
1436 | default: | 1435 | default: |
1437 | gk20a_err(dev_from_gk20a(g), | 1436 | nvgpu_err(g, "ignore unknown fuse override %08x", fuse); |
1438 | "ignore unknown fuse override %08x", fuse); | ||
1439 | break; | 1437 | break; |
1440 | } | 1438 | } |
1441 | } | 1439 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index bfae27c0..a6ca5abf 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -169,7 +169,7 @@ static int gm20b_get_litter_value(struct gk20a *g, int value) | |||
169 | ret = 0; | 169 | ret = 0; |
170 | break; | 170 | break; |
171 | default: | 171 | default: |
172 | gk20a_err(dev_from_gk20a(g), "Missing definition %d", value); | 172 | nvgpu_err(g, "Missing definition %d", value); |
173 | BUG(); | 173 | BUG(); |
174 | break; | 174 | break; |
175 | } | 175 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 491112fc..be07f5a7 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -153,8 +153,7 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | |||
153 | } while (!nvgpu_timeout_expired(&timeout)); | 153 | } while (!nvgpu_timeout_expired(&timeout)); |
154 | 154 | ||
155 | if (nvgpu_timeout_peek_expired(&timeout)) { | 155 | if (nvgpu_timeout_peek_expired(&timeout)) { |
156 | gk20a_err(dev_from_gk20a(g), | 156 | nvgpu_err(g, "comp tag clear timeout"); |
157 | "comp tag clear timeout\n"); | ||
158 | err = -EBUSY; | 157 | err = -EBUSY; |
159 | goto out; | 158 | goto out; |
160 | } | 159 | } |
@@ -201,8 +200,7 @@ void gm20b_ltc_isr(struct gk20a *g) | |||
201 | u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); | 200 | u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); |
202 | 201 | ||
203 | mc_intr = gk20a_readl(g, mc_intr_ltc_r()); | 202 | mc_intr = gk20a_readl(g, mc_intr_ltc_r()); |
204 | gk20a_err(dev_from_gk20a(g), "mc_ltc_intr: %08x", | 203 | nvgpu_err(g, "mc_ltc_intr: %08x", mc_intr); |
205 | mc_intr); | ||
206 | for (ltc = 0; ltc < g->ltc_count; ltc++) { | 204 | for (ltc = 0; ltc < g->ltc_count; ltc++) { |
207 | if ((mc_intr & 1 << ltc) == 0) | 205 | if ((mc_intr & 1 << ltc) == 0) |
208 | continue; | 206 | continue; |
@@ -210,7 +208,7 @@ void gm20b_ltc_isr(struct gk20a *g) | |||
210 | ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + | 208 | ltc_intr = gk20a_readl(g, ltc_ltc0_lts0_intr_r() + |
211 | ltc_stride * ltc + | 209 | ltc_stride * ltc + |
212 | lts_stride * slice); | 210 | lts_stride * slice); |
213 | gk20a_err(dev_from_gk20a(g), "ltc%d, slice %d: %08x", | 211 | nvgpu_err(g, "ltc%d, slice %d: %08x", |
214 | ltc, slice, ltc_intr); | 212 | ltc, slice, ltc_intr); |
215 | gk20a_writel(g, ltc_ltc0_lts0_intr_r() + | 213 | gk20a_writel(g, ltc_ltc0_lts0_intr_r() + |
216 | ltc_stride * ltc + | 214 | ltc_stride * ltc + |
@@ -226,8 +224,7 @@ u32 gm20b_ltc_cbc_fix_config(struct gk20a *g, int base) | |||
226 | if (val == 2) { | 224 | if (val == 2) { |
227 | return base * 2; | 225 | return base * 2; |
228 | } else if (val != 1) { | 226 | } else if (val != 1) { |
229 | gk20a_err(dev_from_gk20a(g), | 227 | nvgpu_err(g, "Invalid number of active ltcs: %08x\n", val); |
230 | "Invalid number of active ltcs: %08x\n", val); | ||
231 | } | 228 | } |
232 | 229 | ||
233 | return base; | 230 | return base; |
@@ -335,8 +332,7 @@ static int gm20b_determine_L2_size_bytes(struct gk20a *g) | |||
335 | ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()) { | 332 | ltc_ltc0_lts0_tstg_cfg1_active_sets_quarter_v()) { |
336 | sets = 16; | 333 | sets = 16; |
337 | } else { | 334 | } else { |
338 | dev_err(dev_from_gk20a(g), | 335 | nvgpu_err(g, "Unknown constant %u for active sets", |
339 | "Unknown constant %u for active sets", | ||
340 | (unsigned)active_sets_value); | 336 | (unsigned)active_sets_value); |
341 | sets = 0; | 337 | sets = 0; |
342 | } | 338 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 38509f69..730c5eaf 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -242,8 +242,7 @@ static int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | |||
242 | &g->ops.pmu.lspmuwprinitdone, 1); | 242 | &g->ops.pmu.lspmuwprinitdone, 1); |
243 | /* check again if it still not ready indicate an error */ | 243 | /* check again if it still not ready indicate an error */ |
244 | if (!g->ops.pmu.lspmuwprinitdone) { | 244 | if (!g->ops.pmu.lspmuwprinitdone) { |
245 | gk20a_err(dev_from_gk20a(g), | 245 | nvgpu_err(g, "PMU not ready to load LSF"); |
246 | "PMU not ready to load LSF"); | ||
247 | return -ETIMEDOUT; | 246 | return -ETIMEDOUT; |
248 | } | 247 | } |
249 | } | 248 | } |
@@ -266,12 +265,12 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | |||
266 | { | 265 | { |
267 | u32 val; | 266 | u32 val; |
268 | 267 | ||
269 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | 268 | nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", |
270 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 269 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
271 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 270 | nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", |
272 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 271 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
273 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); | 272 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); |
274 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 273 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", |
275 | val); | 274 | val); |
276 | } | 275 | } |
277 | 276 | ||