diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_dev.c | 14 |
2 files changed, 16 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c index 4bf03661..1dd3922a 100644 --- a/drivers/gpu/nvgpu/gp106/clk_gp106.c +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -36,7 +36,12 @@ static int clk_gp106_debugfs_init(struct gk20a *g); | |||
36 | #endif | 36 | #endif |
37 | 37 | ||
38 | #define NUM_NAMEMAPS 4 | 38 | #define NUM_NAMEMAPS 4 |
39 | #define XTAL4X_KHZ 108000 | ||
39 | 40 | ||
41 | static u32 gp106_crystal_clk_hz(struct gk20a *g) | ||
42 | { | ||
43 | return (XTAL4X_KHZ * 1000); | ||
44 | } | ||
40 | static int gp106_init_clk_support(struct gk20a *g) { | 45 | static int gp106_init_clk_support(struct gk20a *g) { |
41 | struct clk_gk20a *clk = &g->clk; | 46 | struct clk_gk20a *clk = &g->clk; |
42 | u32 err = 0; | 47 | u32 err = 0; |
@@ -221,6 +226,7 @@ err_out: | |||
221 | 226 | ||
222 | void gp106_init_clk_ops(struct gpu_ops *gops) { | 227 | void gp106_init_clk_ops(struct gpu_ops *gops) { |
223 | gops->clk.init_clk_support = gp106_init_clk_support; | 228 | gops->clk.init_clk_support = gp106_init_clk_support; |
229 | gops->clk.get_crystal_clk_hz = gp106_crystal_clk_hz; | ||
224 | } | 230 | } |
225 | 231 | ||
226 | 232 | ||
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index 89040658..3a7ed1b5 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c | |||
@@ -26,7 +26,6 @@ | |||
26 | #include "include/bios.h" | 26 | #include "include/bios.h" |
27 | #include "volt.h" | 27 | #include "volt.h" |
28 | 28 | ||
29 | #define RAW_PERIOD 160 | ||
30 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 | 29 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 |
31 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 | 30 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 |
32 | 31 | ||
@@ -257,17 +256,24 @@ static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g, | |||
257 | 256 | ||
258 | if (ptmp_dev->super.operation_type == | 257 | if (ptmp_dev->super.operation_type == |
259 | CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { | 258 | CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) { |
260 | ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; | 259 | if (volt_domain == CTRL_VOLT_DOMAIN_LOGIC) |
260 | ptmp_dev->source = | ||
261 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_0; | ||
262 | if (volt_domain == CTRL_VOLT_DOMAIN_SRAM) | ||
263 | ptmp_dev->source = | ||
264 | NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1; | ||
265 | ptmp_dev->raw_period = | ||
266 | g->ops.clk.get_crystal_clk_hz(g) / frequency_hz; | ||
261 | } else if (ptmp_dev->super.operation_type == | 267 | } else if (ptmp_dev->super.operation_type == |
262 | CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) { | 268 | CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) { |
263 | ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0; | 269 | ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0; |
270 | ptmp_dev->raw_period = 0; | ||
264 | } else if (ptmp_dev->super.operation_type == | 271 | } else if (ptmp_dev->super.operation_type == |
265 | CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) { | 272 | CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) { |
266 | ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1; | 273 | ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1; |
274 | ptmp_dev->raw_period = 0; | ||
267 | } | 275 | } |
268 | 276 | ||
269 | ptmp_dev->raw_period = RAW_PERIOD; | ||
270 | |||
271 | /* Initialize data for parent class. */ | 277 | /* Initialize data for parent class. */ |
272 | ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM; | 278 | ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM; |
273 | ptmp_dev->super.volt_domain = volt_domain; | 279 | ptmp_dev->super.volt_domain = volt_domain; |