diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.sources | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/perf_gv100.c | 120 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/perf_gv100.h | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/perf.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/perf.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pstate/pstate.c | 2 |
13 files changed, 211 insertions, 23 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 926ce056..3d7671d0 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -333,6 +333,7 @@ nvgpu-y += \ | |||
333 | gv100/nvlink_gv100.o \ | 333 | gv100/nvlink_gv100.o \ |
334 | gv100/hal_gv100.o \ | 334 | gv100/hal_gv100.o \ |
335 | gv100/pmu_gv100.o \ | 335 | gv100/pmu_gv100.o \ |
336 | gv100/perf_gv100.o \ | ||
336 | pstate/pstate.o \ | 337 | pstate/pstate.o \ |
337 | clk/clk_vin.o \ | 338 | clk/clk_vin.o \ |
338 | clk/clk_fll.o \ | 339 | clk/clk_fll.o \ |
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index a26f827d..5c15ebd0 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources | |||
@@ -215,4 +215,5 @@ srcs := os/posix/nvgpu.c \ | |||
215 | gv100/flcn_gv100.c \ | 215 | gv100/flcn_gv100.c \ |
216 | gv100/nvlink_gv100.c \ | 216 | gv100/nvlink_gv100.c \ |
217 | gv100/hal_gv100.c \ | 217 | gv100/hal_gv100.c \ |
218 | gv100/pmu_gv100.c | 218 | gv100/pmu_gv100.c \ |
219 | gv100/perf_gv100.c | ||
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index f0624595..8532a08b 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -866,6 +866,43 @@ u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g) | |||
866 | return status; | 866 | return status; |
867 | } | 867 | } |
868 | 868 | ||
869 | int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g) | ||
870 | { | ||
871 | int status; | ||
872 | struct change_fll_clk bootfllclk; | ||
873 | u16 gpcclk_clkmhz = BOOT_GPCCLK_MHZ; | ||
874 | u32 gpcclk_voltuv = 0U; | ||
875 | u32 voltuv = 0U; | ||
876 | |||
877 | status = clk_vf_point_cache(g); | ||
878 | if (status != 0) { | ||
879 | nvgpu_err(g, "caching failed"); | ||
880 | return status; | ||
881 | } | ||
882 | |||
883 | status = clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_GPCCLK, | ||
884 | &gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); | ||
885 | if (status != 0) { | ||
886 | return status; | ||
887 | } | ||
888 | |||
889 | voltuv = gpcclk_voltuv; | ||
890 | |||
891 | status = volt_set_voltage(g, voltuv, 0U); | ||
892 | if (status != 0) { | ||
893 | nvgpu_err(g, "attempt to set max voltage failed %d", voltuv); | ||
894 | } | ||
895 | |||
896 | bootfllclk.api_clk_domain = CTRL_CLK_DOMAIN_GPCCLK; | ||
897 | bootfllclk.clkmhz = gpcclk_clkmhz; | ||
898 | bootfllclk.voltuv = voltuv; | ||
899 | status = clk_program_fllclks(g, &bootfllclk); | ||
900 | if (status != 0) { | ||
901 | nvgpu_err(g, "attempt to set max gpcclk failed"); | ||
902 | } | ||
903 | return status; | ||
904 | } | ||
905 | |||
869 | u32 clk_domain_get_f_or_v( | 906 | u32 clk_domain_get_f_or_v( |
870 | struct gk20a *g, | 907 | struct gk20a *g, |
871 | u32 clkapidomain, | 908 | u32 clkapidomain, |
diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h index 5a6aeae3..3f4bdf73 100644 --- a/drivers/gpu/nvgpu/clk/clk.h +++ b/drivers/gpu/nvgpu/clk/clk.h | |||
@@ -138,6 +138,7 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g, | |||
138 | struct nv_pmu_clk_rpc *rpccall, | 138 | struct nv_pmu_clk_rpc *rpccall, |
139 | struct set_fll_clk *setfllclk); | 139 | struct set_fll_clk *setfllclk); |
140 | u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g); | 140 | u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g); |
141 | int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g); | ||
141 | int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload); | 142 | int clk_pmu_freq_effective_avg_load(struct gk20a *g, bool bload); |
142 | u32 clk_freq_effective_avg(struct gk20a *g, u32 clkDomainMask); | 143 | u32 clk_freq_effective_avg(struct gk20a *g, u32 clkDomainMask); |
143 | #endif /* NVGPU_CLK_H */ | 144 | #endif /* NVGPU_CLK_H */ |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index a94453fb..c2d6a921 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -1325,8 +1325,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1325 | clk_avfs_get_vin_cal_fuse_v20; | 1325 | clk_avfs_get_vin_cal_fuse_v20; |
1326 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = | 1326 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = |
1327 | nvgpu_clk_vf_change_inject_data_fill_gv10x; | 1327 | nvgpu_clk_vf_change_inject_data_fill_gv10x; |
1328 | g->ops.pmu_ver.clk.perf_pmu_vfe_load = | ||
1329 | perf_pmu_vfe_load_gv10x; | ||
1330 | g->ops.pmu_ver.clk.clk_set_boot_clk = | 1328 | g->ops.pmu_ver.clk.clk_set_boot_clk = |
1331 | nvgpu_clk_set_boot_fll_clk_gv10x; | 1329 | nvgpu_clk_set_boot_fll_clk_gv10x; |
1332 | } else { | 1330 | } else { |
@@ -1500,8 +1498,6 @@ static int nvgpu_init_pmu_fw_ver_ops(struct nvgpu_pmu *pmu) | |||
1500 | clk_avfs_get_vin_cal_fuse_v10; | 1498 | clk_avfs_get_vin_cal_fuse_v10; |
1501 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = | 1499 | g->ops.pmu_ver.clk.clk_vf_change_inject_data_fill = |
1502 | nvgpu_clk_vf_change_inject_data_fill_gp10x; | 1500 | nvgpu_clk_vf_change_inject_data_fill_gp10x; |
1503 | g->ops.pmu_ver.clk.perf_pmu_vfe_load = | ||
1504 | perf_pmu_vfe_load; | ||
1505 | break; | 1501 | break; |
1506 | case APP_VERSION_GM20B: | 1502 | case APP_VERSION_GM20B: |
1507 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = | 1503 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index d3804f0e..063fbbe3 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -676,6 +676,7 @@ static const struct gpu_ops gp106_ops = { | |||
676 | .mclk_init = gp106_mclk_init, | 676 | .mclk_init = gp106_mclk_init, |
677 | .mclk_change = gp106_mclk_change, | 677 | .mclk_change = gp106_mclk_change, |
678 | .mclk_deinit = gp106_mclk_deinit, | 678 | .mclk_deinit = gp106_mclk_deinit, |
679 | .perf_pmu_vfe_load = perf_pmu_vfe_load, | ||
679 | }, | 680 | }, |
680 | .clk_arb = { | 681 | .clk_arb = { |
681 | .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, | 682 | .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, |
@@ -844,6 +845,7 @@ int gp106_init_hal(struct gk20a *g) | |||
844 | gops->clk.mclk_change = gp106_ops.clk.mclk_change; | 845 | gops->clk.mclk_change = gp106_ops.clk.mclk_change; |
845 | gops->clk.mclk_deinit = gp106_ops.clk.mclk_deinit; | 846 | gops->clk.mclk_deinit = gp106_ops.clk.mclk_deinit; |
846 | gops->clk.clk_domain_get_f_points = gp106_ops.clk.clk_domain_get_f_points; | 847 | gops->clk.clk_domain_get_f_points = gp106_ops.clk.clk_domain_get_f_points; |
848 | gops->clk.perf_pmu_vfe_load = gp106_ops.clk.perf_pmu_vfe_load; | ||
847 | 849 | ||
848 | gops->clk_arb = gp106_ops.clk_arb; | 850 | gops->clk_arb = gp106_ops.clk_arb; |
849 | gops->regops = gp106_ops.regops; | 851 | gops->regops = gp106_ops.regops; |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index ee6dd436..0c64ce58 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -107,6 +107,7 @@ | |||
107 | #include "gv100/pmu_gv100.h" | 107 | #include "gv100/pmu_gv100.h" |
108 | #include "gv100/nvlink_gv100.h" | 108 | #include "gv100/nvlink_gv100.h" |
109 | #include "gv100/regops_gv100.h" | 109 | #include "gv100/regops_gv100.h" |
110 | #include "gv100/perf_gv100.h" | ||
110 | 111 | ||
111 | #include <nvgpu/ptimer.h> | 112 | #include <nvgpu/ptimer.h> |
112 | #include <nvgpu/debug.h> | 113 | #include <nvgpu/debug.h> |
@@ -770,6 +771,7 @@ static const struct gpu_ops gv100_ops = { | |||
770 | .get_rate_cntr = gp106_get_rate_cntr, | 771 | .get_rate_cntr = gp106_get_rate_cntr, |
771 | .measure_freq = gp106_clk_measure_freq, | 772 | .measure_freq = gp106_clk_measure_freq, |
772 | .suspend_clk_support = gp106_suspend_clk_support, | 773 | .suspend_clk_support = gp106_suspend_clk_support, |
774 | .perf_pmu_vfe_load = gv100_perf_pmu_vfe_load, | ||
773 | }, | 775 | }, |
774 | .clk_arb = { | 776 | .clk_arb = { |
775 | .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, | 777 | .get_arbiter_clk_domains = gp106_get_arbiter_clk_domains, |
@@ -981,6 +983,7 @@ int gv100_init_hal(struct gk20a *g) | |||
981 | gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; | 983 | gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz; |
982 | gops->clk.measure_freq = gv100_ops.clk.measure_freq; | 984 | gops->clk.measure_freq = gv100_ops.clk.measure_freq; |
983 | gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; | 985 | gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support; |
986 | gops->clk.perf_pmu_vfe_load = gv100_ops.clk.perf_pmu_vfe_load; | ||
984 | 987 | ||
985 | /* Lone functions */ | 988 | /* Lone functions */ |
986 | gops->chip_init_gpu_characteristics = | 989 | gops->chip_init_gpu_characteristics = |
diff --git a/drivers/gpu/nvgpu/gv100/perf_gv100.c b/drivers/gpu/nvgpu/gv100/perf_gv100.c new file mode 100644 index 00000000..f3ba78ba --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/perf_gv100.c | |||
@@ -0,0 +1,120 @@ | |||
1 | /* | ||
2 | * GV100 PERF | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/pmu.h> | ||
26 | #include <nvgpu/bug.h> | ||
27 | |||
28 | #include "gk20a/gk20a.h" | ||
29 | #include "gv100/perf_gv100.h" | ||
30 | |||
31 | static int pmu_set_boot_clk_runcb_fn(void *arg) | ||
32 | { | ||
33 | struct gk20a *g = (struct gk20a *)arg; | ||
34 | struct nvgpu_pmu *pmu = &g->pmu; | ||
35 | struct nv_pmu_rpc_struct_perf_load rpc; | ||
36 | struct perf_pmupstate *perf_pmu = &g->perf_pmu; | ||
37 | struct nvgpu_vfe_invalidate *vfe_init = &perf_pmu->vfe_init; | ||
38 | int status = 0; | ||
39 | |||
40 | nvgpu_log_fn(g, "thread start"); | ||
41 | |||
42 | while (true) { | ||
43 | NVGPU_COND_WAIT_INTERRUPTIBLE(&vfe_init->wq, | ||
44 | (vfe_init->state_change == true), 0); | ||
45 | |||
46 | vfe_init->state_change = false; | ||
47 | |||
48 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load)); | ||
49 | PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0); | ||
50 | if (status != 0) { | ||
51 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
52 | status); | ||
53 | } | ||
54 | status = nvgpu_clk_set_fll_clk_gv10x(g); | ||
55 | } | ||
56 | |||
57 | return 0; | ||
58 | } | ||
59 | |||
60 | static int gv100_pmu_handle_perf_event(struct gk20a *g, void *pmumsg) | ||
61 | { | ||
62 | struct nv_pmu_perf_msg *msg = (struct nv_pmu_perf_msg *)pmumsg; | ||
63 | struct perf_pmupstate *perf_pmu = &g->perf_pmu; | ||
64 | |||
65 | nvgpu_log_fn(g, " "); | ||
66 | switch (msg->msg_type) { | ||
67 | case NV_PMU_PERF_MSG_ID_VFE_CALLBACK: | ||
68 | perf_pmu->vfe_init.state_change = true; | ||
69 | nvgpu_cond_signal(&perf_pmu->vfe_init.wq); | ||
70 | break; | ||
71 | default: | ||
72 | WARN_ON(1); | ||
73 | break; | ||
74 | } | ||
75 | return 0; | ||
76 | } | ||
77 | |||
78 | u32 perf_pmu_init_vfe_perf_event(struct gk20a *g) | ||
79 | { | ||
80 | struct perf_pmupstate *perf_pmu = &g->perf_pmu; | ||
81 | char thread_name[64]; | ||
82 | u32 err = 0; | ||
83 | |||
84 | nvgpu_log_fn(g, " "); | ||
85 | |||
86 | nvgpu_cond_init(&perf_pmu->vfe_init.wq); | ||
87 | |||
88 | snprintf(thread_name, sizeof(thread_name), | ||
89 | "nvgpu_vfe_invalidate_init_%s", g->name); | ||
90 | |||
91 | err = nvgpu_thread_create(&perf_pmu->vfe_init.state_task, g, | ||
92 | pmu_set_boot_clk_runcb_fn, thread_name); | ||
93 | if (err != 0U) { | ||
94 | nvgpu_err(g, "failed to start nvgpu_vfe_invalidate_init thread"); | ||
95 | } | ||
96 | |||
97 | return err; | ||
98 | |||
99 | } | ||
100 | |||
101 | u32 gv100_perf_pmu_vfe_load(struct gk20a *g) | ||
102 | { | ||
103 | struct nvgpu_pmu *pmu = &g->pmu; | ||
104 | struct nv_pmu_rpc_struct_perf_load rpc; | ||
105 | u32 status = 0; | ||
106 | |||
107 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load)); | ||
108 | PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0); | ||
109 | if (status != 0U) { | ||
110 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
111 | status); | ||
112 | } | ||
113 | |||
114 | perf_pmu_init_vfe_perf_event(g); | ||
115 | |||
116 | /*register call back for future VFE updates*/ | ||
117 | g->ops.perf.handle_pmu_perf_event = gv100_pmu_handle_perf_event; | ||
118 | |||
119 | return status; | ||
120 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/perf_gv100.h b/drivers/gpu/nvgpu/gv100/perf_gv100.h new file mode 100644 index 00000000..e128c06a --- /dev/null +++ b/drivers/gpu/nvgpu/gv100/perf_gv100.h | |||
@@ -0,0 +1,36 @@ | |||
1 | /* | ||
2 | * GV100 PERF | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef __PERF_GV100_H_ | ||
26 | #define __PERF_GV100_H_ | ||
27 | |||
28 | #include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> | ||
29 | |||
30 | struct gk20a; | ||
31 | |||
32 | u32 perf_pmu_init_vfe_perf_event(struct gk20a *g); | ||
33 | u32 gv100_perf_pmu_vfe_load(struct gk20a *g); | ||
34 | |||
35 | |||
36 | #endif /*__PERF_GV100_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 5f875707..e2a0cbf7 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -878,7 +878,6 @@ struct gpu_ops { | |||
878 | u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g, | 878 | u32 (*clk_vf_change_inject_data_fill)(struct gk20a *g, |
879 | struct nv_pmu_clk_rpc *rpccall, | 879 | struct nv_pmu_clk_rpc *rpccall, |
880 | struct set_fll_clk *setfllclk); | 880 | struct set_fll_clk *setfllclk); |
881 | u32 (*perf_pmu_vfe_load)(struct gk20a *g); | ||
882 | u32 (*clk_set_boot_clk)(struct gk20a *g); | 881 | u32 (*clk_set_boot_clk)(struct gk20a *g); |
883 | }clk; | 882 | }clk; |
884 | } pmu_ver; | 883 | } pmu_ver; |
@@ -1113,6 +1112,7 @@ struct gpu_ops { | |||
1113 | bool support_clk_freq_controller; | 1112 | bool support_clk_freq_controller; |
1114 | bool support_pmgr_domain; | 1113 | bool support_pmgr_domain; |
1115 | bool support_lpwr_pg; | 1114 | bool support_lpwr_pg; |
1115 | u32 (*perf_pmu_vfe_load)(struct gk20a *g); | ||
1116 | } clk; | 1116 | } clk; |
1117 | struct { | 1117 | struct { |
1118 | int (*arbiter_clk_init)(struct gk20a *g); | 1118 | int (*arbiter_clk_init)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c index daed6f54..582b2577 100644 --- a/drivers/gpu/nvgpu/perf/perf.c +++ b/drivers/gpu/nvgpu/perf/perf.c | |||
@@ -67,21 +67,6 @@ static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg) | |||
67 | return 0; | 67 | return 0; |
68 | } | 68 | } |
69 | 69 | ||
70 | u32 perf_pmu_vfe_load_gv10x(struct gk20a *g) | ||
71 | { | ||
72 | struct nvgpu_pmu *pmu = &g->pmu; | ||
73 | struct nv_pmu_rpc_struct_perf_load rpc; | ||
74 | u32 status = 0; | ||
75 | |||
76 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perf_load)); | ||
77 | PMU_RPC_EXECUTE_CPB(status, pmu, PERF, VFE_INVALIDATE, &rpc, 0); | ||
78 | if (status) { | ||
79 | nvgpu_err(g, "Failed to execute RPC status=0x%x", | ||
80 | status); | ||
81 | } | ||
82 | return status; | ||
83 | } | ||
84 | |||
85 | u32 perf_pmu_vfe_load(struct gk20a *g) | 70 | u32 perf_pmu_vfe_load(struct gk20a *g) |
86 | { | 71 | { |
87 | struct pmu_cmd cmd; | 72 | struct pmu_cmd cmd; |
diff --git a/drivers/gpu/nvgpu/perf/perf.h b/drivers/gpu/nvgpu/perf/perf.h index 180efb2c..17a9b0e1 100644 --- a/drivers/gpu/nvgpu/perf/perf.h +++ b/drivers/gpu/nvgpu/perf/perf.h | |||
@@ -65,15 +65,21 @@ | |||
65 | 65 | ||
66 | struct gk20a; | 66 | struct gk20a; |
67 | 67 | ||
68 | struct nvgpu_vfe_invalidate { | ||
69 | bool state_change; | ||
70 | struct nvgpu_cond wq; | ||
71 | struct nvgpu_thread state_task; | ||
72 | }; | ||
73 | |||
68 | struct perf_pmupstate { | 74 | struct perf_pmupstate { |
69 | struct vfe_vars vfe_varobjs; | 75 | struct vfe_vars vfe_varobjs; |
70 | struct vfe_equs vfe_equobjs; | 76 | struct vfe_equs vfe_equobjs; |
71 | struct pstates pstatesobjs; | 77 | struct pstates pstatesobjs; |
72 | struct obj_volt volt; | 78 | struct obj_volt volt; |
73 | struct obj_lwpr lpwr; | 79 | struct obj_lwpr lpwr; |
80 | struct nvgpu_vfe_invalidate vfe_init; | ||
74 | }; | 81 | }; |
75 | 82 | ||
76 | u32 perf_pmu_vfe_load(struct gk20a *g); | 83 | u32 perf_pmu_vfe_load(struct gk20a *g); |
77 | u32 perf_pmu_vfe_load_gv10x(struct gk20a *g); | ||
78 | 84 | ||
79 | #endif | 85 | #endif |
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index 80f3edb6..0e7404cb 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c | |||
@@ -222,7 +222,7 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) | |||
222 | return err; | 222 | return err; |
223 | } | 223 | } |
224 | 224 | ||
225 | err = g->ops.pmu_ver.clk.perf_pmu_vfe_load(g); | 225 | err = g->ops.clk.perf_pmu_vfe_load(g); |
226 | if (err) { | 226 | if (err) { |
227 | return err; | 227 | return err; |
228 | } | 228 | } |