diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 398 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 79 |
2 files changed, 477 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index d12c5987..9d9dbb4b 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -192,6 +192,38 @@ static void set_pmu_cmdline_args_falctracedmaidx_v4( | |||
192 | pmu->args_v4.falc_trace_dma_idx = idx; | 192 | pmu->args_v4.falc_trace_dma_idx = idx; |
193 | } | 193 | } |
194 | 194 | ||
195 | static u32 pmu_cmdline_size_v5(struct pmu_gk20a *pmu) | ||
196 | { | ||
197 | return sizeof(struct pmu_cmdline_args_v5); | ||
198 | } | ||
199 | |||
200 | static void set_pmu_cmdline_args_cpufreq_v5(struct pmu_gk20a *pmu, u32 freq) | ||
201 | { | ||
202 | pmu->args_v5.cpu_freq_hz = 204000000; | ||
203 | } | ||
204 | static void set_pmu_cmdline_args_secure_mode_v5(struct pmu_gk20a *pmu, u32 val) | ||
205 | { | ||
206 | pmu->args_v5.secure_mode = val; | ||
207 | } | ||
208 | |||
209 | static void set_pmu_cmdline_args_falctracesize_v5( | ||
210 | struct pmu_gk20a *pmu, u32 size) | ||
211 | { | ||
212 | pmu->args_v5.trace_buf.params |= (size & 0x0FFF); | ||
213 | } | ||
214 | |||
215 | static void set_pmu_cmdline_args_falctracedmabase_v5(struct pmu_gk20a *pmu) | ||
216 | { | ||
217 | pmu->args_v5.trace_buf.address.lo = ((u32)pmu->trace_buf.gpu_va)/0x100; | ||
218 | pmu->args_v5.trace_buf.address.hi = 0; | ||
219 | } | ||
220 | |||
221 | static void set_pmu_cmdline_args_falctracedmaidx_v5( | ||
222 | struct pmu_gk20a *pmu, u32 idx) | ||
223 | { | ||
224 | pmu->args_v5.trace_buf.params |= (idx << 24); | ||
225 | } | ||
226 | |||
195 | static u32 pmu_cmdline_size_v3(struct pmu_gk20a *pmu) | 227 | static u32 pmu_cmdline_size_v3(struct pmu_gk20a *pmu) |
196 | { | 228 | { |
197 | return sizeof(struct pmu_cmdline_args_v3); | 229 | return sizeof(struct pmu_cmdline_args_v3); |
@@ -315,6 +347,10 @@ static void *get_pmu_cmdline_args_ptr_v2(struct pmu_gk20a *pmu) | |||
315 | return (void *)(&pmu->args_v2); | 347 | return (void *)(&pmu->args_v2); |
316 | } | 348 | } |
317 | 349 | ||
350 | static void *get_pmu_cmdline_args_ptr_v5(struct pmu_gk20a *pmu) | ||
351 | { | ||
352 | return (void *)(&pmu->args_v5); | ||
353 | } | ||
318 | static void *get_pmu_cmdline_args_ptr_v1(struct pmu_gk20a *pmu) | 354 | static void *get_pmu_cmdline_args_ptr_v1(struct pmu_gk20a *pmu) |
319 | { | 355 | { |
320 | return (void *)(&pmu->args_v1); | 356 | return (void *)(&pmu->args_v1); |
@@ -325,6 +361,11 @@ static void *get_pmu_cmdline_args_ptr_v0(struct pmu_gk20a *pmu) | |||
325 | return (void *)(&pmu->args_v0); | 361 | return (void *)(&pmu->args_v0); |
326 | } | 362 | } |
327 | 363 | ||
364 | static u32 get_pmu_allocation_size_v3(struct pmu_gk20a *pmu) | ||
365 | { | ||
366 | return sizeof(struct pmu_allocation_v3); | ||
367 | } | ||
368 | |||
328 | static u32 get_pmu_allocation_size_v2(struct pmu_gk20a *pmu) | 369 | static u32 get_pmu_allocation_size_v2(struct pmu_gk20a *pmu) |
329 | { | 370 | { |
330 | return sizeof(struct pmu_allocation_v2); | 371 | return sizeof(struct pmu_allocation_v2); |
@@ -340,6 +381,14 @@ static u32 get_pmu_allocation_size_v0(struct pmu_gk20a *pmu) | |||
340 | return sizeof(struct pmu_allocation_v0); | 381 | return sizeof(struct pmu_allocation_v0); |
341 | } | 382 | } |
342 | 383 | ||
384 | static void set_pmu_allocation_ptr_v3(struct pmu_gk20a *pmu, | ||
385 | void **pmu_alloc_ptr, void *assign_ptr) | ||
386 | { | ||
387 | struct pmu_allocation_v3 **pmu_a_ptr = | ||
388 | (struct pmu_allocation_v3 **)pmu_alloc_ptr; | ||
389 | *pmu_a_ptr = (struct pmu_allocation_v3 *)assign_ptr; | ||
390 | } | ||
391 | |||
343 | static void set_pmu_allocation_ptr_v2(struct pmu_gk20a *pmu, | 392 | static void set_pmu_allocation_ptr_v2(struct pmu_gk20a *pmu, |
344 | void **pmu_alloc_ptr, void *assign_ptr) | 393 | void **pmu_alloc_ptr, void *assign_ptr) |
345 | { | 394 | { |
@@ -364,6 +413,14 @@ static void set_pmu_allocation_ptr_v0(struct pmu_gk20a *pmu, | |||
364 | *pmu_a_ptr = (struct pmu_allocation_v0 *)assign_ptr; | 413 | *pmu_a_ptr = (struct pmu_allocation_v0 *)assign_ptr; |
365 | } | 414 | } |
366 | 415 | ||
416 | static void pmu_allocation_set_dmem_size_v3(struct pmu_gk20a *pmu, | ||
417 | void *pmu_alloc_ptr, u16 size) | ||
418 | { | ||
419 | struct pmu_allocation_v3 *pmu_a_ptr = | ||
420 | (struct pmu_allocation_v3 *)pmu_alloc_ptr; | ||
421 | pmu_a_ptr->alloc.dmem.size = size; | ||
422 | } | ||
423 | |||
367 | static void pmu_allocation_set_dmem_size_v2(struct pmu_gk20a *pmu, | 424 | static void pmu_allocation_set_dmem_size_v2(struct pmu_gk20a *pmu, |
368 | void *pmu_alloc_ptr, u16 size) | 425 | void *pmu_alloc_ptr, u16 size) |
369 | { | 426 | { |
@@ -388,6 +445,14 @@ static void pmu_allocation_set_dmem_size_v0(struct pmu_gk20a *pmu, | |||
388 | pmu_a_ptr->alloc.dmem.size = size; | 445 | pmu_a_ptr->alloc.dmem.size = size; |
389 | } | 446 | } |
390 | 447 | ||
448 | static u16 pmu_allocation_get_dmem_size_v3(struct pmu_gk20a *pmu, | ||
449 | void *pmu_alloc_ptr) | ||
450 | { | ||
451 | struct pmu_allocation_v3 *pmu_a_ptr = | ||
452 | (struct pmu_allocation_v3 *)pmu_alloc_ptr; | ||
453 | return pmu_a_ptr->alloc.dmem.size; | ||
454 | } | ||
455 | |||
391 | static u16 pmu_allocation_get_dmem_size_v2(struct pmu_gk20a *pmu, | 456 | static u16 pmu_allocation_get_dmem_size_v2(struct pmu_gk20a *pmu, |
392 | void *pmu_alloc_ptr) | 457 | void *pmu_alloc_ptr) |
393 | { | 458 | { |
@@ -412,6 +477,14 @@ static u16 pmu_allocation_get_dmem_size_v0(struct pmu_gk20a *pmu, | |||
412 | return pmu_a_ptr->alloc.dmem.size; | 477 | return pmu_a_ptr->alloc.dmem.size; |
413 | } | 478 | } |
414 | 479 | ||
480 | static u32 pmu_allocation_get_dmem_offset_v3(struct pmu_gk20a *pmu, | ||
481 | void *pmu_alloc_ptr) | ||
482 | { | ||
483 | struct pmu_allocation_v3 *pmu_a_ptr = | ||
484 | (struct pmu_allocation_v3 *)pmu_alloc_ptr; | ||
485 | return pmu_a_ptr->alloc.dmem.offset; | ||
486 | } | ||
487 | |||
415 | static u32 pmu_allocation_get_dmem_offset_v2(struct pmu_gk20a *pmu, | 488 | static u32 pmu_allocation_get_dmem_offset_v2(struct pmu_gk20a *pmu, |
416 | void *pmu_alloc_ptr) | 489 | void *pmu_alloc_ptr) |
417 | { | 490 | { |
@@ -436,6 +509,14 @@ static u32 pmu_allocation_get_dmem_offset_v0(struct pmu_gk20a *pmu, | |||
436 | return pmu_a_ptr->alloc.dmem.offset; | 509 | return pmu_a_ptr->alloc.dmem.offset; |
437 | } | 510 | } |
438 | 511 | ||
512 | static u32 *pmu_allocation_get_dmem_offset_addr_v3(struct pmu_gk20a *pmu, | ||
513 | void *pmu_alloc_ptr) | ||
514 | { | ||
515 | struct pmu_allocation_v3 *pmu_a_ptr = | ||
516 | (struct pmu_allocation_v3 *)pmu_alloc_ptr; | ||
517 | return &pmu_a_ptr->alloc.dmem.offset; | ||
518 | } | ||
519 | |||
439 | static u32 *pmu_allocation_get_dmem_offset_addr_v2(struct pmu_gk20a *pmu, | 520 | static u32 *pmu_allocation_get_dmem_offset_addr_v2(struct pmu_gk20a *pmu, |
440 | void *pmu_alloc_ptr) | 521 | void *pmu_alloc_ptr) |
441 | { | 522 | { |
@@ -460,6 +541,14 @@ static u32 *pmu_allocation_get_dmem_offset_addr_v0(struct pmu_gk20a *pmu, | |||
460 | return &pmu_a_ptr->alloc.dmem.offset; | 541 | return &pmu_a_ptr->alloc.dmem.offset; |
461 | } | 542 | } |
462 | 543 | ||
544 | static void pmu_allocation_set_dmem_offset_v3(struct pmu_gk20a *pmu, | ||
545 | void *pmu_alloc_ptr, u32 offset) | ||
546 | { | ||
547 | struct pmu_allocation_v3 *pmu_a_ptr = | ||
548 | (struct pmu_allocation_v3 *)pmu_alloc_ptr; | ||
549 | pmu_a_ptr->alloc.dmem.offset = offset; | ||
550 | } | ||
551 | |||
463 | static void pmu_allocation_set_dmem_offset_v2(struct pmu_gk20a *pmu, | 552 | static void pmu_allocation_set_dmem_offset_v2(struct pmu_gk20a *pmu, |
464 | void *pmu_alloc_ptr, u32 offset) | 553 | void *pmu_alloc_ptr, u32 offset) |
465 | { | 554 | { |
@@ -484,6 +573,25 @@ static void pmu_allocation_set_dmem_offset_v0(struct pmu_gk20a *pmu, | |||
484 | pmu_a_ptr->alloc.dmem.offset = offset; | 573 | pmu_a_ptr->alloc.dmem.offset = offset; |
485 | } | 574 | } |
486 | 575 | ||
576 | static void *get_pmu_msg_pmu_init_msg_ptr_v2(struct pmu_init_msg *init) | ||
577 | { | ||
578 | return (void *)(&(init->pmu_init_v2)); | ||
579 | } | ||
580 | |||
581 | static u16 get_pmu_init_msg_pmu_sw_mg_off_v2(union pmu_init_msg_pmu *init_msg) | ||
582 | { | ||
583 | struct pmu_init_msg_pmu_v2 *init = | ||
584 | (struct pmu_init_msg_pmu_v2 *)(&init_msg->v1); | ||
585 | return init->sw_managed_area_offset; | ||
586 | } | ||
587 | |||
588 | static u16 get_pmu_init_msg_pmu_sw_mg_size_v2(union pmu_init_msg_pmu *init_msg) | ||
589 | { | ||
590 | struct pmu_init_msg_pmu_v2 *init = | ||
591 | (struct pmu_init_msg_pmu_v2 *)(&init_msg->v1); | ||
592 | return init->sw_managed_area_size; | ||
593 | } | ||
594 | |||
487 | static void *get_pmu_msg_pmu_init_msg_ptr_v1(struct pmu_init_msg *init) | 595 | static void *get_pmu_msg_pmu_init_msg_ptr_v1(struct pmu_init_msg *init) |
488 | { | 596 | { |
489 | return (void *)(&(init->pmu_init_v1)); | 597 | return (void *)(&(init->pmu_init_v1)); |
@@ -522,6 +630,11 @@ static u16 get_pmu_init_msg_pmu_sw_mg_size_v0(union pmu_init_msg_pmu *init_msg) | |||
522 | return init->sw_managed_area_size; | 630 | return init->sw_managed_area_size; |
523 | } | 631 | } |
524 | 632 | ||
633 | static u32 get_pmu_perfmon_cmd_start_size_v3(void) | ||
634 | { | ||
635 | return sizeof(struct pmu_perfmon_cmd_start_v3); | ||
636 | } | ||
637 | |||
525 | static u32 get_pmu_perfmon_cmd_start_size_v2(void) | 638 | static u32 get_pmu_perfmon_cmd_start_size_v2(void) |
526 | { | 639 | { |
527 | return sizeof(struct pmu_perfmon_cmd_start_v2); | 640 | return sizeof(struct pmu_perfmon_cmd_start_v2); |
@@ -537,6 +650,20 @@ static u32 get_pmu_perfmon_cmd_start_size_v0(void) | |||
537 | return sizeof(struct pmu_perfmon_cmd_start_v0); | 650 | return sizeof(struct pmu_perfmon_cmd_start_v0); |
538 | } | 651 | } |
539 | 652 | ||
653 | static int get_perfmon_cmd_start_offsetofvar_v3( | ||
654 | enum pmu_perfmon_cmd_start_fields field) | ||
655 | { | ||
656 | switch (field) { | ||
657 | case COUNTER_ALLOC: | ||
658 | return offsetof(struct pmu_perfmon_cmd_start_v3, | ||
659 | counter_alloc); | ||
660 | default: | ||
661 | return -EINVAL; | ||
662 | } | ||
663 | |||
664 | return 0; | ||
665 | } | ||
666 | |||
540 | static int get_perfmon_cmd_start_offsetofvar_v2( | 667 | static int get_perfmon_cmd_start_offsetofvar_v2( |
541 | enum pmu_perfmon_cmd_start_fields field) | 668 | enum pmu_perfmon_cmd_start_fields field) |
542 | { | 669 | { |
@@ -579,6 +706,11 @@ static int get_perfmon_cmd_start_offsetofvar_v0( | |||
579 | return 0; | 706 | return 0; |
580 | } | 707 | } |
581 | 708 | ||
709 | static u32 get_pmu_perfmon_cmd_init_size_v3(void) | ||
710 | { | ||
711 | return sizeof(struct pmu_perfmon_cmd_init_v3); | ||
712 | } | ||
713 | |||
582 | static u32 get_pmu_perfmon_cmd_init_size_v2(void) | 714 | static u32 get_pmu_perfmon_cmd_init_size_v2(void) |
583 | { | 715 | { |
584 | return sizeof(struct pmu_perfmon_cmd_init_v2); | 716 | return sizeof(struct pmu_perfmon_cmd_init_v2); |
@@ -594,6 +726,19 @@ static u32 get_pmu_perfmon_cmd_init_size_v0(void) | |||
594 | return sizeof(struct pmu_perfmon_cmd_init_v0); | 726 | return sizeof(struct pmu_perfmon_cmd_init_v0); |
595 | } | 727 | } |
596 | 728 | ||
729 | static int get_perfmon_cmd_init_offsetofvar_v3( | ||
730 | enum pmu_perfmon_cmd_start_fields field) | ||
731 | { | ||
732 | switch (field) { | ||
733 | case COUNTER_ALLOC: | ||
734 | return offsetof(struct pmu_perfmon_cmd_init_v3, | ||
735 | counter_alloc); | ||
736 | default: | ||
737 | return -EINVAL; | ||
738 | } | ||
739 | return 0; | ||
740 | } | ||
741 | |||
597 | static int get_perfmon_cmd_init_offsetofvar_v2( | 742 | static int get_perfmon_cmd_init_offsetofvar_v2( |
598 | enum pmu_perfmon_cmd_start_fields field) | 743 | enum pmu_perfmon_cmd_start_fields field) |
599 | { | 744 | { |
@@ -636,6 +781,13 @@ static int get_perfmon_cmd_init_offsetofvar_v0( | |||
636 | return 0; | 781 | return 0; |
637 | } | 782 | } |
638 | 783 | ||
784 | static void perfmon_start_set_cmd_type_v3(struct pmu_perfmon_cmd *pc, u8 value) | ||
785 | { | ||
786 | struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; | ||
787 | |||
788 | start->cmd_type = value; | ||
789 | } | ||
790 | |||
639 | static void perfmon_start_set_cmd_type_v2(struct pmu_perfmon_cmd *pc, u8 value) | 791 | static void perfmon_start_set_cmd_type_v2(struct pmu_perfmon_cmd *pc, u8 value) |
640 | { | 792 | { |
641 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; | 793 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; |
@@ -654,6 +806,13 @@ static void perfmon_start_set_cmd_type_v0(struct pmu_perfmon_cmd *pc, u8 value) | |||
654 | start->cmd_type = value; | 806 | start->cmd_type = value; |
655 | } | 807 | } |
656 | 808 | ||
809 | static void perfmon_start_set_group_id_v3(struct pmu_perfmon_cmd *pc, u8 value) | ||
810 | { | ||
811 | struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; | ||
812 | |||
813 | start->group_id = value; | ||
814 | } | ||
815 | |||
657 | static void perfmon_start_set_group_id_v2(struct pmu_perfmon_cmd *pc, u8 value) | 816 | static void perfmon_start_set_group_id_v2(struct pmu_perfmon_cmd *pc, u8 value) |
658 | { | 817 | { |
659 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; | 818 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; |
@@ -672,6 +831,13 @@ static void perfmon_start_set_group_id_v0(struct pmu_perfmon_cmd *pc, u8 value) | |||
672 | start->group_id = value; | 831 | start->group_id = value; |
673 | } | 832 | } |
674 | 833 | ||
834 | static void perfmon_start_set_state_id_v3(struct pmu_perfmon_cmd *pc, u8 value) | ||
835 | { | ||
836 | struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; | ||
837 | |||
838 | start->state_id = value; | ||
839 | } | ||
840 | |||
675 | static void perfmon_start_set_state_id_v2(struct pmu_perfmon_cmd *pc, u8 value) | 841 | static void perfmon_start_set_state_id_v2(struct pmu_perfmon_cmd *pc, u8 value) |
676 | { | 842 | { |
677 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; | 843 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; |
@@ -690,6 +856,13 @@ static void perfmon_start_set_state_id_v0(struct pmu_perfmon_cmd *pc, u8 value) | |||
690 | start->state_id = value; | 856 | start->state_id = value; |
691 | } | 857 | } |
692 | 858 | ||
859 | static void perfmon_start_set_flags_v3(struct pmu_perfmon_cmd *pc, u8 value) | ||
860 | { | ||
861 | struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; | ||
862 | |||
863 | start->flags = value; | ||
864 | } | ||
865 | |||
693 | static void perfmon_start_set_flags_v2(struct pmu_perfmon_cmd *pc, u8 value) | 866 | static void perfmon_start_set_flags_v2(struct pmu_perfmon_cmd *pc, u8 value) |
694 | { | 867 | { |
695 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; | 868 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; |
@@ -708,6 +881,13 @@ static void perfmon_start_set_flags_v0(struct pmu_perfmon_cmd *pc, u8 value) | |||
708 | start->flags = value; | 881 | start->flags = value; |
709 | } | 882 | } |
710 | 883 | ||
884 | static u8 perfmon_start_get_flags_v3(struct pmu_perfmon_cmd *pc) | ||
885 | { | ||
886 | struct pmu_perfmon_cmd_start_v3 *start = &pc->start_v3; | ||
887 | |||
888 | return start->flags; | ||
889 | } | ||
890 | |||
711 | static u8 perfmon_start_get_flags_v2(struct pmu_perfmon_cmd *pc) | 891 | static u8 perfmon_start_get_flags_v2(struct pmu_perfmon_cmd *pc) |
712 | { | 892 | { |
713 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; | 893 | struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2; |
@@ -726,6 +906,14 @@ static u8 perfmon_start_get_flags_v0(struct pmu_perfmon_cmd *pc) | |||
726 | return start->flags; | 906 | return start->flags; |
727 | } | 907 | } |
728 | 908 | ||
909 | static void perfmon_cmd_init_set_sample_buffer_v3(struct pmu_perfmon_cmd *pc, | ||
910 | u16 value) | ||
911 | { | ||
912 | struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3; | ||
913 | |||
914 | init->sample_buffer = value; | ||
915 | } | ||
916 | |||
729 | static void perfmon_cmd_init_set_sample_buffer_v2(struct pmu_perfmon_cmd *pc, | 917 | static void perfmon_cmd_init_set_sample_buffer_v2(struct pmu_perfmon_cmd *pc, |
730 | u16 value) | 918 | u16 value) |
731 | { | 919 | { |
@@ -748,6 +936,14 @@ static void perfmon_cmd_init_set_sample_buffer_v0(struct pmu_perfmon_cmd *pc, | |||
748 | init->sample_buffer = value; | 936 | init->sample_buffer = value; |
749 | } | 937 | } |
750 | 938 | ||
939 | static void perfmon_cmd_init_set_dec_cnt_v3(struct pmu_perfmon_cmd *pc, | ||
940 | u8 value) | ||
941 | { | ||
942 | struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3; | ||
943 | |||
944 | init->to_decrease_count = value; | ||
945 | } | ||
946 | |||
751 | static void perfmon_cmd_init_set_dec_cnt_v2(struct pmu_perfmon_cmd *pc, | 947 | static void perfmon_cmd_init_set_dec_cnt_v2(struct pmu_perfmon_cmd *pc, |
752 | u8 value) | 948 | u8 value) |
753 | { | 949 | { |
@@ -769,6 +965,14 @@ static void perfmon_cmd_init_set_dec_cnt_v0(struct pmu_perfmon_cmd *pc, | |||
769 | init->to_decrease_count = value; | 965 | init->to_decrease_count = value; |
770 | } | 966 | } |
771 | 967 | ||
968 | static void perfmon_cmd_init_set_base_cnt_id_v3(struct pmu_perfmon_cmd *pc, | ||
969 | u8 value) | ||
970 | { | ||
971 | struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3; | ||
972 | |||
973 | init->base_counter_id = value; | ||
974 | } | ||
975 | |||
772 | static void perfmon_cmd_init_set_base_cnt_id_v2(struct pmu_perfmon_cmd *pc, | 976 | static void perfmon_cmd_init_set_base_cnt_id_v2(struct pmu_perfmon_cmd *pc, |
773 | u8 value) | 977 | u8 value) |
774 | { | 978 | { |
@@ -790,6 +994,14 @@ static void perfmon_cmd_init_set_base_cnt_id_v0(struct pmu_perfmon_cmd *pc, | |||
790 | init->base_counter_id = value; | 994 | init->base_counter_id = value; |
791 | } | 995 | } |
792 | 996 | ||
997 | static void perfmon_cmd_init_set_samp_period_us_v3(struct pmu_perfmon_cmd *pc, | ||
998 | u32 value) | ||
999 | { | ||
1000 | struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3; | ||
1001 | |||
1002 | init->sample_period_us = value; | ||
1003 | } | ||
1004 | |||
793 | static void perfmon_cmd_init_set_samp_period_us_v2(struct pmu_perfmon_cmd *pc, | 1005 | static void perfmon_cmd_init_set_samp_period_us_v2(struct pmu_perfmon_cmd *pc, |
794 | u32 value) | 1006 | u32 value) |
795 | { | 1007 | { |
@@ -811,6 +1023,14 @@ static void perfmon_cmd_init_set_samp_period_us_v0(struct pmu_perfmon_cmd *pc, | |||
811 | init->sample_period_us = value; | 1023 | init->sample_period_us = value; |
812 | } | 1024 | } |
813 | 1025 | ||
1026 | static void perfmon_cmd_init_set_num_cnt_v3(struct pmu_perfmon_cmd *pc, | ||
1027 | u8 value) | ||
1028 | { | ||
1029 | struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3; | ||
1030 | |||
1031 | init->num_counters = value; | ||
1032 | } | ||
1033 | |||
814 | static void perfmon_cmd_init_set_num_cnt_v2(struct pmu_perfmon_cmd *pc, | 1034 | static void perfmon_cmd_init_set_num_cnt_v2(struct pmu_perfmon_cmd *pc, |
815 | u8 value) | 1035 | u8 value) |
816 | { | 1036 | { |
@@ -832,6 +1052,14 @@ static void perfmon_cmd_init_set_num_cnt_v0(struct pmu_perfmon_cmd *pc, | |||
832 | init->num_counters = value; | 1052 | init->num_counters = value; |
833 | } | 1053 | } |
834 | 1054 | ||
1055 | static void perfmon_cmd_init_set_mov_avg_v3(struct pmu_perfmon_cmd *pc, | ||
1056 | u8 value) | ||
1057 | { | ||
1058 | struct pmu_perfmon_cmd_init_v3 *init = &pc->init_v3; | ||
1059 | |||
1060 | init->samples_in_moving_avg = value; | ||
1061 | } | ||
1062 | |||
835 | static void perfmon_cmd_init_set_mov_avg_v2(struct pmu_perfmon_cmd *pc, | 1063 | static void perfmon_cmd_init_set_mov_avg_v2(struct pmu_perfmon_cmd *pc, |
836 | u8 value) | 1064 | u8 value) |
837 | { | 1065 | { |
@@ -873,6 +1101,21 @@ static void get_pmu_init_msg_pmu_queue_params_v1(struct pmu_queue *queue, | |||
873 | queue->size = init->queue_info[id].size; | 1101 | queue->size = init->queue_info[id].size; |
874 | } | 1102 | } |
875 | 1103 | ||
1104 | static void get_pmu_init_msg_pmu_queue_params_v2(struct pmu_queue *queue, | ||
1105 | u32 id, void *pmu_init_msg) | ||
1106 | { | ||
1107 | struct pmu_init_msg_pmu_v2 *init = | ||
1108 | (struct pmu_init_msg_pmu_v2 *)pmu_init_msg; | ||
1109 | queue->index = init->queue_info[id].index; | ||
1110 | queue->offset = init->queue_info[id].offset; | ||
1111 | queue->size = init->queue_info[id].size; | ||
1112 | } | ||
1113 | |||
1114 | static void *get_pmu_sequence_in_alloc_ptr_v3(struct pmu_sequence *seq) | ||
1115 | { | ||
1116 | return (void *)(&seq->in_v3); | ||
1117 | } | ||
1118 | |||
876 | static void *get_pmu_sequence_in_alloc_ptr_v1(struct pmu_sequence *seq) | 1119 | static void *get_pmu_sequence_in_alloc_ptr_v1(struct pmu_sequence *seq) |
877 | { | 1120 | { |
878 | return (void *)(&seq->in_v1); | 1121 | return (void *)(&seq->in_v1); |
@@ -883,6 +1126,11 @@ static void *get_pmu_sequence_in_alloc_ptr_v0(struct pmu_sequence *seq) | |||
883 | return (void *)(&seq->in_v0); | 1126 | return (void *)(&seq->in_v0); |
884 | } | 1127 | } |
885 | 1128 | ||
1129 | static void *get_pmu_sequence_out_alloc_ptr_v3(struct pmu_sequence *seq) | ||
1130 | { | ||
1131 | return (void *)(&seq->out_v3); | ||
1132 | } | ||
1133 | |||
886 | static void *get_pmu_sequence_out_alloc_ptr_v1(struct pmu_sequence *seq) | 1134 | static void *get_pmu_sequence_out_alloc_ptr_v1(struct pmu_sequence *seq) |
887 | { | 1135 | { |
888 | return (void *)(&seq->out_v1); | 1136 | return (void *)(&seq->out_v1); |
@@ -903,6 +1151,11 @@ static u8 pg_cmd_eng_buf_load_size_v1(struct pmu_pg_cmd *pg) | |||
903 | return sizeof(pg->eng_buf_load_v1); | 1151 | return sizeof(pg->eng_buf_load_v1); |
904 | } | 1152 | } |
905 | 1153 | ||
1154 | static u8 pg_cmd_eng_buf_load_size_v2(struct pmu_pg_cmd *pg) | ||
1155 | { | ||
1156 | return sizeof(pg->eng_buf_load_v2); | ||
1157 | } | ||
1158 | |||
906 | static void pg_cmd_eng_buf_load_set_cmd_type_v0(struct pmu_pg_cmd *pg, | 1159 | static void pg_cmd_eng_buf_load_set_cmd_type_v0(struct pmu_pg_cmd *pg, |
907 | u8 value) | 1160 | u8 value) |
908 | { | 1161 | { |
@@ -914,6 +1167,13 @@ static void pg_cmd_eng_buf_load_set_cmd_type_v1(struct pmu_pg_cmd *pg, | |||
914 | { | 1167 | { |
915 | pg->eng_buf_load_v1.cmd_type = value; | 1168 | pg->eng_buf_load_v1.cmd_type = value; |
916 | } | 1169 | } |
1170 | |||
1171 | static void pg_cmd_eng_buf_load_set_cmd_type_v2(struct pmu_pg_cmd *pg, | ||
1172 | u8 value) | ||
1173 | { | ||
1174 | pg->eng_buf_load_v2.cmd_type = value; | ||
1175 | } | ||
1176 | |||
917 | static void pg_cmd_eng_buf_load_set_engine_id_v0(struct pmu_pg_cmd *pg, | 1177 | static void pg_cmd_eng_buf_load_set_engine_id_v0(struct pmu_pg_cmd *pg, |
918 | u8 value) | 1178 | u8 value) |
919 | { | 1179 | { |
@@ -924,6 +1184,11 @@ static void pg_cmd_eng_buf_load_set_engine_id_v1(struct pmu_pg_cmd *pg, | |||
924 | { | 1184 | { |
925 | pg->eng_buf_load_v1.engine_id = value; | 1185 | pg->eng_buf_load_v1.engine_id = value; |
926 | } | 1186 | } |
1187 | static void pg_cmd_eng_buf_load_set_engine_id_v2(struct pmu_pg_cmd *pg, | ||
1188 | u8 value) | ||
1189 | { | ||
1190 | pg->eng_buf_load_v2.engine_id = value; | ||
1191 | } | ||
927 | static void pg_cmd_eng_buf_load_set_buf_idx_v0(struct pmu_pg_cmd *pg, | 1192 | static void pg_cmd_eng_buf_load_set_buf_idx_v0(struct pmu_pg_cmd *pg, |
928 | u8 value) | 1193 | u8 value) |
929 | { | 1194 | { |
@@ -934,6 +1199,11 @@ static void pg_cmd_eng_buf_load_set_buf_idx_v1(struct pmu_pg_cmd *pg, | |||
934 | { | 1199 | { |
935 | pg->eng_buf_load_v1.buf_idx = value; | 1200 | pg->eng_buf_load_v1.buf_idx = value; |
936 | } | 1201 | } |
1202 | static void pg_cmd_eng_buf_load_set_buf_idx_v2(struct pmu_pg_cmd *pg, | ||
1203 | u8 value) | ||
1204 | { | ||
1205 | pg->eng_buf_load_v2.buf_idx = value; | ||
1206 | } | ||
937 | 1207 | ||
938 | static void pg_cmd_eng_buf_load_set_pad_v0(struct pmu_pg_cmd *pg, | 1208 | static void pg_cmd_eng_buf_load_set_pad_v0(struct pmu_pg_cmd *pg, |
939 | u8 value) | 1209 | u8 value) |
@@ -945,6 +1215,11 @@ static void pg_cmd_eng_buf_load_set_pad_v1(struct pmu_pg_cmd *pg, | |||
945 | { | 1215 | { |
946 | pg->eng_buf_load_v1.pad = value; | 1216 | pg->eng_buf_load_v1.pad = value; |
947 | } | 1217 | } |
1218 | static void pg_cmd_eng_buf_load_set_pad_v2(struct pmu_pg_cmd *pg, | ||
1219 | u8 value) | ||
1220 | { | ||
1221 | pg->eng_buf_load_v2.pad = value; | ||
1222 | } | ||
948 | 1223 | ||
949 | static void pg_cmd_eng_buf_load_set_buf_size_v0(struct pmu_pg_cmd *pg, | 1224 | static void pg_cmd_eng_buf_load_set_buf_size_v0(struct pmu_pg_cmd *pg, |
950 | u16 value) | 1225 | u16 value) |
@@ -956,6 +1231,11 @@ static void pg_cmd_eng_buf_load_set_buf_size_v1(struct pmu_pg_cmd *pg, | |||
956 | { | 1231 | { |
957 | pg->eng_buf_load_v1.dma_desc.dma_size = value; | 1232 | pg->eng_buf_load_v1.dma_desc.dma_size = value; |
958 | } | 1233 | } |
1234 | static void pg_cmd_eng_buf_load_set_buf_size_v2(struct pmu_pg_cmd *pg, | ||
1235 | u16 value) | ||
1236 | { | ||
1237 | pg->eng_buf_load_v2.dma_desc.params = value; | ||
1238 | } | ||
959 | 1239 | ||
960 | static void pg_cmd_eng_buf_load_set_dma_base_v0(struct pmu_pg_cmd *pg, | 1240 | static void pg_cmd_eng_buf_load_set_dma_base_v0(struct pmu_pg_cmd *pg, |
961 | u32 value) | 1241 | u32 value) |
@@ -968,6 +1248,12 @@ static void pg_cmd_eng_buf_load_set_dma_base_v1(struct pmu_pg_cmd *pg, | |||
968 | pg->eng_buf_load_v1.dma_desc.dma_addr.lo |= u64_lo32(value); | 1248 | pg->eng_buf_load_v1.dma_desc.dma_addr.lo |= u64_lo32(value); |
969 | pg->eng_buf_load_v1.dma_desc.dma_addr.hi |= u64_hi32(value); | 1249 | pg->eng_buf_load_v1.dma_desc.dma_addr.hi |= u64_hi32(value); |
970 | } | 1250 | } |
1251 | static void pg_cmd_eng_buf_load_set_dma_base_v2(struct pmu_pg_cmd *pg, | ||
1252 | u32 value) | ||
1253 | { | ||
1254 | pg->eng_buf_load_v2.dma_desc.address.lo = u64_lo32(value); | ||
1255 | pg->eng_buf_load_v2.dma_desc.address.hi = u64_lo32(value); | ||
1256 | } | ||
971 | 1257 | ||
972 | static void pg_cmd_eng_buf_load_set_dma_offset_v0(struct pmu_pg_cmd *pg, | 1258 | static void pg_cmd_eng_buf_load_set_dma_offset_v0(struct pmu_pg_cmd *pg, |
973 | u8 value) | 1259 | u8 value) |
@@ -979,6 +1265,12 @@ static void pg_cmd_eng_buf_load_set_dma_offset_v1(struct pmu_pg_cmd *pg, | |||
979 | { | 1265 | { |
980 | pg->eng_buf_load_v1.dma_desc.dma_addr.lo |= value; | 1266 | pg->eng_buf_load_v1.dma_desc.dma_addr.lo |= value; |
981 | } | 1267 | } |
1268 | static void pg_cmd_eng_buf_load_set_dma_offset_v2(struct pmu_pg_cmd *pg, | ||
1269 | u8 value) | ||
1270 | { | ||
1271 | pg->eng_buf_load_v2.dma_desc.address.lo |= u64_lo32(value); | ||
1272 | pg->eng_buf_load_v2.dma_desc.address.hi |= u64_lo32(value); | ||
1273 | } | ||
982 | 1274 | ||
983 | static void pg_cmd_eng_buf_load_set_dma_idx_v0(struct pmu_pg_cmd *pg, | 1275 | static void pg_cmd_eng_buf_load_set_dma_idx_v0(struct pmu_pg_cmd *pg, |
984 | u8 value) | 1276 | u8 value) |
@@ -990,6 +1282,11 @@ static void pg_cmd_eng_buf_load_set_dma_idx_v1(struct pmu_pg_cmd *pg, | |||
990 | { | 1282 | { |
991 | pg->eng_buf_load_v1.dma_desc.dma_idx = value; | 1283 | pg->eng_buf_load_v1.dma_desc.dma_idx = value; |
992 | } | 1284 | } |
1285 | static void pg_cmd_eng_buf_load_set_dma_idx_v2(struct pmu_pg_cmd *pg, | ||
1286 | u8 value) | ||
1287 | { | ||
1288 | pg->eng_buf_load_v2.dma_desc.params |= (value << 24); | ||
1289 | } | ||
993 | 1290 | ||
994 | 1291 | ||
995 | int gk20a_init_pmu(struct pmu_gk20a *pmu) | 1292 | int gk20a_init_pmu(struct pmu_gk20a *pmu) |
@@ -1107,6 +1404,107 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu) | |||
1107 | g->ops.pmu_ver.get_pmu_seq_out_a_ptr = | 1404 | g->ops.pmu_ver.get_pmu_seq_out_a_ptr = |
1108 | get_pmu_sequence_out_alloc_ptr_v1; | 1405 | get_pmu_sequence_out_alloc_ptr_v1; |
1109 | break; | 1406 | break; |
1407 | case APP_VERSION_GM206: | ||
1408 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = | ||
1409 | pg_cmd_eng_buf_load_size_v2; | ||
1410 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_cmd_type = | ||
1411 | pg_cmd_eng_buf_load_set_cmd_type_v2; | ||
1412 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_engine_id = | ||
1413 | pg_cmd_eng_buf_load_set_engine_id_v2; | ||
1414 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_idx = | ||
1415 | pg_cmd_eng_buf_load_set_buf_idx_v2; | ||
1416 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_pad = | ||
1417 | pg_cmd_eng_buf_load_set_pad_v2; | ||
1418 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_buf_size = | ||
1419 | pg_cmd_eng_buf_load_set_buf_size_v2; | ||
1420 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_base = | ||
1421 | pg_cmd_eng_buf_load_set_dma_base_v2; | ||
1422 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_offset = | ||
1423 | pg_cmd_eng_buf_load_set_dma_offset_v2; | ||
1424 | g->ops.pmu_ver.pg_cmd_eng_buf_load_set_dma_idx = | ||
1425 | pg_cmd_eng_buf_load_set_dma_idx_v2; | ||
1426 | g->ops.pmu_ver.get_perfmon_cntr_ptr = get_perfmon_cntr_ptr_v2; | ||
1427 | g->ops.pmu_ver.set_perfmon_cntr_ut = set_perfmon_cntr_ut_v2; | ||
1428 | g->ops.pmu_ver.set_perfmon_cntr_lt = set_perfmon_cntr_lt_v2; | ||
1429 | g->ops.pmu_ver.set_perfmon_cntr_valid = | ||
1430 | set_perfmon_cntr_valid_v2; | ||
1431 | g->ops.pmu_ver.set_perfmon_cntr_index = | ||
1432 | set_perfmon_cntr_index_v2; | ||
1433 | g->ops.pmu_ver.set_perfmon_cntr_group_id = | ||
1434 | set_perfmon_cntr_group_id_v2; | ||
1435 | g->ops.pmu_ver.get_perfmon_cntr_sz = pmu_perfmon_cntr_sz_v2; | ||
1436 | g->ops.pmu_ver.cmd_id_zbc_table_update = 16; | ||
1437 | g->ops.pmu_ver.get_pmu_cmdline_args_size = | ||
1438 | pmu_cmdline_size_v5; | ||
1439 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq = | ||
1440 | set_pmu_cmdline_args_cpufreq_v5; | ||
1441 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode = | ||
1442 | set_pmu_cmdline_args_secure_mode_v5; | ||
1443 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size = | ||
1444 | set_pmu_cmdline_args_falctracesize_v5; | ||
1445 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base = | ||
1446 | set_pmu_cmdline_args_falctracedmabase_v5; | ||
1447 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx = | ||
1448 | set_pmu_cmdline_args_falctracedmaidx_v5; | ||
1449 | g->ops.pmu_ver.get_pmu_cmdline_args_ptr = | ||
1450 | get_pmu_cmdline_args_ptr_v5; | ||
1451 | g->ops.pmu_ver.get_pmu_allocation_struct_size = | ||
1452 | get_pmu_allocation_size_v3; | ||
1453 | g->ops.pmu_ver.set_pmu_allocation_ptr = | ||
1454 | set_pmu_allocation_ptr_v3; | ||
1455 | g->ops.pmu_ver.pmu_allocation_set_dmem_size = | ||
1456 | pmu_allocation_set_dmem_size_v3; | ||
1457 | g->ops.pmu_ver.pmu_allocation_get_dmem_size = | ||
1458 | pmu_allocation_get_dmem_size_v3; | ||
1459 | g->ops.pmu_ver.pmu_allocation_get_dmem_offset = | ||
1460 | pmu_allocation_get_dmem_offset_v3; | ||
1461 | g->ops.pmu_ver.pmu_allocation_get_dmem_offset_addr = | ||
1462 | pmu_allocation_get_dmem_offset_addr_v3; | ||
1463 | g->ops.pmu_ver.pmu_allocation_set_dmem_offset = | ||
1464 | pmu_allocation_set_dmem_offset_v3; | ||
1465 | g->ops.pmu_ver.get_pmu_init_msg_pmu_queue_params = | ||
1466 | get_pmu_init_msg_pmu_queue_params_v2; | ||
1467 | g->ops.pmu_ver.get_pmu_msg_pmu_init_msg_ptr = | ||
1468 | get_pmu_msg_pmu_init_msg_ptr_v2; | ||
1469 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_off = | ||
1470 | get_pmu_init_msg_pmu_sw_mg_off_v2; | ||
1471 | g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size = | ||
1472 | get_pmu_init_msg_pmu_sw_mg_size_v2; | ||
1473 | g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size = | ||
1474 | get_pmu_perfmon_cmd_start_size_v3; | ||
1475 | g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar = | ||
1476 | get_perfmon_cmd_start_offsetofvar_v3; | ||
1477 | g->ops.pmu_ver.perfmon_start_set_cmd_type = | ||
1478 | perfmon_start_set_cmd_type_v3; | ||
1479 | g->ops.pmu_ver.perfmon_start_set_group_id = | ||
1480 | perfmon_start_set_group_id_v3; | ||
1481 | g->ops.pmu_ver.perfmon_start_set_state_id = | ||
1482 | perfmon_start_set_state_id_v3; | ||
1483 | g->ops.pmu_ver.perfmon_start_set_flags = | ||
1484 | perfmon_start_set_flags_v3; | ||
1485 | g->ops.pmu_ver.perfmon_start_get_flags = | ||
1486 | perfmon_start_get_flags_v3; | ||
1487 | g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size = | ||
1488 | get_pmu_perfmon_cmd_init_size_v3; | ||
1489 | g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar = | ||
1490 | get_perfmon_cmd_init_offsetofvar_v3; | ||
1491 | g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer = | ||
1492 | perfmon_cmd_init_set_sample_buffer_v3; | ||
1493 | g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt = | ||
1494 | perfmon_cmd_init_set_dec_cnt_v3; | ||
1495 | g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id = | ||
1496 | perfmon_cmd_init_set_base_cnt_id_v3; | ||
1497 | g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us = | ||
1498 | perfmon_cmd_init_set_samp_period_us_v3; | ||
1499 | g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt = | ||
1500 | perfmon_cmd_init_set_num_cnt_v3; | ||
1501 | g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg = | ||
1502 | perfmon_cmd_init_set_mov_avg_v3; | ||
1503 | g->ops.pmu_ver.get_pmu_seq_in_a_ptr = | ||
1504 | get_pmu_sequence_in_alloc_ptr_v3; | ||
1505 | g->ops.pmu_ver.get_pmu_seq_out_a_ptr = | ||
1506 | get_pmu_sequence_out_alloc_ptr_v3; | ||
1507 | break; | ||
1110 | case APP_VERSION_GM20B_5: | 1508 | case APP_VERSION_GM20B_5: |
1111 | case APP_VERSION_GM20B_4: | 1509 | case APP_VERSION_GM20B_4: |
1112 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = | 1510 | g->ops.pmu_ver.pg_cmd_eng_buf_load_size = |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index 7d91b111..8bf642d1 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -51,6 +51,7 @@ | |||
51 | 51 | ||
52 | #define APP_VERSION_NC_1 20313802 | 52 | #define APP_VERSION_NC_1 20313802 |
53 | #define APP_VERSION_NC_0 20360931 | 53 | #define APP_VERSION_NC_0 20360931 |
54 | #define APP_VERSION_GM206 20652057 | ||
54 | #define APP_VERSION_GM20B_5 20490253 | 55 | #define APP_VERSION_GM20B_5 20490253 |
55 | #define APP_VERSION_GM20B_4 19008461 | 56 | #define APP_VERSION_GM20B_4 19008461 |
56 | #define APP_VERSION_GM20B_3 18935575 | 57 | #define APP_VERSION_GM20B_3 18935575 |
@@ -383,6 +384,16 @@ struct pmu_cmdline_args_v1 { | |||
383 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ | 384 | struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */ |
384 | }; | 385 | }; |
385 | 386 | ||
387 | struct flcn_u64 { | ||
388 | u32 lo; | ||
389 | u32 hi; | ||
390 | }; | ||
391 | |||
392 | struct flcn_mem_desc_v0 { | ||
393 | struct flcn_u64 address; | ||
394 | u32 params; | ||
395 | }; | ||
396 | |||
386 | struct pmu_cmdline_args_v2 { | 397 | struct pmu_cmdline_args_v2 { |
387 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | 398 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ |
388 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ | 399 | u32 falc_trace_size; /* falctrace buffer size (bytes) */ |
@@ -419,6 +430,16 @@ struct pmu_cmdline_args_v4 { | |||
419 | u8 pad; | 430 | u8 pad; |
420 | }; | 431 | }; |
421 | 432 | ||
433 | struct pmu_cmdline_args_v5 { | ||
434 | u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ | ||
435 | struct flcn_mem_desc_v0 trace_buf; | ||
436 | u8 secure_mode; | ||
437 | u8 raise_priv_sec; | ||
438 | struct flcn_mem_desc_v0 gc6_ctx; | ||
439 | struct flcn_mem_desc_v0 init_data_dma_info; | ||
440 | u32 dummy; | ||
441 | }; | ||
442 | |||
422 | 443 | ||
423 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ | 444 | #define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ |
424 | #define GK20A_PMU_DMEM_BLKSIZE2 8 | 445 | #define GK20A_PMU_DMEM_BLKSIZE2 8 |
@@ -537,6 +558,13 @@ struct pmu_allocation_v2 { | |||
537 | } alloc; | 558 | } alloc; |
538 | }; | 559 | }; |
539 | 560 | ||
561 | struct pmu_allocation_v3 { | ||
562 | struct { | ||
563 | struct pmu_dmem dmem; | ||
564 | struct flcn_mem_desc_v0 fb; | ||
565 | } alloc; | ||
566 | }; | ||
567 | |||
540 | enum { | 568 | enum { |
541 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, | 569 | PMU_INIT_MSG_TYPE_PMU_INIT = 0, |
542 | }; | 570 | }; |
@@ -571,10 +599,27 @@ struct pmu_init_msg_pmu_v1 { | |||
571 | u16 sw_managed_area_offset; | 599 | u16 sw_managed_area_offset; |
572 | u16 sw_managed_area_size; | 600 | u16 sw_managed_area_size; |
573 | }; | 601 | }; |
602 | struct pmu_init_msg_pmu_v2 { | ||
603 | u8 msg_type; | ||
604 | u8 pad; | ||
605 | u16 os_debug_entry_point; | ||
606 | |||
607 | struct { | ||
608 | u16 size; | ||
609 | u16 offset; | ||
610 | u8 index; | ||
611 | u8 pad; | ||
612 | } queue_info[PMU_QUEUE_COUNT]; | ||
613 | |||
614 | u16 sw_managed_area_offset; | ||
615 | u16 sw_managed_area_size; | ||
616 | u8 dummy[18]; | ||
617 | }; | ||
574 | 618 | ||
575 | union pmu_init_msg_pmu { | 619 | union pmu_init_msg_pmu { |
576 | struct pmu_init_msg_pmu_v0 v0; | 620 | struct pmu_init_msg_pmu_v0 v0; |
577 | struct pmu_init_msg_pmu_v1 v1; | 621 | struct pmu_init_msg_pmu_v1 v1; |
622 | struct pmu_init_msg_pmu_v2 v2; | ||
578 | }; | 623 | }; |
579 | 624 | ||
580 | struct pmu_init_msg { | 625 | struct pmu_init_msg { |
@@ -582,6 +627,7 @@ struct pmu_init_msg { | |||
582 | u8 msg_type; | 627 | u8 msg_type; |
583 | struct pmu_init_msg_pmu_v1 pmu_init_v1; | 628 | struct pmu_init_msg_pmu_v1 pmu_init_v1; |
584 | struct pmu_init_msg_pmu_v0 pmu_init_v0; | 629 | struct pmu_init_msg_pmu_v0 pmu_init_v0; |
630 | struct pmu_init_msg_pmu_v2 pmu_init_v2; | ||
585 | }; | 631 | }; |
586 | }; | 632 | }; |
587 | 633 | ||
@@ -709,6 +755,14 @@ struct pmu_pg_cmd_eng_buf_load_v1 { | |||
709 | } dma_desc; | 755 | } dma_desc; |
710 | }; | 756 | }; |
711 | 757 | ||
758 | struct pmu_pg_cmd_eng_buf_load_v2 { | ||
759 | u8 cmd_type; | ||
760 | u8 engine_id; | ||
761 | u8 buf_idx; | ||
762 | u8 pad; | ||
763 | struct flcn_mem_desc_v0 dma_desc; | ||
764 | }; | ||
765 | |||
712 | enum { | 766 | enum { |
713 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, | 767 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, |
714 | }; | 768 | }; |
@@ -737,6 +791,7 @@ struct pmu_pg_cmd { | |||
737 | struct pmu_pg_cmd_elpg_cmd elpg_cmd; | 791 | struct pmu_pg_cmd_elpg_cmd elpg_cmd; |
738 | struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; | 792 | struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0; |
739 | struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; | 793 | struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1; |
794 | struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2; | ||
740 | struct pmu_pg_cmd_stat stat; | 795 | struct pmu_pg_cmd_stat stat; |
741 | struct pmu_pg_cmd_gr_init_param gr_init_param; | 796 | struct pmu_pg_cmd_gr_init_param gr_init_param; |
742 | /* TBD: other pg commands */ | 797 | /* TBD: other pg commands */ |
@@ -922,6 +977,14 @@ enum { | |||
922 | PMU_PERFMON_CMD_ID_INIT = 2 | 977 | PMU_PERFMON_CMD_ID_INIT = 2 |
923 | }; | 978 | }; |
924 | 979 | ||
980 | struct pmu_perfmon_cmd_start_v3 { | ||
981 | u8 cmd_type; | ||
982 | u8 group_id; | ||
983 | u8 state_id; | ||
984 | u8 flags; | ||
985 | struct pmu_allocation_v3 counter_alloc; | ||
986 | }; | ||
987 | |||
925 | struct pmu_perfmon_cmd_start_v2 { | 988 | struct pmu_perfmon_cmd_start_v2 { |
926 | u8 cmd_type; | 989 | u8 cmd_type; |
927 | u8 group_id; | 990 | u8 group_id; |
@@ -950,6 +1013,17 @@ struct pmu_perfmon_cmd_stop { | |||
950 | u8 cmd_type; | 1013 | u8 cmd_type; |
951 | }; | 1014 | }; |
952 | 1015 | ||
1016 | struct pmu_perfmon_cmd_init_v3 { | ||
1017 | u8 cmd_type; | ||
1018 | u8 to_decrease_count; | ||
1019 | u8 base_counter_id; | ||
1020 | u32 sample_period_us; | ||
1021 | struct pmu_allocation_v3 counter_alloc; | ||
1022 | u8 num_counters; | ||
1023 | u8 samples_in_moving_avg; | ||
1024 | u16 sample_buffer; | ||
1025 | }; | ||
1026 | |||
953 | struct pmu_perfmon_cmd_init_v2 { | 1027 | struct pmu_perfmon_cmd_init_v2 { |
954 | u8 cmd_type; | 1028 | u8 cmd_type; |
955 | u8 to_decrease_count; | 1029 | u8 to_decrease_count; |
@@ -989,10 +1063,12 @@ struct pmu_perfmon_cmd { | |||
989 | struct pmu_perfmon_cmd_start_v0 start_v0; | 1063 | struct pmu_perfmon_cmd_start_v0 start_v0; |
990 | struct pmu_perfmon_cmd_start_v1 start_v1; | 1064 | struct pmu_perfmon_cmd_start_v1 start_v1; |
991 | struct pmu_perfmon_cmd_start_v2 start_v2; | 1065 | struct pmu_perfmon_cmd_start_v2 start_v2; |
1066 | struct pmu_perfmon_cmd_start_v3 start_v3; | ||
992 | struct pmu_perfmon_cmd_stop stop; | 1067 | struct pmu_perfmon_cmd_stop stop; |
993 | struct pmu_perfmon_cmd_init_v0 init_v0; | 1068 | struct pmu_perfmon_cmd_init_v0 init_v0; |
994 | struct pmu_perfmon_cmd_init_v1 init_v1; | 1069 | struct pmu_perfmon_cmd_init_v1 init_v1; |
995 | struct pmu_perfmon_cmd_init_v2 init_v2; | 1070 | struct pmu_perfmon_cmd_init_v2 init_v2; |
1071 | struct pmu_perfmon_cmd_init_v3 init_v3; | ||
996 | }; | 1072 | }; |
997 | }; | 1073 | }; |
998 | 1074 | ||
@@ -1201,11 +1277,13 @@ struct pmu_sequence { | |||
1201 | struct pmu_allocation_v0 in_v0; | 1277 | struct pmu_allocation_v0 in_v0; |
1202 | struct pmu_allocation_v1 in_v1; | 1278 | struct pmu_allocation_v1 in_v1; |
1203 | struct pmu_allocation_v2 in_v2; | 1279 | struct pmu_allocation_v2 in_v2; |
1280 | struct pmu_allocation_v3 in_v3; | ||
1204 | }; | 1281 | }; |
1205 | union { | 1282 | union { |
1206 | struct pmu_allocation_v0 out_v0; | 1283 | struct pmu_allocation_v0 out_v0; |
1207 | struct pmu_allocation_v1 out_v1; | 1284 | struct pmu_allocation_v1 out_v1; |
1208 | struct pmu_allocation_v2 out_v2; | 1285 | struct pmu_allocation_v2 out_v2; |
1286 | struct pmu_allocation_v3 out_v3; | ||
1209 | }; | 1287 | }; |
1210 | u8 *out_payload; | 1288 | u8 *out_payload; |
1211 | pmu_callback callback; | 1289 | pmu_callback callback; |
@@ -1391,6 +1469,7 @@ struct pmu_gk20a { | |||
1391 | struct pmu_cmdline_args_v2 args_v2; | 1469 | struct pmu_cmdline_args_v2 args_v2; |
1392 | struct pmu_cmdline_args_v3 args_v3; | 1470 | struct pmu_cmdline_args_v3 args_v3; |
1393 | struct pmu_cmdline_args_v4 args_v4; | 1471 | struct pmu_cmdline_args_v4 args_v4; |
1472 | struct pmu_cmdline_args_v5 args_v5; | ||
1394 | }; | 1473 | }; |
1395 | unsigned long perfmon_events_cnt; | 1474 | unsigned long perfmon_events_cnt; |
1396 | bool perfmon_sampling_enabled; | 1475 | bool perfmon_sampling_enabled; |