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-rw-r--r--drivers/gpu/nvgpu/common/linux/module.c10
-rw-r--r--drivers/gpu/nvgpu/common/mm/vm.c6
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c6
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c11
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/vm.h6
6 files changed, 36 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/module.c b/drivers/gpu/nvgpu/common/linux/module.c
index ac64041e..52f987b2 100644
--- a/drivers/gpu/nvgpu/common/linux/module.c
+++ b/drivers/gpu/nvgpu/common/linux/module.c
@@ -25,6 +25,7 @@
25#include <linux/reset.h> 25#include <linux/reset.h>
26#include <linux/platform/tegra/common.h> 26#include <linux/platform/tegra/common.h>
27 27
28#include <nvgpu/dma.h>
28#include <nvgpu/kmem.h> 29#include <nvgpu/kmem.h>
29#include <nvgpu/nvgpu_common.h> 30#include <nvgpu/nvgpu_common.h>
30#include <nvgpu/soc.h> 31#include <nvgpu/soc.h>
@@ -1026,9 +1027,16 @@ int nvgpu_remove(struct device *dev, struct class *class)
1026 struct gk20a *g = get_gk20a(dev); 1027 struct gk20a *g = get_gk20a(dev);
1027 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g); 1028 struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
1028 struct gk20a_platform *platform = gk20a_get_platform(dev); 1029 struct gk20a_platform *platform = gk20a_get_platform(dev);
1030 int err;
1029 1031
1030 gk20a_dbg_fn(""); 1032 gk20a_dbg_fn("");
1031 1033
1034 err = nvgpu_quiesce(g);
1035 WARN(err, "gpu failed to idle during driver removal");
1036
1037 if (nvgpu_mem_is_valid(&g->syncpt_mem))
1038 nvgpu_dma_free(g, &g->syncpt_mem);
1039
1032 if (platform->has_cde) 1040 if (platform->has_cde)
1033 gk20a_cde_destroy(l); 1041 gk20a_cde_destroy(l);
1034 1042
@@ -1061,7 +1069,7 @@ int nvgpu_remove(struct device *dev, struct class *class)
1061 1069
1062 gk20a_dbg_fn("removed"); 1070 gk20a_dbg_fn("removed");
1063 1071
1064 return 0; 1072 return err;
1065} 1073}
1066 1074
1067static int __exit gk20a_remove(struct platform_device *pdev) 1075static int __exit gk20a_remove(struct platform_device *pdev)
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c
index 354d6ce4..f8d58349 100644
--- a/drivers/gpu/nvgpu/common/mm/vm.c
+++ b/drivers/gpu/nvgpu/common/mm/vm.c
@@ -527,6 +527,12 @@ static void __nvgpu_vm_remove(struct vm_gk20a *vm)
527 } 527 }
528 } 528 }
529 529
530#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
531 if (nvgpu_mem_is_valid(&g->syncpt_mem) && vm->syncpt_ro_map_gpu_va)
532 nvgpu_gmmu_unmap(vm, &g->syncpt_mem,
533 vm->syncpt_ro_map_gpu_va);
534#endif
535
530 nvgpu_mutex_acquire(&vm->update_gmmu_lock); 536 nvgpu_mutex_acquire(&vm->update_gmmu_lock);
531 537
532 nvgpu_rbtree_enum_start(0, &node, vm->mapped_buffers); 538 nvgpu_rbtree_enum_start(0, &node, vm->mapped_buffers);
diff --git a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
index 380ea048..d83684e4 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_sync_gk20a.c
@@ -76,9 +76,9 @@ static int gk20a_channel_syncpt_wait_syncpt(struct gk20a_channel_sync *s,
76 } 76 }
77 77
78 nvgpu_log(c->g, gpu_dbg_info, "sp->id %d gpu va %llx", 78 nvgpu_log(c->g, gpu_dbg_info, "sp->id %d gpu va %llx",
79 id, sp->syncpt_buf.gpu_va); 79 id, sp->c->vm->syncpt_ro_map_gpu_va);
80 c->g->ops.fifo.add_syncpt_wait_cmd(c->g, wait_cmd, 0, id, 80 c->g->ops.fifo.add_syncpt_wait_cmd(c->g, wait_cmd, 0, id,
81 thresh, sp->syncpt_buf.gpu_va); 81 thresh, c->vm->syncpt_ro_map_gpu_va);
82 82
83 return 0; 83 return 0;
84} 84}
@@ -147,7 +147,7 @@ static int gk20a_channel_syncpt_wait_fd(struct gk20a_channel_sync *s, int fd,
147 wait_id, sp->syncpt_buf.gpu_va); 147 wait_id, sp->syncpt_buf.gpu_va);
148 c->g->ops.fifo.add_syncpt_wait_cmd(c->g, wait_cmd, 148 c->g->ops.fifo.add_syncpt_wait_cmd(c->g, wait_cmd,
149 i * wait_cmd_size, wait_id, wait_value, 149 i * wait_cmd_size, wait_id, wait_value,
150 sp->syncpt_buf.gpu_va); 150 c->vm->syncpt_ro_map_gpu_va);
151 } 151 }
152 } 152 }
153 153
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index d1ad5992..cac62db7 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -154,6 +154,9 @@ int gk20a_finalize_poweron(struct gk20a *g)
154{ 154{
155 struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g)); 155 struct gk20a_platform *platform = gk20a_get_platform(dev_from_gk20a(g));
156 int err; 156 int err;
157#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
158 u32 nr_pages;
159#endif
157 160
158 gk20a_dbg_fn(""); 161 gk20a_dbg_fn("");
159 162
@@ -346,6 +349,14 @@ int gk20a_finalize_poweron(struct gk20a *g)
346 } 349 }
347 } 350 }
348 351
352#if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU)
353 if (gk20a_platform_has_syncpoints(g) && g->syncpt_unit_size) {
354 nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE);
355 __nvgpu_mem_create_from_phys(g, &g->syncpt_mem,
356 g->syncpt_unit_base, nr_pages);
357 }
358#endif
359
349done: 360done:
350 if (err) 361 if (err)
351 g->power_on = false; 362 g->power_on = false;
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 72e47ec6..a45a7b4e 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1293,6 +1293,7 @@ struct gk20a {
1293 size_t syncpt_unit_size; 1293 size_t syncpt_unit_size;
1294 u32 syncpt_size; 1294 u32 syncpt_size;
1295#endif 1295#endif
1296 struct nvgpu_mem syncpt_mem;
1296}; 1297};
1297 1298
1298static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g) 1299static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h
index 4c5d3232..f8868065 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h
@@ -175,6 +175,12 @@ struct vm_gk20a {
175 * Each address space needs to have a semaphore pool. 175 * Each address space needs to have a semaphore pool.
176 */ 176 */
177 struct nvgpu_semaphore_pool *sema_pool; 177 struct nvgpu_semaphore_pool *sema_pool;
178
179 /*
180 * Create sync point read only map for sync point range.
181 * Channels sharing same vm will also share same sync point ro map
182 */
183 u64 syncpt_ro_map_gpu_va;
178}; 184};
179 185
180void nvgpu_vm_get(struct vm_gk20a *vm); 186void nvgpu_vm_get(struct vm_gk20a *vm);