diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 47 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 5 |
2 files changed, 47 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index fca84116..ab736fbe 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -156,7 +156,8 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | |||
156 | cmd.cmd.acr.boot_falcons.flags = flags; | 156 | cmd.cmd.acr.boot_falcons.flags = flags; |
157 | cmd.cmd.acr.boot_falcons.falconidmask = | 157 | cmd.cmd.acr.boot_falcons.falconidmask = |
158 | falconidmask; | 158 | falconidmask; |
159 | cmd.cmd.acr.boot_falcons.usevamask = 0; | 159 | cmd.cmd.acr.boot_falcons.usevamask = |
160 | 1 << LSF_FALCON_ID_GPCCS; | ||
160 | cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = | 161 | cmd.cmd.acr.boot_falcons.wprvirtualbase.lo = |
161 | u64_lo32(g->pmu.wpr_buf.gpu_va); | 162 | u64_lo32(g->pmu.wpr_buf.gpu_va); |
162 | cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = | 163 | cmd.cmd.acr.boot_falcons.wprvirtualbase.hi = |
@@ -171,7 +172,7 @@ static void gp10b_pmu_load_multiple_falcons(struct gk20a *g, u32 falconidmask, | |||
171 | return; | 172 | return; |
172 | } | 173 | } |
173 | 174 | ||
174 | static int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | 175 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) |
175 | { | 176 | { |
176 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; | 177 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; |
177 | 178 | ||
@@ -221,7 +222,7 @@ static void pmu_handle_gr_param_msg(struct gk20a *g, struct pmu_msg *msg, | |||
221 | return; | 222 | return; |
222 | } | 223 | } |
223 | 224 | ||
224 | static int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) | 225 | int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask) |
225 | { | 226 | { |
226 | struct pmu_gk20a *pmu = &g->pmu; | 227 | struct pmu_gk20a *pmu = &g->pmu; |
227 | struct pmu_cmd cmd; | 228 | struct pmu_cmd cmd; |
@@ -280,7 +281,7 @@ static int gp10b_pmu_setup_elpg(struct gk20a *g) | |||
280 | return ret; | 281 | return ret; |
281 | } | 282 | } |
282 | 283 | ||
283 | static void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) | 284 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr) |
284 | { | 285 | { |
285 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), | 286 | gk20a_writel(g, pwr_falcon_dmatrfbase_r(), |
286 | addr); | 287 | addr); |
@@ -396,12 +397,50 @@ static int send_ecc_overide_en_dis_cmd(struct gk20a *g, u32 bitmask) | |||
396 | return status; | 397 | return status; |
397 | } | 398 | } |
398 | 399 | ||
400 | static bool gp10b_is_lazy_bootstrap(u32 falcon_id) | ||
401 | { | ||
402 | bool enable_status = false; | ||
403 | |||
404 | switch (falcon_id) { | ||
405 | case LSF_FALCON_ID_FECS: | ||
406 | enable_status = false; | ||
407 | break; | ||
408 | case LSF_FALCON_ID_GPCCS: | ||
409 | enable_status = true; | ||
410 | break; | ||
411 | default: | ||
412 | break; | ||
413 | } | ||
414 | |||
415 | return enable_status; | ||
416 | } | ||
417 | |||
418 | static bool gp10b_is_priv_load(u32 falcon_id) | ||
419 | { | ||
420 | bool enable_status = false; | ||
421 | |||
422 | switch (falcon_id) { | ||
423 | case LSF_FALCON_ID_FECS: | ||
424 | enable_status = false; | ||
425 | break; | ||
426 | case LSF_FALCON_ID_GPCCS: | ||
427 | enable_status = false; | ||
428 | break; | ||
429 | default: | ||
430 | break; | ||
431 | } | ||
432 | |||
433 | return enable_status; | ||
434 | } | ||
435 | |||
399 | void gp10b_init_pmu_ops(struct gpu_ops *gops) | 436 | void gp10b_init_pmu_ops(struct gpu_ops *gops) |
400 | { | 437 | { |
401 | if (gops->privsecurity) { | 438 | if (gops->privsecurity) { |
402 | gm20b_init_secure_pmu(gops); | 439 | gm20b_init_secure_pmu(gops); |
403 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 440 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
404 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 441 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |
442 | gops->pmu.is_lazy_bootstrap = gp10b_is_lazy_bootstrap; | ||
443 | gops->pmu.is_priv_load = gp10b_is_priv_load; | ||
405 | } else { | 444 | } else { |
406 | gk20a_init_pmu_ops(gops); | 445 | gk20a_init_pmu_ops(gops); |
407 | gops->pmu.load_lsfalcon_ucode = NULL; | 446 | gops->pmu.load_lsfalcon_ucode = NULL; |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h index f61f6a93..18e7bdd3 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B PMU | 2 | * GP10B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -17,5 +17,8 @@ | |||
17 | #define __PMU_GP10B_H_ | 17 | #define __PMU_GP10B_H_ |
18 | 18 | ||
19 | void gp10b_init_pmu_ops(struct gpu_ops *gops); | 19 | void gp10b_init_pmu_ops(struct gpu_ops *gops); |
20 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); | ||
21 | int gp10b_pg_gr_init(struct gk20a *g, u8 grfeaturemask); | ||
22 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); | ||
20 | 23 | ||
21 | #endif /*__PMU_GP10B_H_*/ | 24 | #endif /*__PMU_GP10B_H_*/ |