diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 27 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 9 |
6 files changed, 57 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index b813541a..de234972 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -297,6 +297,7 @@ struct gpu_ops { | |||
297 | int (*init_clk_support)(struct gk20a *g); | 297 | int (*init_clk_support)(struct gk20a *g); |
298 | int (*suspend_clk_support)(struct gk20a *g); | 298 | int (*suspend_clk_support)(struct gk20a *g); |
299 | } clk; | 299 | } clk; |
300 | bool privsecurity; | ||
300 | }; | 301 | }; |
301 | 302 | ||
302 | struct gk20a { | 303 | struct gk20a { |
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c index 1aae0304..8d1a29dd 100644 --- a/drivers/gpu/nvgpu/gk20a/hal.c +++ b/drivers/gpu/nvgpu/gk20a/hal.c | |||
@@ -26,7 +26,9 @@ int gpu_init_hal(struct gk20a *g) | |||
26 | gk20a_init_hal(&g->ops); | 26 | gk20a_init_hal(&g->ops); |
27 | break; | 27 | break; |
28 | case GK20A_GPUID_GM20B: | 28 | case GK20A_GPUID_GM20B: |
29 | gm20b_init_hal(&g->ops); | 29 | gk20a_dbg_info("gm20b detected"); |
30 | if (gm20b_init_hal(&g->ops)) | ||
31 | return -ENODEV; | ||
30 | break; | 32 | break; |
31 | default: | 33 | default: |
32 | gk20a_err(&g->dev->dev, "no support for %x", ver); | 34 | gk20a_err(&g->dev->dev, "no support for %x", ver); |
diff --git a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c index 3dae9450..1b8157f1 100644 --- a/drivers/gpu/nvgpu/gk20a/hal_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/hal_gk20a.c | |||
@@ -44,6 +44,7 @@ struct gpu_ops gk20a_ops = { | |||
44 | int gk20a_init_hal(struct gpu_ops *gops) | 44 | int gk20a_init_hal(struct gpu_ops *gops) |
45 | { | 45 | { |
46 | *gops = gk20a_ops; | 46 | *gops = gk20a_ops; |
47 | gops->privsecurity = 0; | ||
47 | gk20a_init_ltc(gops); | 48 | gk20a_init_ltc(gops); |
48 | gk20a_init_gr_ops(gops); | 49 | gk20a_init_gr_ops(gops); |
49 | gk20a_init_fb(gops); | 50 | gk20a_init_fb(gops); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c9c32b9f..7949405c 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -31,12 +31,11 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | |||
31 | 31 | ||
32 | gk20a_dbg_info("initialize gpc mmu"); | 32 | gk20a_dbg_info("initialize gpc mmu"); |
33 | 33 | ||
34 | #ifndef CONFIG_TEGRA_ACR | 34 | if (!g->ops.privsecurity) { |
35 | /* Bypass MMU check for non-secure boot. For | 35 | /* Bypass MMU check for non-secure boot. For |
36 | * secure-boot,this register write has no-effect */ | 36 | * secure-boot,this register write has no-effect */ |
37 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); | 37 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); |
38 | #endif | 38 | } |
39 | |||
40 | temp = gk20a_readl(g, fb_mmu_ctrl_r()); | 39 | temp = gk20a_readl(g, fb_mmu_ctrl_r()); |
41 | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | | 40 | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | |
42 | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | | 41 | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | |
@@ -722,6 +721,13 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
722 | 721 | ||
723 | return 0; | 722 | return 0; |
724 | } | 723 | } |
724 | #else | ||
725 | |||
726 | static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | ||
727 | { | ||
728 | return -EPERM; | ||
729 | } | ||
730 | |||
725 | #endif | 731 | #endif |
726 | 732 | ||
727 | void gm20b_init_gr(struct gpu_ops *gops) | 733 | void gm20b_init_gr(struct gpu_ops *gops) |
@@ -745,11 +751,10 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
745 | gops->gr.init_fs_state = gr_gm20b_ctx_state_floorsweep; | 751 | gops->gr.init_fs_state = gr_gm20b_ctx_state_floorsweep; |
746 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; | 752 | gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask; |
747 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; | 753 | gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments; |
748 | #ifdef CONFIG_TEGRA_ACR | 754 | if (gops->privsecurity) |
749 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; | 755 | gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode; |
750 | #else | 756 | else |
751 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; | 757 | gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode; |
752 | #endif | ||
753 | gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask; | 758 | gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask; |
754 | gops->gr.free_channel_ctx = gk20a_free_channel_ctx; | 759 | gops->gr.free_channel_ctx = gk20a_free_channel_ctx; |
755 | gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; | 760 | gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 5e8fc0ae..1dafc13d 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -27,6 +27,10 @@ | |||
27 | #include "mm_gm20b.h" | 27 | #include "mm_gm20b.h" |
28 | #include "pmu_gm20b.h" | 28 | #include "pmu_gm20b.h" |
29 | #include "clk_gm20b.h" | 29 | #include "clk_gm20b.h" |
30 | #include <linux/tegra-fuse.h> | ||
31 | |||
32 | #define FUSE_OPT_PRIV_SEC_DIS_0 0x264 | ||
33 | #define PRIV_SECURITY_DISABLE 0x01 | ||
30 | 34 | ||
31 | struct gpu_ops gm20b_ops = { | 35 | struct gpu_ops gm20b_ops = { |
32 | .clock_gating = { | 36 | .clock_gating = { |
@@ -46,6 +50,34 @@ struct gpu_ops gm20b_ops = { | |||
46 | int gm20b_init_hal(struct gpu_ops *gops) | 50 | int gm20b_init_hal(struct gpu_ops *gops) |
47 | { | 51 | { |
48 | *gops = gm20b_ops; | 52 | *gops = gm20b_ops; |
53 | #ifdef CONFIG_TEGRA_ACR | ||
54 | if (tegra_platform_is_linsim()) { | ||
55 | gops->privsecurity = 1; | ||
56 | } else { | ||
57 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) & | ||
58 | PRIV_SECURITY_DISABLE) { | ||
59 | gk20a_dbg_info("priv security is disabled in HW"); | ||
60 | gops->privsecurity = 0; | ||
61 | } else { | ||
62 | gops->privsecurity = 1; | ||
63 | } | ||
64 | } | ||
65 | #else | ||
66 | if (tegra_platform_is_linsim()) { | ||
67 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | ||
68 | gops->privsecurity = 0; | ||
69 | } else { | ||
70 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) & | ||
71 | PRIV_SECURITY_DISABLE) { | ||
72 | gops->privsecurity = 0; | ||
73 | } else { | ||
74 | gk20a_dbg_info("priv security is not supported but enabled"); | ||
75 | gops->privsecurity = 1; | ||
76 | return -EPERM; | ||
77 | } | ||
78 | } | ||
79 | #endif | ||
80 | |||
49 | gm20b_init_ltc(gops); | 81 | gm20b_init_ltc(gops); |
50 | gm20b_init_gr(gops); | 82 | gm20b_init_gr(gops); |
51 | gm20b_init_ltc(gops); | 83 | gm20b_init_ltc(gops); |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 04f9e02a..98dc6845 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -150,10 +150,9 @@ int gm20b_pmu_setup_elpg(struct gk20a *g) | |||
150 | 150 | ||
151 | void gm20b_init_pmu_ops(struct gpu_ops *gops) | 151 | void gm20b_init_pmu_ops(struct gpu_ops *gops) |
152 | { | 152 | { |
153 | #ifdef CONFIG_TEGRA_ACR | 153 | if (gops->privsecurity) |
154 | gm20b_init_secure_pmu(gops); | 154 | gm20b_init_secure_pmu(gops); |
155 | #else | 155 | else |
156 | gk20a_init_pmu_ops(gops); | 156 | gk20a_init_pmu_ops(gops); |
157 | #endif | ||
158 | gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg; | 157 | gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg; |
159 | } | 158 | } |