diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/acr_t18x.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 370 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/acr_gp106.h | 141 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mm_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h | 135 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | 239 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h | 82 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h | 76 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h (renamed from drivers/gpu/nvgpu/acr.h) | 65 |
14 files changed, 597 insertions, 548 deletions
diff --git a/drivers/gpu/nvgpu/acr_t18x.h b/drivers/gpu/nvgpu/acr_t18x.h deleted file mode 100644 index 1e48d5ca..00000000 --- a/drivers/gpu/nvgpu/acr_t18x.h +++ /dev/null | |||
@@ -1,20 +0,0 @@ | |||
1 | /* | ||
2 | * NVIDIA T18x ACR | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | #ifndef _NVGPU_ACR_T18X_H_ | ||
16 | #define _NVGPU_ACR_T18X_H_ | ||
17 | |||
18 | #include "gp106/acr_gp106.h" | ||
19 | |||
20 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index acc3b975..51569fb7 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -38,6 +38,8 @@ struct acr_desc; | |||
38 | 38 | ||
39 | #include "../../../arch/arm/mach-tegra/iomap.h" | 39 | #include "../../../arch/arm/mach-tegra/iomap.h" |
40 | 40 | ||
41 | #include <nvgpu/acr/nvgpu_acr.h> | ||
42 | |||
41 | #include "as_gk20a.h" | 43 | #include "as_gk20a.h" |
42 | #include "clk_gk20a.h" | 44 | #include "clk_gk20a.h" |
43 | #include "ce2_gk20a.h" | 45 | #include "ce2_gk20a.h" |
@@ -50,7 +52,6 @@ struct acr_desc; | |||
50 | #include "therm_gk20a.h" | 52 | #include "therm_gk20a.h" |
51 | #include "platform_gk20a.h" | 53 | #include "platform_gk20a.h" |
52 | #include "gm20b/acr_gm20b.h" | 54 | #include "gm20b/acr_gm20b.h" |
53 | #include "acr.h" | ||
54 | #include "cde_gk20a.h" | 55 | #include "cde_gk20a.h" |
55 | #include "debug_gk20a.h" | 56 | #include "debug_gk20a.h" |
56 | #include "sched_gk20a.h" | 57 | #include "sched_gk20a.h" |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index c1cefc29..db3974bb 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -23,9 +23,12 @@ | |||
23 | 23 | ||
24 | #include <nvgpu/timers.h> | 24 | #include <nvgpu/timers.h> |
25 | #include <nvgpu/nvgpu_common.h> | 25 | #include <nvgpu/nvgpu_common.h> |
26 | #include <nvgpu/acr/nvgpu_acr.h> | ||
26 | 27 | ||
27 | #include "gk20a/gk20a.h" | 28 | #include "gk20a/gk20a.h" |
28 | #include "gk20a/pmu_gk20a.h" | 29 | #include "gk20a/pmu_gk20a.h" |
30 | #include "mm_gm20b.h" | ||
31 | #include "acr_gm20b.h" | ||
29 | 32 | ||
30 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> | 33 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> |
31 | 34 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index fb61e366..84478611 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B ACR | 2 | * GM20B ACR |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -15,15 +15,6 @@ | |||
15 | 15 | ||
16 | #ifndef __ACR_GM20B_H_ | 16 | #ifndef __ACR_GM20B_H_ |
17 | #define __ACR_GM20B_H_ | 17 | #define __ACR_GM20B_H_ |
18 | #include "gk20a/gk20a.h" | ||
19 | #include "mm_gm20b.h" | ||
20 | |||
21 | /*Defines*/ | ||
22 | #define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */ | ||
23 | |||
24 | /*chip specific defines*/ | ||
25 | #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ | ||
26 | #define LSF_UCODE_DATA_ALIGNMENT 4096 | ||
27 | 18 | ||
28 | #define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin" | 19 | #define GM20B_PMU_UCODE_IMAGE "gpmu_ucode_image.bin" |
29 | #define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin" | 20 | #define GM20B_PMU_UCODE_DESC "gpmu_ucode_desc.bin" |
@@ -33,365 +24,6 @@ | |||
33 | #define GM20B_FECS_UCODE_SIG "fecs_sig.bin" | 24 | #define GM20B_FECS_UCODE_SIG "fecs_sig.bin" |
34 | #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin" | 25 | #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin" |
35 | 26 | ||
36 | #define LSFM_DISABLE_MASK_NONE (0x00000000) /*Disable all LS falcons*/ | ||
37 | #define LSFM_DISABLE_MASK_ALL (0xFFFFFFFF) /*Enable all LS falcons*/ | ||
38 | |||
39 | #define PMU_SECURE_MODE (0x1) | ||
40 | #define PMU_LSFM_MANAGED (0x2) | ||
41 | |||
42 | /*ACR load related*/ | ||
43 | /*! | ||
44 | * Supporting maximum of 2 regions. | ||
45 | * This is needed to pre-allocate space in DMEM | ||
46 | */ | ||
47 | #define T210_FLCN_ACR_MAX_REGIONS (2) | ||
48 | #define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) | ||
49 | |||
50 | /*! | ||
51 | * Falcon Id Defines | ||
52 | * Defines a common Light Secure Falcon identifier. | ||
53 | */ | ||
54 | #define LSF_FALCON_ID_PMU (0) | ||
55 | #define LSF_FALCON_ID_RESERVED (1) | ||
56 | #define LSF_FALCON_ID_FECS (2) | ||
57 | #define LSF_FALCON_ID_GPCCS (3) | ||
58 | #define LSF_FALCON_ID_END (11) | ||
59 | #define LSF_FALCON_ID_INVALID (0xFFFFFFFF) | ||
60 | |||
61 | /*! | ||
62 | * Bootstrap Owner Defines | ||
63 | */ | ||
64 | #define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU) | ||
65 | |||
66 | /*! | ||
67 | * Image Status Defines | ||
68 | */ | ||
69 | #define LSF_IMAGE_STATUS_NONE (0) | ||
70 | #define LSF_IMAGE_STATUS_COPY (1) | ||
71 | #define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2) | ||
72 | #define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3) | ||
73 | #define LSF_IMAGE_STATUS_VALIDATION_DONE (4) | ||
74 | #define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5) | ||
75 | #define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6) | ||
76 | |||
77 | /*LSB header related defines*/ | ||
78 | #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 | ||
79 | #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 | ||
80 | #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 | ||
81 | #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4 | ||
82 | #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8 | ||
83 | #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0 | ||
84 | |||
85 | /*! | ||
86 | * Light Secure WPR Content Alignments | ||
87 | */ | ||
88 | #define LSF_LSB_HEADER_ALIGNMENT 256 | ||
89 | #define LSF_BL_DATA_ALIGNMENT 256 | ||
90 | #define LSF_BL_DATA_SIZE_ALIGNMENT 256 | ||
91 | #define LSF_BL_CODE_SIZE_ALIGNMENT 256 | ||
92 | |||
93 | /*! | ||
94 | * Falcon UCODE header index. | ||
95 | */ | ||
96 | #define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0) | ||
97 | #define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1) | ||
98 | #define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2) | ||
99 | #define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3) | ||
100 | #define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4) | ||
101 | /*! | ||
102 | * There are total N number of Apps with code and offset defined in UCODE header | ||
103 | * This macro provides the CODE and DATA offset and size of Ath application. | ||
104 | */ | ||
105 | #define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5) | ||
106 | #define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \ | ||
107 | (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2)) | ||
108 | #define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \ | ||
109 | (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1) | ||
110 | #define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \ | ||
111 | (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1) | ||
112 | |||
113 | #define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \ | ||
114 | (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1) | ||
115 | #define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \ | ||
116 | (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2)) | ||
117 | #define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \ | ||
118 | (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1) | ||
119 | #define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \ | ||
120 | (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1) | ||
121 | |||
122 | #define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \ | ||
123 | (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1) | ||
124 | #define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ | ||
125 | (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2) | ||
126 | |||
127 | enum acr_capabilities { | ||
128 | ACR_LRF_TEX_LTC_DRAM_PRIV_MASK_ENABLE_LS_OVERRIDE = (0x00000001), | ||
129 | }; | ||
130 | |||
131 | /*Externs*/ | ||
132 | |||
133 | /*Structs*/ | ||
134 | |||
135 | /*! | ||
136 | * Light Secure Falcon Ucode Description Defines | ||
137 | * This stucture is prelim and may change as the ucode signing flow evolves. | ||
138 | */ | ||
139 | struct lsf_ucode_desc { | ||
140 | u8 prd_keys[2][16]; | ||
141 | u8 dbg_keys[2][16]; | ||
142 | u32 b_prd_present; | ||
143 | u32 b_dbg_present; | ||
144 | u32 falcon_id; | ||
145 | }; | ||
146 | |||
147 | /*! | ||
148 | * Light Secure WPR Header | ||
149 | * Defines state allowing Light Secure Falcon bootstrapping. | ||
150 | * | ||
151 | * falcon_id - LS falcon ID | ||
152 | * lsb_offset - Offset into WPR region holding LSB header | ||
153 | * bootstrap_owner - Bootstrap OWNER (either PMU or SEC2) | ||
154 | * lazy_bootstrap - Skip bootstrapping by ACR | ||
155 | * status - Bootstrapping status | ||
156 | */ | ||
157 | struct lsf_wpr_header { | ||
158 | u32 falcon_id; | ||
159 | u32 lsb_offset; | ||
160 | u32 bootstrap_owner; | ||
161 | u32 lazy_bootstrap; | ||
162 | u32 status; | ||
163 | }; | ||
164 | |||
165 | struct lsf_lsb_header { | ||
166 | struct lsf_ucode_desc signature; | ||
167 | u32 ucode_off; | ||
168 | u32 ucode_size; | ||
169 | u32 data_size; | ||
170 | u32 bl_code_size; | ||
171 | u32 bl_imem_off; | ||
172 | u32 bl_data_off; | ||
173 | u32 bl_data_size; | ||
174 | u32 app_code_off; | ||
175 | u32 app_code_size; | ||
176 | u32 app_data_off; | ||
177 | u32 app_data_size; | ||
178 | u32 flags; | ||
179 | }; | ||
180 | |||
181 | /*! | ||
182 | * Structure used by the boot-loader to load the rest of the code. This has | ||
183 | * to be filled by host and copied into DMEM at offset provided in the | ||
184 | * hsflcn_bl_desc.bl_desc_dmem_load_off. | ||
185 | * | ||
186 | * signature - 16B signature for secure code. 0s if no secure code | ||
187 | * ctx_dma - CtxDma to be used by BL while loading code/data | ||
188 | * code_dma_base - 256B aligned Physical FB Address where code is located | ||
189 | * non_sec_code_off - Offset from code_dma_base where the nonSecure code is | ||
190 | * located. The offset must be multiple of 256 to help perf | ||
191 | * non_sec_code_size - The size of the nonSecure code part. | ||
192 | * sec_code_size - Offset from code_dma_base where the secure code is | ||
193 | * located. The offset must be multiple of 256 to help perf | ||
194 | * code_entry_point - Code entry point which will be invoked by BL after | ||
195 | * code is loaded. | ||
196 | * data_dma_base - 256B aligned Physical FB Address where data is located. | ||
197 | * data_size - Size of data block. Should be multiple of 256B | ||
198 | */ | ||
199 | struct flcn_bl_dmem_desc { | ||
200 | u32 reserved[4]; /*Should be the first element..*/ | ||
201 | u32 signature[4]; /*Should be the first element..*/ | ||
202 | u32 ctx_dma; | ||
203 | u32 code_dma_base; | ||
204 | u32 non_sec_code_off; | ||
205 | u32 non_sec_code_size; | ||
206 | u32 sec_code_off; | ||
207 | u32 sec_code_size; | ||
208 | u32 code_entry_point; | ||
209 | u32 data_dma_base; | ||
210 | u32 data_size; | ||
211 | u32 code_dma_base1; | ||
212 | u32 data_dma_base1; | ||
213 | }; | ||
214 | |||
215 | /*! | ||
216 | * Legacy structure used by the current PMU/DPU bootloader. | ||
217 | */ | ||
218 | struct loader_config { | ||
219 | u32 dma_idx; | ||
220 | u32 code_dma_base; /*<! upper 32-bits of 40-bit dma address*/ | ||
221 | u32 code_size_total; | ||
222 | u32 code_size_to_load; | ||
223 | u32 code_entry_point; | ||
224 | u32 data_dma_base; /*<! upper 32-bits of 40-bit dma address*/ | ||
225 | u32 data_size; /*<! initialized data of the application */ | ||
226 | u32 overlay_dma_base; /*<! upper 32-bits of the 40-bit dma address*/ | ||
227 | u32 argc; | ||
228 | u32 argv; | ||
229 | u16 code_dma_base1; /*<! upper 7 bits of 47-bit dma address*/ | ||
230 | u16 data_dma_base1; /*<! upper 7 bits of 47-bit dma address*/ | ||
231 | u16 overlay_dma_base1; /*<! upper 7 bits of the 47-bit dma address*/ | ||
232 | }; | ||
233 | |||
234 | /*! | ||
235 | * Union of all supported structures used by bootloaders. | ||
236 | */ | ||
237 | union flcn_bl_generic_desc { | ||
238 | struct flcn_bl_dmem_desc bl_dmem_desc; | ||
239 | struct loader_config loader_cfg; | ||
240 | }; | ||
241 | |||
242 | struct flcn_ucode_img { | ||
243 | u32 *header; /*only some falcons have header*/ | ||
244 | u32 *data; | ||
245 | struct pmu_ucode_desc *desc; /*only some falcons have descriptor*/ | ||
246 | u32 data_size; | ||
247 | void *fw_ver; /*NV2080_CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct*/ | ||
248 | u8 load_entire_os_data; /* load the whole osData section at boot time.*/ | ||
249 | struct lsf_ucode_desc *lsf_desc; /* NULL if not a light secure falcon.*/ | ||
250 | u8 free_res_allocs;/*True if there a resources to freed by the client.*/ | ||
251 | u32 flcn_inst; | ||
252 | }; | ||
253 | |||
254 | /*! | ||
255 | * LSFM Managed Ucode Image | ||
256 | * next : Next image the list, NULL if last. | ||
257 | * wpr_header : WPR header for this ucode image | ||
258 | * lsb_header : LSB header for this ucode image | ||
259 | * bl_gen_desc : Bootloader generic desc structure for this ucode image | ||
260 | * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image | ||
261 | * full_ucode_size : Surface size required for final ucode image | ||
262 | * ucode_img : Ucode image info | ||
263 | */ | ||
264 | struct lsfm_managed_ucode_img { | ||
265 | struct lsfm_managed_ucode_img *next; | ||
266 | struct lsf_wpr_header wpr_header; | ||
267 | struct lsf_lsb_header lsb_header; | ||
268 | union flcn_bl_generic_desc bl_gen_desc; | ||
269 | u32 bl_gen_desc_size; | ||
270 | u32 full_ucode_size; | ||
271 | struct flcn_ucode_img ucode_img; | ||
272 | }; | ||
273 | |||
274 | struct ls_flcn_mgr { | ||
275 | u16 managed_flcn_cnt; | ||
276 | u32 wpr_size; | ||
277 | u32 disable_mask; | ||
278 | struct lsfm_managed_ucode_img *ucode_img_list; | ||
279 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | ||
280 | }; | ||
281 | |||
282 | /*ACR related structs*/ | ||
283 | /*! | ||
284 | * start_addr - Starting address of region | ||
285 | * end_addr - Ending address of region | ||
286 | * region_id - Region ID | ||
287 | * read_mask - Read Mask | ||
288 | * write_mask - WriteMask | ||
289 | * client_mask - Bit map of all clients currently using this region | ||
290 | */ | ||
291 | struct flcn_acr_region_prop { | ||
292 | u32 start_addr; | ||
293 | u32 end_addr; | ||
294 | u32 region_id; | ||
295 | u32 read_mask; | ||
296 | u32 write_mask; | ||
297 | u32 client_mask; | ||
298 | }; | ||
299 | |||
300 | /*! | ||
301 | * no_regions - Number of regions used. | ||
302 | * region_props - Region properties | ||
303 | */ | ||
304 | struct flcn_acr_regions { | ||
305 | u32 no_regions; | ||
306 | struct flcn_acr_region_prop region_props[T210_FLCN_ACR_MAX_REGIONS]; | ||
307 | }; | ||
308 | |||
309 | /*! | ||
310 | * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons, | ||
311 | * and need to switch into LS mode, it needs to have its own | ||
312 | * actual DMEM image copied into DMEM as part of LS setup. If | ||
313 | * ACR desc is at location 0, it will definitely get overwritten | ||
314 | * causing data corruption. Hence we are reserving 0x200 bytes | ||
315 | * to give room for any loading data. NOTE: This has to be the | ||
316 | * first member always | ||
317 | * signature - Signature of ACR ucode. | ||
318 | * wpr_region_id - Region ID holding the WPR header and its details | ||
319 | * wpr_offset - Offset from the WPR region holding the wpr header | ||
320 | * regions - Region descriptors | ||
321 | * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob | ||
322 | * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob | ||
323 | */ | ||
324 | struct flcn_acr_desc { | ||
325 | union { | ||
326 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | ||
327 | u32 signatures[4]; | ||
328 | } ucode_reserved_space; | ||
329 | /*Always 1st*/ | ||
330 | u32 wpr_region_id; | ||
331 | u32 wpr_offset; | ||
332 | u32 mmu_mem_range; | ||
333 | struct flcn_acr_regions regions; | ||
334 | u32 nonwpr_ucode_blob_size; | ||
335 | u64 nonwpr_ucode_blob_start; | ||
336 | }; | ||
337 | |||
338 | /*! | ||
339 | * The header used by RM to figure out code and data sections of bootloader. | ||
340 | * | ||
341 | * bl_code_off - Offset of code section in the image | ||
342 | * bl_code_size - Size of code section in the image | ||
343 | * bl_data_off - Offset of data section in the image | ||
344 | * bl_data_size - Size of data section in the image | ||
345 | */ | ||
346 | struct hsflcn_bl_img_hdr { | ||
347 | u32 bl_code_off; | ||
348 | u32 bl_code_size; | ||
349 | u32 bl_data_off; | ||
350 | u32 bl_data_size; | ||
351 | }; | ||
352 | |||
353 | /*! | ||
354 | * The descriptor used by RM to figure out the requirements of boot loader. | ||
355 | * | ||
356 | * bl_start_tag - Starting tag of bootloader | ||
357 | * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc | ||
358 | to be loaded | ||
359 | * bl_img_hdr - Description of the image | ||
360 | */ | ||
361 | struct hsflcn_bl_desc { | ||
362 | u32 bl_start_tag; | ||
363 | u32 bl_desc_dmem_load_off; | ||
364 | struct hsflcn_bl_img_hdr bl_img_hdr; | ||
365 | }; | ||
366 | |||
367 | struct bin_hdr { | ||
368 | u32 bin_magic; /* 0x10de */ | ||
369 | u32 bin_ver; /* versioning of bin format */ | ||
370 | u32 bin_size; /* entire image size including this header */ | ||
371 | u32 header_offset; /* Header offset of executable binary metadata, | ||
372 | start @ offset- 0x100 */ | ||
373 | u32 data_offset; /* Start of executable binary data, start @ | ||
374 | offset- 0x200 */ | ||
375 | u32 data_size; /* Size ofexecutable binary */ | ||
376 | }; | ||
377 | |||
378 | struct acr_fw_header { | ||
379 | u32 sig_dbg_offset; | ||
380 | u32 sig_dbg_size; | ||
381 | u32 sig_prod_offset; | ||
382 | u32 sig_prod_size; | ||
383 | u32 patch_loc; | ||
384 | u32 patch_sig; | ||
385 | u32 hdr_offset; /*this header points to acr_ucode_header_t210_load*/ | ||
386 | u32 hdr_size; /*size of above header*/ | ||
387 | }; | ||
388 | |||
389 | struct wpr_carveout_info { | ||
390 | u64 wpr_base; | ||
391 | u64 nonwpr_base; | ||
392 | u64 size; | ||
393 | }; | ||
394 | |||
395 | void gm20b_init_secure_pmu(struct gpu_ops *gops); | 27 | void gm20b_init_secure_pmu(struct gpu_ops *gops); |
396 | int prepare_ucode_blob(struct gk20a *g); | 28 | int prepare_ucode_blob(struct gk20a *g); |
397 | int gm20b_pmu_setup_sw(struct gk20a *g); | 29 | int gm20b_pmu_setup_sw(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 9cf644fd..44a0116b 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -27,7 +27,6 @@ | |||
27 | 27 | ||
28 | #include "gr_gm20b.h" | 28 | #include "gr_gm20b.h" |
29 | #include "pmu_gm20b.h" | 29 | #include "pmu_gm20b.h" |
30 | #include "acr_gm20b.h" | ||
31 | 30 | ||
32 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | 31 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> |
33 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> | 32 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 847a0b00..a4dfd07f 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -19,9 +19,13 @@ | |||
19 | #include <linux/dma-mapping.h> | 19 | #include <linux/dma-mapping.h> |
20 | #include <linux/io.h> | 20 | #include <linux/io.h> |
21 | 21 | ||
22 | #include <nvgpu/nvgpu_common.h> | ||
23 | #include <nvgpu/acr/nvgpu_acr.h> | ||
24 | |||
22 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
23 | #include "gk20a/pmu_gk20a.h" | 26 | #include "gk20a/pmu_gk20a.h" |
24 | 27 | ||
28 | #include "gm20b/mm_gm20b.h" | ||
25 | #include "gm20b/acr_gm20b.h" | 29 | #include "gm20b/acr_gm20b.h" |
26 | #include "gp106/acr_gp106.h" | 30 | #include "gp106/acr_gp106.h" |
27 | #include "gp106/pmu_gp106.h" | 31 | #include "gp106/pmu_gp106.h" |
@@ -29,8 +33,6 @@ | |||
29 | #include "sec2_gp106.h" | 33 | #include "sec2_gp106.h" |
30 | #include "nvgpu_gpuid_t18x.h" | 34 | #include "nvgpu_gpuid_t18x.h" |
31 | 35 | ||
32 | #include <nvgpu/nvgpu_common.h> | ||
33 | |||
34 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> | 36 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> |
35 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 37 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
36 | 38 | ||
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.h b/drivers/gpu/nvgpu/gp106/acr_gp106.h index dee01f6b..34d2b117 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.h +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.h | |||
@@ -14,152 +14,11 @@ | |||
14 | #ifndef __ACR_GP106_H_ | 14 | #ifndef __ACR_GP106_H_ |
15 | #define __ACR_GP106_H_ | 15 | #define __ACR_GP106_H_ |
16 | 16 | ||
17 | #include "gm20b/acr_gm20b.h" | ||
18 | |||
19 | #define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin" | 17 | #define GP106_FECS_UCODE_SIG "gp106/fecs_sig.bin" |
20 | #define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin" | 18 | #define GP106_GPCCS_UCODE_SIG "gp106/gpccs_sig.bin" |
21 | #define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin" | 19 | #define GP104_FECS_UCODE_SIG "gp104/fecs_sig.bin" |
22 | #define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin" | 20 | #define GP104_GPCCS_UCODE_SIG "gp104/gpccs_sig.bin" |
23 | 21 | ||
24 | struct loader_config_v1 { | ||
25 | u32 reserved; | ||
26 | u32 dma_idx; | ||
27 | struct falc_u64 code_dma_base; | ||
28 | u32 code_size_total; | ||
29 | u32 code_size_to_load; | ||
30 | u32 code_entry_point; | ||
31 | struct falc_u64 data_dma_base; | ||
32 | u32 data_size; | ||
33 | struct falc_u64 overlay_dma_base; | ||
34 | u32 argc; | ||
35 | u32 argv; | ||
36 | }; | ||
37 | |||
38 | struct flcn_bl_dmem_desc_v1 { | ||
39 | u32 reserved[4]; /*Should be the first element..*/ | ||
40 | u32 signature[4]; /*Should be the first element..*/ | ||
41 | u32 ctx_dma; | ||
42 | struct falc_u64 code_dma_base; | ||
43 | u32 non_sec_code_off; | ||
44 | u32 non_sec_code_size; | ||
45 | u32 sec_code_off; | ||
46 | u32 sec_code_size; | ||
47 | u32 code_entry_point; | ||
48 | struct falc_u64 data_dma_base; | ||
49 | u32 data_size; | ||
50 | u32 argc; | ||
51 | u32 argv; | ||
52 | }; | ||
53 | |||
54 | /*! | ||
55 | * Union of all supported structures used by bootloaders. | ||
56 | */ | ||
57 | union flcn_bl_generic_desc_v1 { | ||
58 | struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; | ||
59 | struct loader_config_v1 loader_cfg_v1; | ||
60 | }; | ||
61 | |||
62 | struct lsf_ucode_desc_v1 { | ||
63 | u8 prd_keys[2][16]; | ||
64 | u8 dbg_keys[2][16]; | ||
65 | u32 b_prd_present; | ||
66 | u32 b_dbg_present; | ||
67 | u32 falcon_id; | ||
68 | u32 bsupports_versioning; | ||
69 | u32 version; | ||
70 | u32 dep_map_count; | ||
71 | u8 dep_map[LSF_FALCON_ID_END * 2 * 4]; | ||
72 | u8 kdf[16]; | ||
73 | }; | ||
74 | |||
75 | struct lsf_wpr_header_v1 { | ||
76 | u32 falcon_id; | ||
77 | u32 lsb_offset; | ||
78 | u32 bootstrap_owner; | ||
79 | u32 lazy_bootstrap; | ||
80 | u32 bin_version; | ||
81 | u32 status; | ||
82 | }; | ||
83 | |||
84 | struct lsf_lsb_header_v1 { | ||
85 | struct lsf_ucode_desc_v1 signature; | ||
86 | u32 ucode_off; | ||
87 | u32 ucode_size; | ||
88 | u32 data_size; | ||
89 | u32 bl_code_size; | ||
90 | u32 bl_imem_off; | ||
91 | u32 bl_data_off; | ||
92 | u32 bl_data_size; | ||
93 | u32 app_code_off; | ||
94 | u32 app_code_size; | ||
95 | u32 app_data_off; | ||
96 | u32 app_data_size; | ||
97 | u32 flags; | ||
98 | }; | ||
99 | |||
100 | struct flcn_ucode_img_v1 { | ||
101 | u32 *header; /*only some falcons have header*/ | ||
102 | u32 *data; | ||
103 | struct pmu_ucode_desc_v1 *desc; /*only some falcons have descriptor*/ | ||
104 | u32 data_size; | ||
105 | void *fw_ver; /*NV2080_CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct*/ | ||
106 | u8 load_entire_os_data; /* load the whole osData section at boot time.*/ | ||
107 | struct lsf_ucode_desc_v1 *lsf_desc; /* NULL if not a light secure falcon.*/ | ||
108 | u8 free_res_allocs;/*True if there a resources to freed by the client.*/ | ||
109 | u32 flcn_inst; | ||
110 | }; | ||
111 | |||
112 | struct lsfm_managed_ucode_img_v2 { | ||
113 | struct lsfm_managed_ucode_img_v2 *next; | ||
114 | struct lsf_wpr_header_v1 wpr_header; | ||
115 | struct lsf_lsb_header_v1 lsb_header; | ||
116 | union flcn_bl_generic_desc_v1 bl_gen_desc; | ||
117 | u32 bl_gen_desc_size; | ||
118 | u32 full_ucode_size; | ||
119 | struct flcn_ucode_img_v1 ucode_img; | ||
120 | }; | ||
121 | struct ls_flcn_mgr_v1 { | ||
122 | u16 managed_flcn_cnt; | ||
123 | u32 wpr_size; | ||
124 | u32 disable_mask; | ||
125 | struct lsfm_managed_ucode_img_v2 *ucode_img_list; | ||
126 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | ||
127 | }; | ||
128 | |||
129 | struct flcn_acr_region_prop_v1 { | ||
130 | u32 start_addr; | ||
131 | u32 end_addr; | ||
132 | u32 region_id; | ||
133 | u32 read_mask; | ||
134 | u32 write_mask; | ||
135 | u32 client_mask; | ||
136 | u32 shadowmMem_startaddress; | ||
137 | }; | ||
138 | |||
139 | /*! | ||
140 | * no_regions - Number of regions used. | ||
141 | * region_props - Region properties | ||
142 | */ | ||
143 | struct flcn_acr_regions_v1 { | ||
144 | u32 no_regions; | ||
145 | struct flcn_acr_region_prop_v1 region_props[T210_FLCN_ACR_MAX_REGIONS]; | ||
146 | }; | ||
147 | |||
148 | struct flcn_acr_desc_v1 { | ||
149 | union { | ||
150 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | ||
151 | } ucode_reserved_space; | ||
152 | u32 signatures[4]; | ||
153 | /*Always 1st*/ | ||
154 | u32 wpr_region_id; | ||
155 | u32 wpr_offset; | ||
156 | u32 mmu_mem_range; | ||
157 | struct flcn_acr_regions_v1 regions; | ||
158 | u32 nonwpr_ucode_blob_size; | ||
159 | u64 nonwpr_ucode_blob_start; | ||
160 | u32 dummy[4]; //ACR_BSI_VPR_DESC | ||
161 | }; | ||
162 | |||
163 | void gp106_init_secure_pmu(struct gpu_ops *gops); | 22 | void gp106_init_secure_pmu(struct gpu_ops *gops); |
164 | 23 | ||
165 | #endif /*__PMU_GP106_H_*/ | 24 | #endif /*__PMU_GP106_H_*/ |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 51e76605..92f99165 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -22,10 +22,8 @@ | |||
22 | #include "gp10b/pmu_gp10b.h" | 22 | #include "gp10b/pmu_gp10b.h" |
23 | 23 | ||
24 | #include "gp106/pmu_gp106.h" | 24 | #include "gp106/pmu_gp106.h" |
25 | #include "gp106/acr_gp106.h" | ||
26 | 25 | ||
27 | #include "sec2_gp106.h" | 26 | #include "sec2_gp106.h" |
28 | #include "acr.h" | ||
29 | 27 | ||
30 | #include <nvgpu/hw/gp106/hw_mc_gp106.h> | 28 | #include <nvgpu/hw/gp106/hw_mc_gp106.h> |
31 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 29 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c index 776bbe85..26facbe3 100644 --- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c | |||
@@ -17,7 +17,7 @@ | |||
17 | #include <linux/dma-mapping.h> | 17 | #include <linux/dma-mapping.h> |
18 | 18 | ||
19 | #include "gk20a/gk20a.h" | 19 | #include "gk20a/gk20a.h" |
20 | 20 | #include "gm20b/mm_gm20b.h" | |
21 | #include "mm_gp10b.h" | 21 | #include "mm_gp10b.h" |
22 | #include "rpfb_gp10b.h" | 22 | #include "rpfb_gp10b.h" |
23 | 23 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h new file mode 100644 index 00000000..00b72d3e --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_flcnbl.h | |||
@@ -0,0 +1,135 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef __ACR_FLCNBL_H__ | ||
14 | #define __ACR_FLCNBL_H__ | ||
15 | |||
16 | #include <nvgpu/flcnif_cmn.h> | ||
17 | |||
18 | #ifndef __NVGPU_ACR_H__ | ||
19 | #warning "acr_flcnbl.h not included from nvgpu_acr.h!" \ | ||
20 | "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" | ||
21 | #endif | ||
22 | |||
23 | /* | ||
24 | * Structure used by the boot-loader to load the rest of the code. This has | ||
25 | * to be filled by NVGPU and copied into DMEM at offset provided in the | ||
26 | * hsflcn_bl_desc.bl_desc_dmem_load_off. | ||
27 | */ | ||
28 | struct flcn_bl_dmem_desc { | ||
29 | u32 reserved[4]; /*Should be the first element..*/ | ||
30 | u32 signature[4]; /*Should be the first element..*/ | ||
31 | u32 ctx_dma; | ||
32 | u32 code_dma_base; | ||
33 | u32 non_sec_code_off; | ||
34 | u32 non_sec_code_size; | ||
35 | u32 sec_code_off; | ||
36 | u32 sec_code_size; | ||
37 | u32 code_entry_point; | ||
38 | u32 data_dma_base; | ||
39 | u32 data_size; | ||
40 | u32 code_dma_base1; | ||
41 | u32 data_dma_base1; | ||
42 | }; | ||
43 | |||
44 | struct flcn_bl_dmem_desc_v1 { | ||
45 | u32 reserved[4]; /*Should be the first element..*/ | ||
46 | u32 signature[4]; /*Should be the first element..*/ | ||
47 | u32 ctx_dma; | ||
48 | struct falc_u64 code_dma_base; | ||
49 | u32 non_sec_code_off; | ||
50 | u32 non_sec_code_size; | ||
51 | u32 sec_code_off; | ||
52 | u32 sec_code_size; | ||
53 | u32 code_entry_point; | ||
54 | struct falc_u64 data_dma_base; | ||
55 | u32 data_size; | ||
56 | u32 argc; | ||
57 | u32 argv; | ||
58 | }; | ||
59 | |||
60 | /* | ||
61 | * The header used by NVGPU to figure out code and data sections of bootloader | ||
62 | * | ||
63 | * bl_code_off - Offset of code section in the image | ||
64 | * bl_code_size - Size of code section in the image | ||
65 | * bl_data_off - Offset of data section in the image | ||
66 | * bl_data_size - Size of data section in the image | ||
67 | */ | ||
68 | struct flcn_bl_img_hdr { | ||
69 | u32 bl_code_off; | ||
70 | u32 bl_code_size; | ||
71 | u32 bl_data_off; | ||
72 | u32 bl_data_size; | ||
73 | }; | ||
74 | |||
75 | /* | ||
76 | * The descriptor used by NVGPU to figure out the requirements of bootloader | ||
77 | * | ||
78 | * bl_start_tag - Starting tag of bootloader | ||
79 | * bl_desc_dmem_load_off - Dmem offset where _def_rm_flcn_bl_dmem_desc | ||
80 | * to be loaded | ||
81 | * bl_img_hdr - Description of the image | ||
82 | */ | ||
83 | struct hsflcn_bl_desc { | ||
84 | u32 bl_start_tag; | ||
85 | u32 bl_desc_dmem_load_off; | ||
86 | struct flcn_bl_img_hdr bl_img_hdr; | ||
87 | }; | ||
88 | |||
89 | /* | ||
90 | * Legacy structure used by the current PMU/DPU bootloader. | ||
91 | */ | ||
92 | struct loader_config { | ||
93 | u32 dma_idx; | ||
94 | u32 code_dma_base; /* upper 32-bits of 40-bit dma address */ | ||
95 | u32 code_size_total; | ||
96 | u32 code_size_to_load; | ||
97 | u32 code_entry_point; | ||
98 | u32 data_dma_base; /* upper 32-bits of 40-bit dma address */ | ||
99 | u32 data_size; /* initialized data of the application */ | ||
100 | u32 overlay_dma_base; /* upper 32-bits of the 40-bit dma address */ | ||
101 | u32 argc; | ||
102 | u32 argv; | ||
103 | u16 code_dma_base1; /* upper 7 bits of 47-bit dma address */ | ||
104 | u16 data_dma_base1; /* upper 7 bits of 47-bit dma address */ | ||
105 | u16 overlay_dma_base1; /* upper 7 bits of the 47-bit dma address */ | ||
106 | }; | ||
107 | |||
108 | struct loader_config_v1 { | ||
109 | u32 reserved; | ||
110 | u32 dma_idx; | ||
111 | struct falc_u64 code_dma_base; | ||
112 | u32 code_size_total; | ||
113 | u32 code_size_to_load; | ||
114 | u32 code_entry_point; | ||
115 | struct falc_u64 data_dma_base; | ||
116 | u32 data_size; | ||
117 | struct falc_u64 overlay_dma_base; | ||
118 | u32 argc; | ||
119 | u32 argv; | ||
120 | }; | ||
121 | |||
122 | /* | ||
123 | * Union of all supported structures used by bootloaders. | ||
124 | */ | ||
125 | union flcn_bl_generic_desc { | ||
126 | struct flcn_bl_dmem_desc bl_dmem_desc; | ||
127 | struct loader_config loader_cfg; | ||
128 | }; | ||
129 | |||
130 | union flcn_bl_generic_desc_v1 { | ||
131 | struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; | ||
132 | struct loader_config_v1 loader_cfg_v1; | ||
133 | }; | ||
134 | |||
135 | #endif /* __ACR_FLCNBL_H__ */ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h new file mode 100644 index 00000000..89edcefa --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_lsfm.h | |||
@@ -0,0 +1,239 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef __ACR_LSFM_H__ | ||
14 | #define __ACR_LSFM_H__ | ||
15 | |||
16 | #ifndef __NVGPU_ACR_H__ | ||
17 | #warning "acr_lsfm.h not included from nvgpu_acr.h!" \ | ||
18 | "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" | ||
19 | #endif | ||
20 | |||
21 | /* | ||
22 | * Falcon Id Defines | ||
23 | * Defines a common Light Secure Falcon identifier. | ||
24 | */ | ||
25 | #define LSF_FALCON_ID_PMU (0) | ||
26 | #define LSF_FALCON_ID_RESERVED (1) | ||
27 | #define LSF_FALCON_ID_FECS (2) | ||
28 | #define LSF_FALCON_ID_GPCCS (3) | ||
29 | #define LSF_FALCON_ID_END (11) | ||
30 | #define LSF_FALCON_ID_INVALID (0xFFFFFFFF) | ||
31 | |||
32 | /* | ||
33 | * Light Secure Falcon Ucode Description Defines | ||
34 | * This structure is prelim and may change as the ucode signing flow evolves. | ||
35 | */ | ||
36 | struct lsf_ucode_desc { | ||
37 | u8 prd_keys[2][16]; | ||
38 | u8 dbg_keys[2][16]; | ||
39 | u32 b_prd_present; | ||
40 | u32 b_dbg_present; | ||
41 | u32 falcon_id; | ||
42 | }; | ||
43 | |||
44 | struct lsf_ucode_desc_v1 { | ||
45 | u8 prd_keys[2][16]; | ||
46 | u8 dbg_keys[2][16]; | ||
47 | u32 b_prd_present; | ||
48 | u32 b_dbg_present; | ||
49 | u32 falcon_id; | ||
50 | u32 bsupports_versioning; | ||
51 | u32 version; | ||
52 | u32 dep_map_count; | ||
53 | u8 dep_map[LSF_FALCON_ID_END * 2 * 4]; | ||
54 | u8 kdf[16]; | ||
55 | }; | ||
56 | |||
57 | /* | ||
58 | * Light Secure WPR Header | ||
59 | * Defines state allowing Light Secure Falcon bootstrapping. | ||
60 | */ | ||
61 | struct lsf_wpr_header { | ||
62 | u32 falcon_id; | ||
63 | u32 lsb_offset; | ||
64 | u32 bootstrap_owner; | ||
65 | u32 lazy_bootstrap; | ||
66 | u32 status; | ||
67 | }; | ||
68 | |||
69 | struct lsf_wpr_header_v1 { | ||
70 | u32 falcon_id; | ||
71 | u32 lsb_offset; | ||
72 | u32 bootstrap_owner; | ||
73 | u32 lazy_bootstrap; | ||
74 | u32 bin_version; | ||
75 | u32 status; | ||
76 | }; | ||
77 | /* | ||
78 | * Bootstrap Owner Defines | ||
79 | */ | ||
80 | #define LSF_BOOTSTRAP_OWNER_DEFAULT (LSF_FALCON_ID_PMU) | ||
81 | |||
82 | /* | ||
83 | * Image Status Defines | ||
84 | */ | ||
85 | #define LSF_IMAGE_STATUS_NONE (0) | ||
86 | #define LSF_IMAGE_STATUS_COPY (1) | ||
87 | #define LSF_IMAGE_STATUS_VALIDATION_CODE_FAILED (2) | ||
88 | #define LSF_IMAGE_STATUS_VALIDATION_DATA_FAILED (3) | ||
89 | #define LSF_IMAGE_STATUS_VALIDATION_DONE (4) | ||
90 | #define LSF_IMAGE_STATUS_VALIDATION_SKIPPED (5) | ||
91 | #define LSF_IMAGE_STATUS_BOOTSTRAP_READY (6) | ||
92 | |||
93 | /*Light Secure Bootstrap header related defines*/ | ||
94 | #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_FALSE 0 | ||
95 | #define NV_FLCN_ACR_LSF_FLAG_LOAD_CODE_AT_0_TRUE 1 | ||
96 | #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_FALSE 0 | ||
97 | #define NV_FLCN_ACR_LSF_FLAG_DMACTL_REQ_CTX_TRUE 4 | ||
98 | #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_TRUE 8 | ||
99 | #define NV_FLCN_ACR_LSF_FLAG_FORCE_PRIV_LOAD_FALSE 0 | ||
100 | |||
101 | /* | ||
102 | * Light Secure Bootstrap Header | ||
103 | * Defines state allowing Light Secure Falcon bootstrapping. | ||
104 | */ | ||
105 | struct lsf_lsb_header { | ||
106 | struct lsf_ucode_desc signature; | ||
107 | u32 ucode_off; | ||
108 | u32 ucode_size; | ||
109 | u32 data_size; | ||
110 | u32 bl_code_size; | ||
111 | u32 bl_imem_off; | ||
112 | u32 bl_data_off; | ||
113 | u32 bl_data_size; | ||
114 | u32 app_code_off; | ||
115 | u32 app_code_size; | ||
116 | u32 app_data_off; | ||
117 | u32 app_data_size; | ||
118 | u32 flags; | ||
119 | }; | ||
120 | |||
121 | struct lsf_lsb_header_v1 { | ||
122 | struct lsf_ucode_desc_v1 signature; | ||
123 | u32 ucode_off; | ||
124 | u32 ucode_size; | ||
125 | u32 data_size; | ||
126 | u32 bl_code_size; | ||
127 | u32 bl_imem_off; | ||
128 | u32 bl_data_off; | ||
129 | u32 bl_data_size; | ||
130 | u32 app_code_off; | ||
131 | u32 app_code_size; | ||
132 | u32 app_data_off; | ||
133 | u32 app_data_size; | ||
134 | u32 flags; | ||
135 | }; | ||
136 | |||
137 | /* | ||
138 | * Light Secure WPR Content Alignments | ||
139 | */ | ||
140 | #define LSF_LSB_HEADER_ALIGNMENT 256 | ||
141 | #define LSF_BL_DATA_ALIGNMENT 256 | ||
142 | #define LSF_BL_DATA_SIZE_ALIGNMENT 256 | ||
143 | #define LSF_BL_CODE_SIZE_ALIGNMENT 256 | ||
144 | |||
145 | #define LSF_UCODE_DATA_ALIGNMENT 4096 | ||
146 | |||
147 | /* | ||
148 | * Supporting maximum of 2 regions. | ||
149 | * This is needed to pre-allocate space in DMEM | ||
150 | */ | ||
151 | #define NVGPU_FLCN_ACR_MAX_REGIONS (2) | ||
152 | #define LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE (0x200) | ||
153 | |||
154 | /* | ||
155 | * start_addr - Starting address of region | ||
156 | * end_addr - Ending address of region | ||
157 | * region_id - Region ID | ||
158 | * read_mask - Read Mask | ||
159 | * write_mask - WriteMask | ||
160 | * client_mask - Bit map of all clients currently using this region | ||
161 | */ | ||
162 | struct flcn_acr_region_prop { | ||
163 | u32 start_addr; | ||
164 | u32 end_addr; | ||
165 | u32 region_id; | ||
166 | u32 read_mask; | ||
167 | u32 write_mask; | ||
168 | u32 client_mask; | ||
169 | }; | ||
170 | |||
171 | struct flcn_acr_region_prop_v1 { | ||
172 | u32 start_addr; | ||
173 | u32 end_addr; | ||
174 | u32 region_id; | ||
175 | u32 read_mask; | ||
176 | u32 write_mask; | ||
177 | u32 client_mask; | ||
178 | u32 shadowmMem_startaddress; | ||
179 | }; | ||
180 | |||
181 | /* | ||
182 | * no_regions - Number of regions used. | ||
183 | * region_props - Region properties | ||
184 | */ | ||
185 | struct flcn_acr_regions { | ||
186 | u32 no_regions; | ||
187 | struct flcn_acr_region_prop region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; | ||
188 | }; | ||
189 | |||
190 | struct flcn_acr_regions_v1 { | ||
191 | u32 no_regions; | ||
192 | struct flcn_acr_region_prop_v1 region_props[NVGPU_FLCN_ACR_MAX_REGIONS]; | ||
193 | }; | ||
194 | /* | ||
195 | * reserved_dmem-When the bootstrap owner has done bootstrapping other falcons, | ||
196 | * and need to switch into LS mode, it needs to have its own | ||
197 | * actual DMEM image copied into DMEM as part of LS setup. If | ||
198 | * ACR desc is at location 0, it will definitely get overwritten | ||
199 | * causing data corruption. Hence we are reserving 0x200 bytes | ||
200 | * to give room for any loading data. NOTE: This has to be the | ||
201 | * first member always | ||
202 | * signature - Signature of ACR ucode. | ||
203 | * wpr_region_id - Region ID holding the WPR header and its details | ||
204 | * wpr_offset - Offset from the WPR region holding the wpr header | ||
205 | * regions - Region descriptors | ||
206 | * nonwpr_ucode_blob_start -stores non-WPR start where kernel stores ucode blob | ||
207 | * nonwpr_ucode_blob_end -stores non-WPR end where kernel stores ucode blob | ||
208 | */ | ||
209 | struct flcn_acr_desc { | ||
210 | union { | ||
211 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | ||
212 | u32 signatures[4]; | ||
213 | } ucode_reserved_space; | ||
214 | /*Always 1st*/ | ||
215 | u32 wpr_region_id; | ||
216 | u32 wpr_offset; | ||
217 | u32 mmu_mem_range; | ||
218 | struct flcn_acr_regions regions; | ||
219 | u32 nonwpr_ucode_blob_size; | ||
220 | u64 nonwpr_ucode_blob_start; | ||
221 | }; | ||
222 | |||
223 | struct flcn_acr_desc_v1 { | ||
224 | union { | ||
225 | u32 reserved_dmem[(LSF_BOOTSTRAP_OWNER_RESERVED_DMEM_SIZE/4)]; | ||
226 | } ucode_reserved_space; | ||
227 | u32 signatures[4]; | ||
228 | /*Always 1st*/ | ||
229 | u32 wpr_region_id; | ||
230 | u32 wpr_offset; | ||
231 | u32 mmu_mem_range; | ||
232 | struct flcn_acr_regions_v1 regions; | ||
233 | u32 nonwpr_ucode_blob_size; | ||
234 | u64 nonwpr_ucode_blob_start; | ||
235 | u32 dummy[4]; /* ACR_BSI_VPR_DESC */ | ||
236 | }; | ||
237 | |||
238 | |||
239 | #endif /* __ACR_LSFM_H__ */ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h new file mode 100644 index 00000000..0f2f66d6 --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objflcn.h | |||
@@ -0,0 +1,82 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef __ACR_OBJFLCN_H__ | ||
14 | #define __ACR_OBJFLCN_H__ | ||
15 | |||
16 | #ifndef __NVGPU_ACR_H__ | ||
17 | #warning "acr_objflcn.h not included from nvgpu_acr.h!" \ | ||
18 | "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" | ||
19 | #endif | ||
20 | |||
21 | struct flcn_ucode_img { | ||
22 | u32 *header; /* only some falcons have header */ | ||
23 | u32 *data; | ||
24 | struct pmu_ucode_desc *desc; /* only some falcons have descriptor */ | ||
25 | u32 data_size; | ||
26 | void *fw_ver; /* CTRL_GPU_GET_FIRMWARE_VERSION_PARAMS struct */ | ||
27 | u8 load_entire_os_data; /* load the whole osData section at boot time.*/ | ||
28 | /* NULL if not a light secure falcon.*/ | ||
29 | struct lsf_ucode_desc *lsf_desc; | ||
30 | /* True if there a resources to freed by the client. */ | ||
31 | u8 free_res_allocs; | ||
32 | u32 flcn_inst; | ||
33 | }; | ||
34 | |||
35 | struct flcn_ucode_img_v1 { | ||
36 | u32 *header; | ||
37 | u32 *data; | ||
38 | struct pmu_ucode_desc_v1 *desc; | ||
39 | u32 data_size; | ||
40 | void *fw_ver; | ||
41 | u8 load_entire_os_data; | ||
42 | struct lsf_ucode_desc_v1 *lsf_desc; | ||
43 | u8 free_res_allocs; | ||
44 | u32 flcn_inst; | ||
45 | }; | ||
46 | |||
47 | /* | ||
48 | * Falcon UCODE header index. | ||
49 | */ | ||
50 | #define FLCN_NL_UCODE_HDR_OS_CODE_OFF_IND (0) | ||
51 | #define FLCN_NL_UCODE_HDR_OS_CODE_SIZE_IND (1) | ||
52 | #define FLCN_NL_UCODE_HDR_OS_DATA_OFF_IND (2) | ||
53 | #define FLCN_NL_UCODE_HDR_OS_DATA_SIZE_IND (3) | ||
54 | #define FLCN_NL_UCODE_HDR_NUM_APPS_IND (4) | ||
55 | |||
56 | /* | ||
57 | * There are total N number of Apps with code and offset defined in UCODE header | ||
58 | * This macro provides the CODE and DATA offset and size of Ath application. | ||
59 | */ | ||
60 | #define FLCN_NL_UCODE_HDR_APP_CODE_START_IND (5) | ||
61 | #define FLCN_NL_UCODE_HDR_APP_CODE_OFF_IND(N, A) \ | ||
62 | (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2)) | ||
63 | #define FLCN_NL_UCODE_HDR_APP_CODE_SIZE_IND(N, A) \ | ||
64 | (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (A*2) + 1) | ||
65 | #define FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) \ | ||
66 | (FLCN_NL_UCODE_HDR_APP_CODE_START_IND + (N*2) - 1) | ||
67 | |||
68 | #define FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) \ | ||
69 | (FLCN_NL_UCODE_HDR_APP_CODE_END_IND(N) + 1) | ||
70 | #define FLCN_NL_UCODE_HDR_APP_DATA_OFF_IND(N, A) \ | ||
71 | (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2)) | ||
72 | #define FLCN_NL_UCODE_HDR_APP_DATA_SIZE_IND(N, A) \ | ||
73 | (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (A*2) + 1) | ||
74 | #define FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) \ | ||
75 | (FLCN_NL_UCODE_HDR_APP_DATA_START_IND(N) + (N*2) - 1) | ||
76 | |||
77 | #define FLCN_NL_UCODE_HDR_OS_OVL_OFF_IND(N) \ | ||
78 | (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 1) | ||
79 | #define FLCN_NL_UCODE_HDR_OS_OVL_SIZE_IND(N) \ | ||
80 | (FLCN_NL_UCODE_HDR_APP_DATA_END_IND(N) + 2) | ||
81 | |||
82 | #endif /* __ACR_OBJFLCN_H__ */ | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h new file mode 100644 index 00000000..a7ea5bba --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/acr_objlsfm.h | |||
@@ -0,0 +1,76 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef __ACR_OBJLSFM_H__ | ||
14 | #define __ACR_OBJLSFM_H__ | ||
15 | |||
16 | #ifndef __NVGPU_ACR_H__ | ||
17 | #warning "acr_objlsfm.h not included from nvgpu_acr.h!" \ | ||
18 | "Include nvgpu_acr.h instead of acr_xxx.h to get access to ACR interfaces" | ||
19 | #endif | ||
20 | |||
21 | #include "acr_flcnbl.h" | ||
22 | #include "acr_objflcn.h" | ||
23 | |||
24 | /* | ||
25 | * LSFM Managed Ucode Image | ||
26 | * next : Next image the list, NULL if last. | ||
27 | * wpr_header : WPR header for this ucode image | ||
28 | * lsb_header : LSB header for this ucode image | ||
29 | * bl_gen_desc : Bootloader generic desc structure for this ucode image | ||
30 | * bl_gen_desc_size : Sizeof bootloader desc structure for this ucode image | ||
31 | * full_ucode_size : Surface size required for final ucode image | ||
32 | * ucode_img : Ucode image info | ||
33 | */ | ||
34 | struct lsfm_managed_ucode_img { | ||
35 | struct lsfm_managed_ucode_img *next; | ||
36 | struct lsf_wpr_header wpr_header; | ||
37 | struct lsf_lsb_header lsb_header; | ||
38 | union flcn_bl_generic_desc bl_gen_desc; | ||
39 | u32 bl_gen_desc_size; | ||
40 | u32 full_ucode_size; | ||
41 | struct flcn_ucode_img ucode_img; | ||
42 | }; | ||
43 | |||
44 | struct lsfm_managed_ucode_img_v2 { | ||
45 | struct lsfm_managed_ucode_img_v2 *next; | ||
46 | struct lsf_wpr_header_v1 wpr_header; | ||
47 | struct lsf_lsb_header_v1 lsb_header; | ||
48 | union flcn_bl_generic_desc_v1 bl_gen_desc; | ||
49 | u32 bl_gen_desc_size; | ||
50 | u32 full_ucode_size; | ||
51 | struct flcn_ucode_img_v1 ucode_img; | ||
52 | }; | ||
53 | |||
54 | /* | ||
55 | * Defines the structure used to contain all generic information related to | ||
56 | * the LSFM. | ||
57 | * Contains the Light Secure Falcon Manager (LSFM) feature related data. | ||
58 | */ | ||
59 | struct ls_flcn_mgr { | ||
60 | u16 managed_flcn_cnt; | ||
61 | u32 wpr_size; | ||
62 | u32 disable_mask; | ||
63 | struct lsfm_managed_ucode_img *ucode_img_list; | ||
64 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | ||
65 | }; | ||
66 | |||
67 | struct ls_flcn_mgr_v1 { | ||
68 | u16 managed_flcn_cnt; | ||
69 | u32 wpr_size; | ||
70 | u32 disable_mask; | ||
71 | struct lsfm_managed_ucode_img_v2 *ucode_img_list; | ||
72 | void *wpr_client_req_state;/*PACR_CLIENT_REQUEST_STATE originally*/ | ||
73 | }; | ||
74 | |||
75 | |||
76 | #endif /* __ACR_OBJLSFM_H__ */ | ||
diff --git a/drivers/gpu/nvgpu/acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h index df90c96e..f207c9ab 100644 --- a/drivers/gpu/nvgpu/acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h | |||
@@ -11,15 +11,60 @@ | |||
11 | * more details. | 11 | * more details. |
12 | */ | 12 | */ |
13 | 13 | ||
14 | #ifndef __ACR_H_ | 14 | #ifndef __NVGPU_ACR_H__ |
15 | #define __ACR_H_ | 15 | #define __NVGPU_ACR_H__ |
16 | 16 | ||
17 | #include "gm20b/mm_gm20b.h" | 17 | #include "gk20a/mm_gk20a.h" |
18 | #include "gm20b/acr_gm20b.h" | 18 | |
19 | #include "gp106/acr_gp106.h" | 19 | #include "acr_lsfm.h" |
20 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | 20 | #include "acr_flcnbl.h" |
21 | #include "acr_t18x.h" | 21 | #include "acr_objlsfm.h" |
22 | #endif | 22 | #include "acr_objflcn.h" |
23 | |||
24 | #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ | ||
25 | |||
26 | #define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */ | ||
27 | |||
28 | #define PMU_SECURE_MODE (0x1) | ||
29 | #define PMU_LSFM_MANAGED (0x2) | ||
30 | |||
31 | struct bin_hdr { | ||
32 | /* 0x10de */ | ||
33 | u32 bin_magic; | ||
34 | /* versioning of bin format */ | ||
35 | u32 bin_ver; | ||
36 | /* Entire image size including this header */ | ||
37 | u32 bin_size; | ||
38 | /* | ||
39 | * Header offset of executable binary metadata, | ||
40 | * start @ offset- 0x100 * | ||
41 | */ | ||
42 | u32 header_offset; | ||
43 | /* | ||
44 | * Start of executable binary data, start @ | ||
45 | * offset- 0x200 | ||
46 | */ | ||
47 | u32 data_offset; | ||
48 | /* Size of executable binary */ | ||
49 | u32 data_size; | ||
50 | }; | ||
51 | |||
52 | struct acr_fw_header { | ||
53 | u32 sig_dbg_offset; | ||
54 | u32 sig_dbg_size; | ||
55 | u32 sig_prod_offset; | ||
56 | u32 sig_prod_size; | ||
57 | u32 patch_loc; | ||
58 | u32 patch_sig; | ||
59 | u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */ | ||
60 | u32 hdr_size; /* Size of above header */ | ||
61 | }; | ||
62 | |||
63 | struct wpr_carveout_info { | ||
64 | u64 wpr_base; | ||
65 | u64 nonwpr_base; | ||
66 | u64 size; | ||
67 | }; | ||
23 | 68 | ||
24 | struct acr_desc { | 69 | struct acr_desc { |
25 | struct mem_desc ucode_blob; | 70 | struct mem_desc ucode_blob; |
@@ -32,9 +77,7 @@ struct acr_desc { | |||
32 | const struct firmware *acr_fw; | 77 | const struct firmware *acr_fw; |
33 | union{ | 78 | union{ |
34 | struct flcn_acr_desc *acr_dmem_desc; | 79 | struct flcn_acr_desc *acr_dmem_desc; |
35 | #ifdef CONFIG_ARCH_TEGRA_18x_SOC | ||
36 | struct flcn_acr_desc_v1 *acr_dmem_desc_v1; | 80 | struct flcn_acr_desc_v1 *acr_dmem_desc_v1; |
37 | #endif | ||
38 | }; | 81 | }; |
39 | struct mem_desc acr_ucode; | 82 | struct mem_desc acr_ucode; |
40 | const struct firmware *hsbl_fw; | 83 | const struct firmware *hsbl_fw; |
@@ -48,4 +91,4 @@ struct acr_desc { | |||
48 | u32 capabilities; | 91 | u32 capabilities; |
49 | }; | 92 | }; |
50 | 93 | ||
51 | #endif /*__ACR_H_*/ | 94 | #endif /*__NVGPU_ACR_H__*/ |