diff options
Diffstat (limited to 'drivers/gpu/nvgpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/soc.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/soc.h | 1 |
3 files changed, 15 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/soc.c b/drivers/gpu/nvgpu/common/linux/soc.c index 305d8bd9..1b27d6f1 100644 --- a/drivers/gpu/nvgpu/common/linux/soc.c +++ b/drivers/gpu/nvgpu/common/linux/soc.c | |||
@@ -12,6 +12,7 @@ | |||
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <soc/tegra/chip-id.h> | 14 | #include <soc/tegra/chip-id.h> |
15 | #include <soc/tegra/fuse.h> | ||
15 | #include <soc/tegra/tegra_bpmp.h> | 16 | #include <soc/tegra/tegra_bpmp.h> |
16 | #ifdef CONFIG_TEGRA_HV_MANAGER | 17 | #ifdef CONFIG_TEGRA_HV_MANAGER |
17 | #include <soc/tegra/virt/syscalls.h> | 18 | #include <soc/tegra/virt/syscalls.h> |
@@ -46,6 +47,13 @@ bool nvgpu_is_bpmp_running(struct gk20a *g) | |||
46 | return tegra_bpmp_running(); | 47 | return tegra_bpmp_running(); |
47 | } | 48 | } |
48 | 49 | ||
50 | bool nvgpu_is_soc_t194_a01(struct gk20a *g) | ||
51 | { | ||
52 | return ((tegra_get_chip_id() == TEGRA194 && | ||
53 | tegra_chip_get_revision() == TEGRA194_REVISION_A01) ? | ||
54 | true : false); | ||
55 | } | ||
56 | |||
49 | #ifdef CONFIG_TEGRA_HV_MANAGER | 57 | #ifdef CONFIG_TEGRA_HV_MANAGER |
50 | /* When nvlink is enabled on dGPU, we need to use physical memory addresses. | 58 | /* When nvlink is enabled on dGPU, we need to use physical memory addresses. |
51 | * There is no SMMU translation. However, the device initially enumerates as a | 59 | * There is no SMMU translation. However, the device initially enumerates as a |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 536d9dcb..df323da1 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <nvgpu/fuse.h> | 31 | #include <nvgpu/fuse.h> |
32 | #include <nvgpu/bug.h> | 32 | #include <nvgpu/bug.h> |
33 | #include <nvgpu/error_notifier.h> | 33 | #include <nvgpu/error_notifier.h> |
34 | #include <nvgpu/soc.h> | ||
34 | 35 | ||
35 | #include "gk20a/gk20a.h" | 36 | #include "gk20a/gk20a.h" |
36 | #include "gk20a/gr_gk20a.h" | 37 | #include "gk20a/gr_gk20a.h" |
@@ -2860,7 +2861,6 @@ int gr_gv11b_init_fs_state(struct gk20a *g) | |||
2860 | u32 data; | 2861 | u32 data; |
2861 | int err; | 2862 | int err; |
2862 | u32 ver = g->params.gpu_arch + g->params.gpu_impl; | 2863 | u32 ver = g->params.gpu_arch + g->params.gpu_impl; |
2863 | u32 rev = g->params.gpu_rev; | ||
2864 | 2864 | ||
2865 | nvgpu_log_fn(g, " "); | 2865 | nvgpu_log_fn(g, " "); |
2866 | 2866 | ||
@@ -2869,9 +2869,9 @@ int gr_gv11b_init_fs_state(struct gk20a *g) | |||
2869 | gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); | 2869 | gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_match_f()); |
2870 | gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); | 2870 | gk20a_writel(g, gr_gpcs_tpcs_sm_texio_control_r(), data); |
2871 | 2871 | ||
2872 | if (ver == NVGPU_GPUID_GV11B && rev == 0xa1) { | 2872 | if (ver == NVGPU_GPUID_GV11B && nvgpu_is_soc_t194_a01(g)) |
2873 | 2873 | { | |
2874 | /* Disable CBM alpha and beta invalidations for l2 for gv11b A01 */ | 2874 | /* Disable CBM alpha and beta invalidations for l2 for t194 A01 */ |
2875 | data = gk20a_readl(g, gr_gpcs_ppcs_cbm_debug_r()); | 2875 | data = gk20a_readl(g, gr_gpcs_ppcs_cbm_debug_r()); |
2876 | data = set_field(data, | 2876 | data = set_field(data, |
2877 | gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(), | 2877 | gr_gpcs_ppcs_cbm_debug_invalidate_alpha_m(), |
@@ -2881,14 +2881,14 @@ int gr_gv11b_init_fs_state(struct gk20a *g) | |||
2881 | gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f()); | 2881 | gr_gpcs_ppcs_cbm_debug_invalidate_beta_disable_f()); |
2882 | gk20a_writel(g, gr_gpcs_ppcs_cbm_debug_r(), data); | 2882 | gk20a_writel(g, gr_gpcs_ppcs_cbm_debug_r(), data); |
2883 | 2883 | ||
2884 | /* Disable SCC pagepool invalidates for gv11b A01 */ | 2884 | /* Disable SCC pagepool invalidates for t194 A01 */ |
2885 | data = gk20a_readl(g, gr_scc_debug_r()); | 2885 | data = gk20a_readl(g, gr_scc_debug_r()); |
2886 | data = set_field(data, | 2886 | data = set_field(data, |
2887 | gr_scc_debug_pagepool_invalidates_m(), | 2887 | gr_scc_debug_pagepool_invalidates_m(), |
2888 | gr_scc_debug_pagepool_invalidates_disable_f()); | 2888 | gr_scc_debug_pagepool_invalidates_disable_f()); |
2889 | gk20a_writel(g, gr_scc_debug_r(), data); | 2889 | gk20a_writel(g, gr_scc_debug_r(), data); |
2890 | 2890 | ||
2891 | /* Disable SWDX spill buffer invalidates for gv11b A01 */ | 2891 | /* Disable SWDX spill buffer invalidates */ |
2892 | data = gk20a_readl(g, gr_gpcs_swdx_spill_unit_r()); | 2892 | data = gk20a_readl(g, gr_gpcs_swdx_spill_unit_r()); |
2893 | data = set_field(data, | 2893 | data = set_field(data, |
2894 | gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(), | 2894 | gr_gpcs_swdx_spill_unit_spill_buffer_cache_mgmt_mode_m(), |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/soc.h b/drivers/gpu/nvgpu/include/nvgpu/soc.h index 3a3490d2..fc7f6341 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/soc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/soc.h | |||
@@ -31,6 +31,7 @@ bool nvgpu_platform_is_simulation(struct gk20a *g); | |||
31 | bool nvgpu_platform_is_fpga(struct gk20a *g); | 31 | bool nvgpu_platform_is_fpga(struct gk20a *g); |
32 | bool nvgpu_is_hypervisor_mode(struct gk20a *g); | 32 | bool nvgpu_is_hypervisor_mode(struct gk20a *g); |
33 | bool nvgpu_is_bpmp_running(struct gk20a *g); | 33 | bool nvgpu_is_bpmp_running(struct gk20a *g); |
34 | bool nvgpu_is_soc_t194_a01(struct gk20a *g); | ||
34 | int nvgpu_init_soc_vars(struct gk20a *g); | 35 | int nvgpu_init_soc_vars(struct gk20a *g); |
35 | 36 | ||
36 | #endif | 37 | #endif |